Patent Application
20050272288
The present invention relates generally to PCI Express connectors.
Personal computers can be connected to various peripheral components using peripheral component interconnect (PCI) connectors. Since its inception in 1992, the PCI bus has become the input/output standard of most computing platforms. Computer central processing units can be connected, using PCI architecture, to hard disk drives, printers, networks, and various other components. This relatively old connector/interface technology, however, has resulted in bottlenecks as newer, higher speed, more powerful computer components have been introduced.
Not surprisingly, the PCI technology has evolved by offloading various functions to higher-bandwidth PCI derivatives, including AGP and PCI-X, both of which are PCI variants. Unfortunately, the PCI bus cannot be easily scaled up in frequency or down in voltage. In addition, the PCI bus does not support features such as advanced power management, native hot plugging/hot swapping of peripherals, or quality of service to guarantee bandwidth for real-time operations. Finally, all of the available bandwidth of the PCI bus is limited to one direction of communication (send or receive) at a time. This is a drawback because many communication networks support simultaneous bidirectional traffic, which minimizes message latency.
A relatively new connector architecture known as PCI express (formerly “3GIO”) has been introduced which uses four wires of two differential pairs to support simultaneous two-way communication. More particularly, PCI express uses a high speed serial link (unlike 32 bit and 64 bit parallel buses) that consists of dual simplex channels, each implemented as a transmit pair and a receive pair for simultaneous transmission in each direction. Each pair consists of two low-voltage, differentially driven pairs of signals. A PCI Express link can be scaled by adding signal pairs to form multiple lanes between two devices, with one bit (x1), four bit (x4), eight bit (x8), and sixteen bit (x16) lane widths being supported.
With that overview of PCI express in mind, the present invention recognizes that the PCI express architecture can support components having connectors (i.e., x1, x4, x8, and x16) of various sizes, ranging from smallest (x1), requiring the fewest connector elements, to the largest (x16) such as some video cards, which requires all 164 connector elements of a PCI express connector. In other words, a single PCI express connector on the motherboard of a computer is expected to support component connectors of various sizes. However, as understood herein some computers and/or their operating systems might not be configured to operate with components having larger (e.g., x16) connectors. Nevertheless, the presence of the single PCI express connector might induce a user to unwittingly plug into the connector an unsupported component, on the erroneous assumption that the component is supported by the computer. This invention is directed to that problem.
A computer connector system includes a peripheral component interconnect (PCI) express connector assembly that has first connector elements and second connector elements at least some of which can be electrically connected to a computer component such as a CPU. A hollow cover is configured for closely receiving the PCI express connector in an interference fit. In accordance with the present invention, the cover defines a top that is solid except for a window which permits access to the first connector elements but not the second when the cover is engaged with the connector.
In non-limiting embodiments the cover has two short sides parallel to each other and two long sides parallel to each other, with each side being orthogonal to its adjoining sides. The cover may also have a substantially completely open bottom opposite the top to receive the connector through the open bottom. The cover may be made of a single unitary piece of plastic.
If desired, the top can bear indicia representing instructions for use. Specifically, the instructions for use can relate to removing the cover. The first and second connector elements together can define a x16 PCI express connector array.
In another aspect, a device is disclosed for rendering a connector array configured to accept relatively large connectors to physically accept only connectors that are smaller than the relatively large connectors. The device includes a hollow unitary plastic body defining a parallelepiped-shaped enclosure configured to closely receive the connector array. The body defines a partially open top which permits access to some but not all connector elements of the connector array when the body is engaged with the connector array.
In still another aspect, a method for impeding misplugs of computer component connectors into a PCI express x16 connector array includes providing a cover having an open bottom and a top opposed thereto, and positioning the cover on the PCI x16 express connector array in close engagement therewith with the top covering some, but not all, connector elements of the PCI express x16 connector array.
The details of the present invention, both as to its structure and operation, can best be understood in reference to the accompanying drawings, in which like reference numerals refer to like parts, and in which:
As used herein, the term “PCI express connector” generally refers to a connector that uses differential pairs of simplex channels in a serial link to support simultaneous two-way communication through the connector, and that can support component connectors of at least two different sizes, unless otherwise more explicitly limited in the claims.
Referring initially to
One or more components 20 (only a single component shown in
Now referring to
The non-limiting body 34 of the cover 26 has two short sides 36 that are parallel to each other and two long sides 38 that are parallel to each other, with each side 36, 38 being orthogonal to its adjoining sides to establish a parallelepiped-shaped structure (and, hence, an interior parallelepiped-shaped enclosure to receive the CPU connector 24). Also, the body 34 has a completely open bottom 40 through which the connector is received.
In accordance with the present invention, opposite the bottom 40, the body 34 of the cover 26 has a rectangular planar top 42, and the top 42 is solid except for a window 44 which is formed therein to permit access to the first connector elements 28 (and if desired, to the key 32) as shown in
It is to be understood that while a single solid segment and single window is shown, the top 42 can have more than one window and more than one solid segment with windows and solid segments alternating with each other, as long as the size of connector sought to be blocked from engagement is indeed blocked. For instance, the cover 100 shown in
It may now be appreciated that the cover 26 renders the CPU connector 24, which is otherwise configured to accept relatively large (e.g., x16 connectors), to physically accept only connectors that are relatively smaller, e.g., x1, x4, x8 connectors, because the top 42 of the cover 26 permits access to some but not all connector elements of the connector array. In this way, the cover 26 impedes misplugs of computer component connectors into the CPU connector 24 in the event that the computer 12 does not support the associated computer components.
While the particular COVER FOR PCI EXPRESS CONNECTOR as herein shown and described in detail is fully capable of attaining the above-described objects of the invention, it is to be understood that it is the presently preferred embodiment of the present invention and is thus representative of the subject matter which is broadly contemplated by the present invention, that the scope of the present invention fully encompasses other embodiments which may become obvious to those skilled in the art, and that the scope of the present invention is accordingly to be limited by nothing other than the appended claims, in which reference to an element in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more”. It is not necessary for a device or method to address each and every problem sought to be solved by the present invention, for it to be encompassed by the present claims. Furthermore, no element, component, or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims. No claim element herein is to be construed under the provisions of 35 U.S.C. §112, sixth paragraph, unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited as a “step” instead of an “act”. Absent express definitions herein, claim terms are to be given all ordinary and accustomed meanings that are not irreconcilable with the present specification and file history.
