Patent Application
20250021323
Embodiments of the present disclosure relate generally to operating autonomous driving vehicles. More particularly, embodiments of the disclosure relate to complex programmable logic device (CPLD) firmware over the air (FOTA) updates for autonomous driving vehicles (ADVs).
Vehicles operating in an autonomous mode (e.g., driverless) can relieve occupants, especially the driver, from some driving-related responsibilities. When operating in an autonomous mode, the vehicle can navigate to various locations using onboard sensors, allowing the vehicle to travel with minimal human interaction or in some cases without any passengers.
Autonomous vehicles can use complex programmable logic devices (CPLDs) to implement various digital logics. CPLD is a type of programmable logic device that is used to implement digital logics. A CPLD has a matrix of programmable logic blocks (PLBs) connected by programmable interconnects, and has input/output blocks (IOBs) for interfacing with external devices. The PLBs contain logic functions and are fully programmable. The IOBs provide I/O interfaces between the CPLD and external devices. IOBs allow signals to enter and exit the CPLD and can be configured as input, output, or bidirectional ports. The programmable interconnects connect the PLBs and IOBs and allow the CPLD to route signals between them. The interconnects are programmable and can be configured to create a wide range of routing paths.
The CPLD also has a configuration memory that stores the configuration data that defines the behavior of the CPLD. The configuration memory typically is a non-volatile memory such as flash memory or electrically erasable programmable read-only memory (EEPROM).
Embodiments of the disclosure are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements.
Various embodiments and aspects of the disclosure will be described with reference to details discussed below, and the accompanying drawings will illustrate the various embodiments. The following description and drawings are illustrative of the disclosure and are not to be construed as limiting the disclosure. Numerous specific details are described to provide a thorough understanding of various embodiments of the present disclosure. However, in certain instances, well-known or conventional details are not described in order to provide a concise discussion of embodiments of the present disclosure.
Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in conjunction with the embodiment can be included in at least one embodiment of the disclosure. The appearances of the phrase “in one embodiment” in various places in the specification do not necessarily all refer to the same embodiment.
According to some embodiments, complex programmable logic devices (CPLDs) employed at an autonomous driving vehicle (ADV) require continuous updates to deploy new features. A firmware over the air (FOTA) update can be applied to CPLDs wirelessly. The autonomous vehicle computing system (or host system) can retrieve new firmware data over the air and load the new firmware data to a temporary data buffer on the CPLD via an I2C slave interface. The host system directs the new firmware data in the temporary data buffer to be transferred to the configuration memory of the CPLD, and instructs the CPLD to load the new firmware data from the configuration memory of the CPLD.
Conventionally, an operator updates the firmware on a CPLD by connecting a physical cable (such as a JTAG connector) of a CPLD to a host system and switches the CPLD to a programmable mode (such as in-system programming (ISP) mode). When in the ISP mode, the logic functions of the CPLD are halted, and the configuration memory of the CPLD is erased and loaded with new configuration data from the host computer. Periodic updates due to modifications and/or new features on multiple CPLDs of an autonomous driving vehicle (ADV) computing system is, however, cumbersome.
A conventional firmware over the air (FOTA) controller can be used for wireless CPLD updates but a FOTA controller for a CPLD uses a significant amount of logic resource from the CPLD and requires additional storage space to store new versions of the firmware locally. Because a CPLD has limited logic resources, a customized FOTA update system/method using the inter-integrated controller (I2C) protocol can minimize CPLD logic resources expenditures.
In some embodiments, an autonomous driving computing platform (or host system) makes available, to a complex programmable logic device (CPLD), an I2C port. The I2C port can be made available directly (e.g., through VGA, DVI, or HDMI ports that use the display data channel (DDC) to communicate, where the DDC uses an I2C interface) or indirectly (e.g., through an I2C interface adapter such as a USB to I2C adapter). The host system acting as an I2C master can push firmware versions to the CPLD that is acting as an I2C slave. In one embodiment, the host system determines a version identifier of the first firmware version at a complex programmable logic device (CPLD) executing a first firmware version. The host system determines a second firmware version for the CPLD is available to the CPLD via a FOTA process, where a version identifier of the second firmware version is different from the version identifier of the first firmware version. The host system performs a write operation to write data blocks corresponding to the second firmware version (e.g., update version) of the CPLD to a memory address of a data buffer of the CPLD in a block-by-block manner. The host system instructs the CPLD to transfer the data blocks corresponding to the second firmware version from the data buffer to a configuration memory of the CPLD and causes the second firmware version at the configuration memory of the CPLD to load onto the CPLD.
In some embodiments, a microcontroller (MCU) can bridge the communication between the host system and the CPLD, where the microcontroller relays the bidirectional communication packets between the host system and the CPLD. Here, the host system and the microcontroller (MCU) can exchange data through Ethernet communication while communication between the MCU and the CPLD can be performed through the I2C protocol. In some embodiments, the microcontroller acts as the I2C master while the CPLD acts as the I2C slave.
I2C refers to a synchronous, multi-master/multi-slave, packet switched, single-ended, serial communication protocol. I2C allows a host system (I2C master) to communicate with one or more I2C slaves (e.g., one or more CPLDs). I2C uses two signal pins. One pin is for data signals (SDA), and another pin is for clock signals (SCL).
An ADV refers to a vehicle that can be configured to in an autonomous mode in which the vehicle navigates through an environment with little or no input from a driver. Such an ADV can include a sensor system having one or more sensors that are configured to detect information about the environment in which the vehicle operates. The vehicle and its associated controller(s) use the detected information to navigate through the environment. ADV 101 can operate in a manual mode, a full autonomous mode, or a partial autonomous mode.
In one embodiment, ADV 101 includes, but is not limited to, autonomous driving system (ADS) 110, vehicle control system 111, wireless communication system 112, user interface system 113, and sensor system 115. ADV 101 may further include certain common components included in ordinary vehicles, such as, an engine, wheels, steering wheel, transmission, etc., which may be controlled by vehicle control system 111 and/or ADS 110 using a variety of communication signals and/or commands, such as, for example, acceleration signals or commands, deceleration signals or commands, steering signals or commands, braking signals or commands, etc.
Components 110-115 may be communicatively coupled to each other via an interconnect, a bus, a network, or a combination thereof. For example, components 110-115 may be communicatively coupled to each other via a controller area network (CAN) bus. A CAN bus is a vehicle bus standard designed to allow microcontrollers and devices to communicate with each other in applications without a host computer. It is a message-based protocol, designed originally for multiplex electrical wiring within automobiles, but is also used in many other contexts.
Referring now to
Sensor system 115 may further include other sensors, such as, a sonar sensor, an infrared sensor, a steering sensor, a throttle sensor, a braking sensor, and an audio sensor (e.g., microphone). An audio sensor may be configured to capture sound from the environment surrounding the ADV. A steering sensor may be configured to sense the steering angle of a steering wheel, wheels of the vehicle, or a combination thereof. A throttle sensor and a braking sensor sense the throttle position and braking position of the vehicle, respectively. In some situations, a throttle sensor and a braking sensor may be integrated as an integrated throttle/braking sensor.
In one embodiment, vehicle control system 111 includes, but is not limited to, steering unit 201, throttle unit 202 (also referred to as an acceleration unit), and braking unit 203. Steering unit 201 is to adjust the direction or heading of the vehicle. Throttle unit 202 is to control the speed of the motor or engine that in turn controls the speed and acceleration of the vehicle. Braking unit 203 is to decelerate the vehicle by providing friction to slow the wheels or tires of the vehicle. Note that the components as shown in
Referring back to
Some or all of the functions of ADV 101 may be controlled or managed by ADS 110, especially when operating in an autonomous driving mode. ADS 110 includes the necessary hardware (e.g., processor(s), memory, storage) and software (e.g., operating system, planning and routing programs) to receive information from sensor system 115, control system 111, wireless communication system 112, and/or user interface system 113, process the received information, plan a route or path from a starting point to a destination point, and then drive vehicle 101 based on the planning and control information. Alternatively, ADS 110 may be integrated with vehicle control system 111.
For example, a user as a passenger may specify a starting location and a destination of a trip, for example, via a user interface. ADS 110 obtains the trip related data. For example, ADS 110 may obtain location and route data from an MPOI server, which may be a part of servers 103-104. The location server provides location services and the MPOI server provides map services and the POIs of certain locations. Alternatively, such location and MPOI information may be cached locally in a persistent storage device of ADS 110.
While ADV 101 is moving along the route, ADS 110 may also obtain real-time traffic information from a traffic information system or server (TIS). Note that servers 103-104 may be operated by a third party entity. Alternatively, the functionalities of servers 103-104 may be integrated with ADS 110. Based on the real-time traffic information, MPOI information, and location information, as well as real-time local environment data detected or sensed by sensor system 115 (e.g., obstacles, objects, nearby vehicles), ADS 110 can plan an optimal route and drive vehicle 101, for example, via control system 111, according to the planned route to reach the specified destination safely and efficiently.
Server 103 can be a FOTA update system that performs firmware update services for one or more clients (e.g., ADVs). For example, software development/production team can upload new firmware updates to server 103. Server 103 can push the new firmware updates to the autonomous driving computing system 110 of autonomous driving vehicle 101.
Some or all of modules 301-308 may be implemented in software, hardware, or a combination thereof. For example, these modules may be installed in persistent storage device 352, loaded into memory 351, and executed by one or more processors (not shown). Note that some or all of these modules may be communicatively coupled to or integrated with some or all modules of vehicle control system 111 of
Localization module 301 determines a current location of ADV 101 (e.g., leveraging GPS unit 212) and manages any data related to a trip or route of a user. Localization module 301 (also referred to as a map and route module) manages any data related to a trip or route of a user. A user may log in and specify a starting location and a destination of a trip, for example, via a user interface. Localization module 301 communicates with other components of ADV 101, such as map and route data 311, to obtain the trip related data. For example, localization module 301 may obtain location and route data from a location server and a map and POI (MPOI) server. A location server provides location services and an MPOI server provides map services and the POIs of certain locations, which may be cached as part of map and route data 311. While ADV 101 is moving along the route, localization module 301 may also obtain real-time traffic information from a traffic information system or server.
Based on the sensor data provided by sensor system 115 and localization information obtained by localization module 301, a perception of the surrounding environment is determined by perception module 302. The perception information may represent what an ordinary driver would perceive surrounding a vehicle in which the driver is driving. The perception can include the lane configuration, traffic light signals, a relative position of another vehicle, a pedestrian, a building, crosswalk, or other traffic related signs (e.g., stop signs, yield signs), etc., for example, in a form of an object. The lane configuration includes information describing a lane or lanes, such as, for example, a shape of the lane (e.g., straight or curvature), a width of the lane, how many lanes in a road, one-way or two-way lane, merging or splitting lanes, exiting lane, etc.
Perception module 302 may include a computer vision system or functionalities of a computer vision system to process and analyze images captured by one or more cameras in order to identify objects and/or features in the environment of the ADV. The objects can include traffic signals, road way boundaries, other vehicles, pedestrians, and/or obstacles, etc. The computer vision system may use an object recognition algorithm, video tracking, and other computer vision techniques. In some embodiments, the computer vision system can map an environment, track objects, and estimate the speed of objects, etc. Perception module 302 can also detect objects based on other sensors data provided by other sensors such as a radar and/or LIDAR.
For each of the objects, prediction module 303 predicts what the object will behave under the circumstances. The prediction is performed based on the perception data perceiving the driving environment at the point in time in view of a set of map/route information 311 and traffic rules 312. For example, if the object is a vehicle at an opposing direction and the current driving environment includes an intersection, prediction module 303 will predict whether the vehicle will likely move straight forward or make a turn. If the perception data indicates that the intersection has no traffic light, prediction module 303 may predict that the vehicle may have to fully stop prior to enter the intersection. If the perception data indicates that the vehicle is currently at a left-turn only lane or a right-turn only lane, prediction module 303 may predict that the vehicle will more likely make a left turn or right turn respectively.
For each of the objects, decision module 304 makes a decision regarding how to handle the object. For example, for a particular object (e.g., another vehicle in a crossing route) as well as its metadata describing the object (e.g., a speed, direction, turning angle), decision module 304 decides how to encounter the object (e.g., overtake, yield, stop, pass). Decision module 304 may make such decisions according to a set of rules such as traffic rules or driving rules 312, which may be stored in persistent storage device 352.
Routing module 307 is configured to provide one or more routes or paths from a starting point to a destination point. For a given trip from a start location to a destination location, for example, received from a user, routing module 307 obtains route and map information 311 and determines all possible routes or paths from the starting location to reach the destination location. Routing module 307 may generate a reference line in a form of a topographic map for each of the routes it determines from the starting location to reach the destination location. A reference line refers to an ideal route or path without any interference from others such as other vehicles, obstacles, or traffic condition. That is, if there is no other vehicle, pedestrians, or obstacles on the road, an ADV should exactly or closely follows the reference line. The topographic maps are then provided to decision module 304 and/or planning module 305. Decision module 304 and/or planning module 305 examine all of the possible routes to select and modify one of the most optimal routes in view of other data provided by other modules such as traffic conditions from localization module 301, driving environment perceived by perception module 302, and traffic condition predicted by prediction module 303. The actual path or route for controlling the ADV may be close to or different from the reference line provided by routing module 307 dependent upon the specific driving environment at the point in time.
Based on a decision for each of the objects perceived, planning module 305 plans a path or route for the ADV, as well as driving parameters (e.g., distance, speed, and/or turning angle), using a reference line provided by routing module 307 as a basis. That is, for a given object, decision module 304 decides what to do with the object, while planning module 305 determines how to do it. For example, for a given object, decision module 304 may decide to pass the object, while planning module 305 may determine whether to pass on the left side or right side of the object. Planning and control data is generated by planning module 305 including information describing how vehicle 101 would move in a next moving cycle (e.g., next route/path segment). For example, the planning and control data may instruct vehicle 101 to move 10 meters at a speed of 30 miles per hour (mph), then change to a right lane at the speed of 25 mph.
Based on the planning and control data, control module 306 controls and drives the ADV, by sending proper commands or signals to vehicle control system 111, according to a route or path defined by the planning and control data. The planning and control data include sufficient information to drive the vehicle from a first point to a second point of a route or path using appropriate vehicle settings or driving parameters (e.g., throttle, braking, steering commands) at different points in time along the path or route.
In one embodiment, the planning phase is performed in a number of planning cycles, also referred to as driving cycles, such as, for example, in every time interval of 100 milliseconds (ms). For each of the planning cycles or driving cycles, one or more control commands will be issued based on the planning and control data. That is, for every 100 ms, planning module 305 plans a next route segment or path segment, for example, including a target position and the time required for the ADV to reach the target position. Alternatively, planning module 305 may further specify the specific speed, direction, and/or steering angle, etc. In one embodiment, planning module 305 plans a route segment or path segment for the next predetermined period of time such as 5 seconds. For each planning cycle, planning module 305 plans a target position for the current cycle (e.g., next 5 seconds) based on a target position planned in a previous cycle. Control module 306 then generates one or more control commands (e.g., throttle, brake, steering control commands) based on the planning and control data of the current cycle.
Note that decision module 304 and planning module 305 may be integrated as an integrated module. Decision module 304/planning module 305 may include a navigation system or functionalities of a navigation system to determine a driving path for the ADV. For example, the navigation system may determine a series of speeds and directional headings to affect movement of the ADV along a path that substantially avoids perceived obstacles while generally advancing the ADV along a roadway-based path leading to an ultimate destination. The destination may be set according to user inputs via user interface system 113. The navigation system may update the driving path dynamically while the ADV is in operation. The navigation system can incorporate data from a GPS system and one or more maps so as to determine the driving path for the ADV.
FOTA update module 308 can receive a firmware version from a remote server, such as server 103, via an application programming interface (API), and perform a FOTA update for local programmable logic devices (e.g., simple programmable logic devices (SPLD), CPLDs, FPGAs, etc.) at the ADV 101.
In some embodiments, the programmable logic devices at an ADS of an ADV can perform a power on or a power reset operation for a peripheral component interconnect express (PCIe) device of the ADS, or perform a power on or power reset operation for one or more sensors of the ADV. The CPLD can also implement signal pre- or post-processing logics for sensor signals or other autonomous driving logic blocks, such as routing, planning, perception, control, etc.
In one embodiment, a microcontroller 401 serves as a forwarding device to bridge the communication between the ADS 110 and CPLDs 403. Here, microcontroller 401 can communicate with ADS 110 wirelessly over ethernet communication or through a physical cable interface (such as the COM or RS232 port of a computing system). Microcontroller 401 can then communicate with CPLDs 403 via an I2C interface. Although
Write submodule 417 can perform a write operation to a memory address of the CPLD. Transfer submodule 419 can move data from data buffer of the CPLD to the configuration (CFG) memory. Reload configuration submodule 421 can cause the CPLD to reload the firmware from the CFG memory. Check complete submodule 423 can check that a firmware version update is complete. Some or all of modules 411-423 may be implemented in software, hardware, or a combination thereof. Some or all of modules 411-423 may be integrated together as an integrated module.
In some embodiments, programmable logic device 403 (such as a CPLD) can implement the logic blocks for I2C slave 501, data buffer 503, reg file 505, and local bus master 507, configuration (CFG) memory interface 509, CSR 511, and CFG memory 513. CFG memory 513 can be a flash memory or an embedded memory that store programming code for the CPLD. Depending on the specific CPLD model being used, some logic blocks may be implemented by external device. For example, some CPLDs may offer external memory interfaces, allowing the CPLD to interface with external cache or memory components.
Referring to
In one embodiment, bitstream data for a firmware update is transferred from host system 110 to data buffer 503 in a block-by-block manner. In one embodiment, each block can be an I2C transaction, e.g., one or two bytes plus an ACK/NACK bit, but other block sizes are possible. Block-by-block transfers is a way of transferring data between the CPLD and external devices (e.g., host system). In block-by-block transfers, the data is transferred one block at a time, where each block containing a fixed number of data words. The transfer of each block is initiated by the CPLD, and the data is transferred until the block is complete.
In one embodiment, when the firmware version is received at data buffer 503. The FOTA logic at local host master instructs the firmware version at data buffer 503 to be moved to CPLD configuration memory in a burst manner (e.g., multiple blocks are transferred at a time). Data buffer burst mode transfer to configuration memory refers to the process of transferring data from the data buffer to the configuration memory in burst mode. The burst mode transfer allows for a high speed CPLD FOTA process. Host system can check settings register (CSR) to determine if a transfer is complete before instructing the CPLD to reload firmware data from configuration memory.
Referring to read operation 603, once host system 110 posts the write operation and the read I2C data block, CPLD peripheral would post the values from the op_addr to 8-bit num_MSB and 8-bit num_LSB. The read operation typically can be used to retrieve register values to determine a status of the CPLD or to determine memory addresses where firmware version data is stored.
In some embodiments, once firmware data is transferred to data buffer. Host system can specify a memory location at reg file corresponding to the CFG memory of the CPLD and initiate local bus master logic to transfer the data from data buffer to the CFG memory. Host system can read CSR or other settings register to check that the transfer is complete (e.g., CPLD is idle). Host system can then cause the CPLD to restart to load the firmware at CFG memory to the CPLD.
At block 809, processing logic causes the second firmware version at the configuration memory of the CPLD to load onto the CPLD. For example, processing logic can power cycle the CPLD or configuration the CPLD into a reconfiguration on-the-fly mode to cause the CPLD to reload the firmware version from configuration memory.
In one embodiment, the second firmware version of the CPLD configures the CPLD to perform a power on or a power reset operation for a peripheral component interconnect express (PCIe) device of an autonomous driving vehicle, or perform a power on or power reset operation for one or more sensors of the autonomous driving vehicle.
In one embodiment, processing logic reads a memory address of a register file, retrieves a value of the register file based on the memory address of the register file, and determines the memory address of the configuration memory based on the value of the register file.
In one embodiment, processing logic receives, from a firmware over the air (FOTA) server, data corresponding to the second firmware version. Processing logic determines an integrity of the received data, including determining a checksum of the received data, and comparing the determined checksum and an expected checksum of the received data.
In one embodiment, the data blocks are transferred from the data buffer to the configuration memory of the CPLD in a burst mode.
In one embodiment, read and write operations are performed by a host system onto the CPLD through a microcontroller, where the microcontroller is configured to forward communication packets between the host system and the CPLD. In one embodiment, the read and write operations are performed according to an I2C protocol.
In one embodiment, a host system communicates with a microcontroller via ethernet communication and the microcontroller communicates with the CPLD through an I2C interface. In one embodiment, the CPLD is configured to a reconfiguration on the fly mode for the FOTA process. In one embodiment, processing logic further retrieves a status of the FOTA process indicating whether the FOTA process completed successfully.
Note that some or all of the components as shown and described above may be implemented in software, hardware, or a combination thereof. For example, such components can be implemented as software installed and stored in a persistent storage device, which can be loaded and executed in a memory by a processor (not shown) to carry out the processes or operations described throughout this application. Alternatively, such components can be implemented as executable code programmed or embedded into dedicated hardware such as an integrated circuit (e.g., an application specific IC or ASIC), a digital signal processor (DSP), or a field programmable gate array (FPGA), which can be accessed via a corresponding driver and/or operating system from an application. Furthermore, such components can be implemented as specific hardware logic in a processor or processor core as part of an instruction set accessible by a software component via one or more specific instructions.
Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the above discussion, it is appreciated that throughout the description, discussions utilizing terms such as those set forth in the claims below, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
Embodiments of the disclosure also relate to an apparatus for performing the operations herein. Such a computer program is stored in a non-transitory computer readable medium. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices).
The processes or methods depicted in the preceding figures may be performed by processing logic that comprises hardware (e.g. circuitry, dedicated logic, etc.), software (e.g., embodied on a non-transitory computer readable medium), or a combination of both. Although the processes or methods are described above in terms of some sequential operations, it should be appreciated that some of the operations described may be performed in a different order. Moreover, some operations may be performed in parallel rather than sequentially.
Embodiments of the present disclosure are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of embodiments of the disclosure as described herein.
In the foregoing specification, embodiments of the disclosure have been described with reference to specific exemplary embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.
