This application claims the benefit of priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2015-0189838, filed on Dec. 30, 2015, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
Field of the Disclosure
The present disclosure relates to a central processing unit (CPU) system, a computing system that includes the CPU system, and a debugging method of the computing system. More particularly, the present disclosure relates to a CPU system that includes debug logic for gathering debug information, a computing system that includes the CPU system, and a debugging method of the computing system.
Background Information
When a computing system operates, a hang-up state of the computing system may occur for various reasons. Sometimes, a hang-up state of a central processing unit (CPU) may also occur. The computing system may record log information about an operation of the computing system. When an error occurs in the computing system, a debugging operation that includes the reason for the occurrence of the error or an analysis of the error may be performed on the basis of the log information to debug the computing system. However, a debugging operation using the log information may not correctly determine information related to an instruction that is performed while a hang-up state of the computing system or CPU occurs. Thus, a lot of time is required for solving an error of the computing system or CPU.
The present disclosure describes a central processing unit (CPU) system that includes debug logic for gathering debug information necessary to quickly perform a debugging operation.
The present disclosure also describes a computing system that includes the CPU system.
Additionally, the present disclosure describes a debugging method of the computing system.
According to an aspect of the present disclosure, a central processing unit (CPU) system includes: a CPU configured to execute a program based on multiple pieces of register information; a CPU hang-up detector configured to detect a hang-up state of the CPU and generate a CPU hang-up occurrence signal; and a memory that stores debug logic configured to gather the multiple pieces of register information from the CPU in response to the CPU hang-up occurrence signal before a reset operation for the CPU is performed.
According to another aspect of the present disclosure, the multiple pieces of register information may include first program counter register information that includes a memory address. An instruction to be currently executed by the CPU is stored at the memory address.
According to yet another aspect of the present disclosure, the multiple pieces of register information may include link register information that includes a memory address. An instruction to be executed by the CPU in response to a branch return instruction is stored at the memory address.
According to still another aspect of the present disclosure, the CPU may include a stack area for storing stack information, wherein the multiple pieces of register information include program state register information that indicates an operation state of the CPU and stack pointer register information that includes a pointer address pointing to the stack information.
According to another aspect of the present disclosure, the debug logic may be configured to provide an operation completion signal to the CPU hang-up detector when an operation of gathering the multiple pieces of register information is completed, wherein the CPU hang-up detector is configured to control performing the reset operation for the CPU in response to the operation completion signal.
According to yet another aspect of the present disclosure, the CPU system may further include a cache unit in which cache data used when the CPU executes the program is stored, wherein CPU hang-up detector is configured to control performing the reset operation for the CPU and control performing an operation of preserving the cache data stored in the cache unit.
According to another aspect of the present disclosure, a computing system includes a central processing unit (CPU) system with a CPU configured to execute a program based on multiple pieces of register information and a debugger configured to debug the CPU system. A debugging method of the computing system includes detecting a hang-up state of the CPU system and generating a CPU hang-up occurrence signal; gathering the multiple pieces of register information from the CPU in response to the CPU hang-up occurrence signal before a reset operation for the CPU system is performed; and debugging, by the debugger, the CPU system based on the gathered pieces of register information.
According to another aspect of the present disclosure, the debugging method may further include: controlling the reset operation of the CPU system after completing the gathering of the multiple pieces of register information.
According to yet another aspect of the present disclosure, the CPU system may further include a cache unit configured to store cache data used when the CPU executes the program, wherein performing the reset operation includes controlling an operation of preserving the cache data stored in the cache unit.
The computing system may further include a memory device configured to store data used when the CPU executes the program, and the debugging method may further include flushing the preserved cache data to the memory device and updating data stored in the memory device.
Exemplary embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.
Hereinafter, example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Embodiments of this disclosure are described so as to be thorough and complete, and to fully convey the concepts described herein to one of ordinary skill in the art. Since the present disclosure may have diverse modified embodiments, preferred embodiments are illustrated in the drawings and are described in the detailed description of the present disclosure. However, this does not limit the concepts described herein within specific embodiments and it should be understood that the present disclosure covers all the modifications, equivalents, and replacements within the idea and technical scope of the concepts described herein. Like reference numerals refer to like elements throughout. In the drawings, the dimensions and size of each structure are exaggerated, reduced, or schematically illustrated for convenience in description and clarity.
The terms used in this application, only certain embodiments have been used to describe, is not intended to limit the present embodiments. In the following description, the technical terms are used only for explain a specific exemplary embodiment while not limiting the present embodiments. The terms of a singular form may include plural forms unless referred to the contrary. The meaning of “include,” “comprise,” “including,” or “comprising,” specifies a property, a region, a fixed number, a step, a process, an element and/or a component but does not exclude other properties, regions, fixed numbers, steps, processes, elements and/or components.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which concepts described herein belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
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Data that is frequently used when the CPU 20 executes a program is stored in the cache unit 50. The cache unit 50 makes it possible to reduce the frequency of access to an external memory device having an input and output speed that is relatively low compared to that of the cache unit 50. The CPU 20 may use cache data, stored in the cache unit 50, when executing a program.
The CPU hang-up detector 30 may receive a program execution result signal ER from the CPU 20 and may detect a hang-up state of the CPU 20 based on the program execution result signal ER. The CPU 20 may periodically transmit the program execution result signal ER to the CPU hang-up detector 30 via a general purpose input output (GPIO) included in the CPU 20. The hang-up state of the CPU 20 may denote a state in which the CPU 20 stops program execution without any reason, or unexpectedly, or the CPU 20 does not execute a program any more when the CPU 20 enters a permanent loop during program execution. In addition, when the CPU 20 is in a hang-up state, the CPU system 10 may also be in the hang-up state. In an embodiment, the CPU hang-up detector 30 may detect that the CPU 20 is in a hang-up state when the program execution result signal ER is not received within a predetermined period of time or when the level of the program execution result signal ER is not changed within a predetermined period of time. However, this is only an embodiment and the CPU hang-up detector 30 may detect the hang-up state of the CPU 20 using a variety of methods. In an embodiment, the CPU hang-up detector 30 may determine whether the CPU 20 is in a hang-up state, by using a watch-dog operation method.
When the hang-up state of the CPU 20 is detected, the CPU hang-up detector 30 may provide a CPU hang-up occurrence signal Osig to the debug logic 40 to inform the debug logic 40 that a hang-up of the CPU 20 has occurred. In an embodiment, the CPU hang-up detector 30 may provide the CPU hang-up occurrence signal Osig to the debug logic 40 before controlling a reset operation for the CPU 20. Then the CPU hang-up detector 30 may not control the reset operation for the CPU 20 until the debug logic 40 receives a predetermined signal.
When the debug logic 40 receives the CPU hang-up occurrence signal Osig, the debug logic 40 may provide a debug information request signal DI_Req for requesting debug information to the CPU 20. The CPU 20 may provide debug information DI to the debug logic 40 in response to the debug information request signal DI_Req. In an embodiment, the debug information DI may include multiple pieces of register information stored in the register unit 24 of the CPU 20. In an embodiment, the debug logic 40 may request program counter register information that includes a memory address. An instruction which the CPU 20 has to presently execute is stored at the memory address. The debug logic 40 may also gather register information including the program counter register information. In another embodiment, the debug logic 40 may request link register information that includes a memory address. An instruction, which the CPU 20 has to execute in response to a branch return instruction, is stored in memory at the memory address. The debug logic 40 may also gather register information that includes the link register information. In another embodiment, the debug logic 40 may request state register information that indicates an operation state of the CPU 20 and stack pointer register information that includes a pointer address pointing to stack information. The debug logic may also gather register information including the state register information and the stack pointer register information. However, this is only an embodiment and the debug logic 40 may request various pieces of register information stored in the CPU 20 and gather the various pieces of register information.
In an embodiment, when the debug logic 40 provides the debug information request signal DI_Req to the CPU 20, the CU 22 may convert a multiple pieces of register information stored in the register unit 24 into a context in response to the debug information request signal DI_Req and provide the context to the debug logic 40. The context may include all pieces of register information used in order for the CPU 20 to execute a program when the CPU receives the debug information request signal DI_Req. Furthermore, the control logic 22 may select at least one of the multiple pieces of register information and convert the selected register information into a context. Debug information DI that is received by the debug logic 40 from the CPU 20 may include the context. The debug logic 40 may store the debug information DI gathered from the CPU 20. Furthermore, the debug logic 40 may include an internal debugger and perform a debugging operation for the CPU 20 based on gathered debug information DI.
The debug logic 40 may provide a gathering operation completion signal Fsig to the CPU hang-up detector 30 when an operation of gathering the debug information DI is completed. The CPU hang-up detector 30 may provide a reset control signal R_CS to the CPU 20 in response to the gathering operation completion signal Fsig. The CPU 20 may be reset in response to the reset control signal R_CS. In addition, in an embodiment, the CPU hang-up detector 30 may selectively target blocks, on which a reset operation is to be performed, before controlling the reset operation. For example, the CPU hang-up detector 30 may selectively target blocks other than the cache unit 50, and not target the cache unit 50 as a target block on which a reset operation is to be performed. Accordingly, the CPU hang-up detector 30 may control performing a reset operation on blocks other than the cache unit 50. Such an operation of the CPU hang-up detector 30 may be referred to as a selective reset operation. In other words, the CPU hang-up detector 30 may perform a reset operation for target blocks that include the decoder 21, the CU 22, the ALU 23, and the register unit 24. Accordingly, data and register information, stored in each target block, may be deleted. In this case, cache data stored in the cache unit 50 may be preserved even after a reset operation for the CPU 20 has been completed. Then, the CPU 20 may perform a flush operation of flushing the cache data stored in the cache unit 50 to an external memory device, thereby updating data of the external memory device.
According to an embodiment, the debug logic 40 may provide gathered debug information DI to a debugger via a joint test action group (JTAG) interface and the like. The debugger may perform a debugging operation for the CPU system 10 or the CPU 20, based on at least one of the debug information DI and updated data stored in the external memory device.
The debug logic 40 may gather register information at a point in time when a hang-up has occurred in the CPU 20 before a reset operation is performed. The debug logic 40 may utilize the gathered register information as debugging information during a subsequent debugging operation. Thus, a time that is required for the debugging operation may be reduced.
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When a hang-up state of a CPU or CPU system is detected, the CPU hang-up detector 200 according to the current embodiment may secure a time. The secured time may be a time required until a debug logic completes gathering register information of the CPU. The secured time may be secured by limiting a reset operation for the CPU or CPU system until a predetermined signal is received from the outside.
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When a hang-up state of a CPU or CPU system occurs, the debug logic 300 according to the current embodiment may gather register information stored in the CPU as debug information. The debug logic 300 may use the gathered register information in a subsequent debugging operation, and thus may quickly correct errors.
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The CPU 400a may use program counter register information, stored in the program counter register 441a, to execute a program. Register information that includes a memory address may be stored in the program counter register 441a (operation {circle around (1)}). An instruction to be executed by the CPU 400a is stored at the memory address. In an embodiment, the memory address may be a memory address for the external memory device EMD connected to the CPU 400a via a bus. For example, the program counter register 451a may store program counter register information, for example, “0x1000”. The “0x1000” may be stored in the address register 443a (operation {circle around (2)}), and the CPU 400a may access the external memory device EMD by using the “0x1000” (operation {circle around (3)}). In an embodiment, the external memory device EMD may include instruction information for the CU 420a and data information related to the instruction information. For example, data, which includes information about a “LOAD” instruction and memory address information with data related to the “LOAD” instruction, that is, memory address information with data such as “0x2000”, may be stored in a memory address “0x1000” of the external memory device EMD. The CPU 400a may read data “LOAD 0x2000” stored in the address “0x1000” of the external memory device EMD and store the read data in the instruction register 442a (operations {circle around (4)} and {circle around (5)}). The decoder 410a may decode the data “LOAD 0x2000” read from the external memory device EMD (operation {circle around (6)}). The CU 420a may receive a decoding result (operation {circle around (7)}) and may read data “1”, stored in the address “0x2000” of the external memory device EMD, based on the decoding result and then store the read data in the data register 444a (operations {circle around (8)} and {circle around (9)}). Also, the CU 420a may control an arithmetic operation of the ALU 430a using the data “1”, based on the decoding result (operations {circle around (10)} and {circle around (11)}).
When a hang-up state occurs in the CPU 400a during the above-described operation (operation {circle around (12)}), the debug logic DL may provide a debug information request signal DI_Req_1 to the CPU 400a. The CPU 400a may provide debug information to the debug logic DL in response to the debug information request signal DI_Req_1. In an embodiment, the debug information DL_1 may include program counter register information stored in the program counter register 441a.
In this manner, the CPU 400a may execute an instruction by using the program counter register information. Accordingly, by referring to the program counter register information when the CPU 400a is in a hang-up state, information about an instruction executed before the CPU 400a is in the hang-up state may be extracted and a debugging operation may be quickly performed by using the extracted information.
Furthermore, when the CPU 400a executes a program by using a pipe-line method, offset information corresponding to the program counter register information may be generated. Then, the CPU 400a may generate register information using the offset information and the program counter register information. The register information may include a memory address in which an instruction that is presently executed by the CPU 400a is stored, by. In other words, when the CPU 400a executes a program by using the pipe-line method, an instruction that is executed by the CPU 400a may be different from the program counter register information. Accordingly, the CPU 400a may generate offset information for correcting the difference, generate register information that includes a memory address using the offset information, and provide the generated register information to the debug logic DL. An instruction that is presently executed by the CPU 400a is stored at the memory address. However, this is only an embodiment, and the debug logic DL may generate the offset information and the register information or an additional logic may generate the offset information and the register information. However, CPUs described herein are not limited thereto.
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For example, in order to execute a program via the sub-function f1, program counter register information that includes a memory address corresponding to “0x0000” may be stored in a program counter register 441b. Similar to the method described above, the memory address corresponding to “0x0000” may be stored in an address register 443b, and “LOAD 0x3000” read from an external memory device EMD may be stored in an instruction register 442b. A data register 444b may store “3” read from the external memory device EMD. Link register information that includes a memory address corresponding to “0x1000” may be stored in the link register 445b in order to execute a program via the main function f0 again in response to a subsequent branch return instruction. In other words, link register information, which includes a memory address may be stored in the link register 445b. An instruction which the CPU 400b has to execute in response to a branch return instruction is stored at the memory address.
When a hang-up state occurs in the CPU 400b, a debug logic DL may provide a debug information request signal DI_Req_2 to the CPU 400b. The CPU 400b may provide debug information DI_2 to the debug logic DL in response to the debug information request signal DI_Req_2. In an embodiment, the debug information DL_2 may include link register information stored in the link register 445b.
In this manner, the CPU 400b may execute an instruction on the basis of the link register information. Accordingly, by referring to the link register information when the CPU 400a is in a hang-up state, the CPU 400b may return to a state before the hang-up state and thus information about an instruction scheduled to be executed may be extracted, and a debugging operation may be quickly performed on the basis of the extracted information.
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When a hang-up state occurs in the CPU 400c, a debug logic DL may provide a debug information request signal DI_Req_3 to the CPU 400c. The CPU 400c may provide debug information DI_3 to the debug logic DL in response to the debug information request signal DI_Req_3. In an embodiment, the debug information DL_3 may include at least one of program status register information and stack pointer register information. Furthermore, the debug information DL_3 may further include stack information stored in the stack area 450c.
In this manner, the CPU 400c may execute an instruction by using the program status register information and the stack pointer register information. Accordingly, by referring to the stack pointer register information when the CPU 400c is in a hang-up state, stack information of the stack area 450c, used before the CPU 400c is in a hang-up state, may be extracted. In addition, since the stack area 450c that is used is changed according to an operating state of the CPU 400c, the stack information may be extracted by referring the program status register information in addition to the stack pointer register information, and a debugging operation may be quickly performed by using the extracted information.
Descriptions provided with reference to
Furthermore, the debug logic DL may select at least one from the program counter register information, the instruction register information, the address register information, the data register information, the link register information, the stack pointer register information, and the program status register information and request the CPUs 400a, 400b, and 400c to send the selected register information.
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When a hang-up state of at least one of the CPUs 720 is detected, the CPU hang-up detector 730 may provide a CPU hang-up occurrence signal Osig to the debug logic 740. The debug logic 740 may provide debug information request signals DI_Reqs to the multiple CPUs 720 in response to the CPU hang-up occurrence signal Osig. The CPUs 720 may provide debug information DIs to the debug logic 740 in response to the debug information request signals DI_Reqs. In an embodiment, the debug information DIs) may include multiple pieces of register information stored in each of the CPUs 720. The debug logic 740 may further include a debug information storage unit 743. The debug information storage unit 743 may be divided into multiple storage areas 743_n corresponding to the CPUs 720, and thus, the debug information storage unit 743 may store the pieces of register information according to the CPUs 720 corresponding thereto.
In another embodiment, the debug logic 740 may select some of the multiple CPUs 720 and provide the debug information request signals DI_Reqs to the selected CPUs. The debug logic 740 may select CPUs in which a hang-up has occurred from among the CPUs 720 or select only CPUs in which a hang-up state occurs more times than a threshold number, and may provide the debug information request signals DI_Reqs to the selected CPUs. Through this operation, the debug logic 740 may reduce the amount of debug information DIs, which is stored in the debug information storage unit 743, by gathering the debug information DIs only from the selected CPUs.
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The computer platform 1000 includes a multi-CPU system 1100, an interface block 1200, and a memory device 1300. According to an embodiment, the computer platform 1000 may further include at least one of a wireless interface block 1400 and a display 1500.
The multi-CPU system 1000 may communicate with the memory device 1300, the wireless interface block 1400, or the display 1500 via the interface block 1200. As described above with reference to
The wireless interface block 1400 may connect the computer platform 1000 to a wireless network, for example, a mobile communication network or a wireless local area network (LAN), via an antenna.
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For example, the I/O ports 2400 may include at least one of a port for connecting to a pointing device such as a computer mouse, a port for connecting to a printer, or a port for connecting to a USB driver. The expansion card 2500 may be implemented as a secure digital (SD) card or a multimedia card (MMC). According to an embodiment, the expansion card 2500 may be a subscriber identification module (SIM) card or a universal subscriber identity module (USIM). The network device 2600 may be a device that may connect the computing system 2000 to a wired network or a wireless network. The display 2700 may display data output from the memory device 2300, the I/O ports 2400, the expansion card 2500, or the network device 1600.
The camera module 2800 is a module that may convert an optical image into an electrical image. Accordingly, an electrical image output from the camera module 2800 may be stored in the memory device 2300 or the expansion card 2500. In addition, an electrical image output from the camera module 2800 may be displayed via the display 2700 according to the control of the multi-CPU system 2100.
While the concepts described herein have been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
Number | Date | Country | Kind |
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10-2015-0189838 | Dec 2015 | KR | national |