Patent Application
20220138544
This disclosure describes a crested barrier device that includes interface switching modulation (ISM) layers enhance the operation of the device.
A modern electronic neural network includes digital and/or analog circuitry that is inspired by, and seeks to approximate, the biological neural networks used by neurological systems found in nature. Like their natural counterparts, electronic neural networks attempt to learn and perform various tasks and recognize input stimuli without being pre-programmed using tasks-specific rules. This learning process may be accomplished using a collection of connected nodes representing artificial neurons which operationally approximate the behavior of neurons in a biological system. Connections between neurons may approximate the behavior of biological synapses to transmit signals between one or more artificial neurons. Multiple successive layers of neuron-and-synapse connections can be chained together to break complex tasks down into incremental stages. Therefore, an electronic neural network can be taught to perform new tasks in the same way that biological neural networks learn and grow over time.
In some embodiments, a crested barrier device with interface switching modulation layers may include a first electrode, a first tunneling layer including cobalt oxide, and one or more interface switching modulation (ISM) layers. The first tunneling layer may be between the first electrode and the one or more ISM layers. Each of the one or more ISM layers may include a layer of hafnium oxide, a layer of silicon oxide having a second dielectric constant; and a monolayer of titanium oxide between the layer of hafnium oxide and the layer of silicon oxide. The device may also include a second electrode the one or more ISM layers are between the one or more ISM layers and the second electrode.
In any embodiments, any and/or all of the following features may be implemented in any combination and without limitation. The first tunneling layer may be approximately 10 nm thick. Layers in the one or more ISM layers may be approximately 1 nm thick. Each of the one or more ISM layers may include material dipoles with polarities that are controlled by a voltage applied across the first electrode and the second electrode.
In some embodiments, a crested barrier device with interface switching modulation layers may include a first electrode, a first tunneling layer comprising a first dielectric constant, and one or more interface switching modulation (ISM) layers. The first tunneling layer may be between the first electrode and the one or more ISM layers. Each of the one or more ISM layers may include a layer of hafnium oxide, a layer of silicon oxide comprising a second dielectric constant where the second dielectric constant maybe at least 1.5 times larger than the first dielectric constant, and a monolayer of titanium oxide between the layer of hafnium oxide and the layer of silicon oxide. The device may also include a second tunneling layer comprising a third dielectric constant. The one or more ISM layers may be between the first tunneling layer and the second tunneling layer. The second dielectric constant may be at least 1.5 times larger than the third dielectric constant. The device may further include a second electrode, where the second tunneling layer may be between the one or more ISM layers and the second electrode.
In any embodiments, any and/or all of the following features may be implemented in any combination and without limitation. The one or more ISM layers may include a plurality of ISM layers. The one or more ISM layers may include three ISM layers. The first dielectric constant may be between approximately 8 and approximately 17. The first dielectric constant may be approximately 4. The device may also include one or more connections to a plurality of other crested barrier devices in a neural network. The device may model a synapse. In some devices, there need be no barrier layer between the first tunneling layer and the one or more ISM layers. The second dielectric constant may be at least 2.5 times larger than the first dielectric constant.
In some embodiments, a method of fabricating a crested barrier device with interface switching modulation layers may include forming a first electrode, forming a first tunneling layer comprising a first dielectric constant, and forming one or more interface switching modulation (ISM) layers. The first tunneling layer may be between the first electrode and the one or more ISM layers. Each of the one or more ISM layers may include a layer of hafnium oxide, a layer of silicon oxide having a second dielectric constant where the second dielectric constant may be at least 1.5 times larger than the first dielectric constant, and a monolayer of titanium oxide between the layer of hafnium oxide and the layer of silicon oxide. The method may also include forming a second tunneling layer comprising a third dielectric constant. The one or more ISM layers may be between the first tunneling layer and the second tunneling layer. The second dielectric constant may be at least 1.5 times larger than the third dielectric constant. The method may additionally include forming a second electrode. The second tunneling layer may be between the one or more ISM layers and the second electrode.
In any embodiments, any and/or all of the following features may be implemented in any combination and without limitation. The first tunneling layer may include cobalt oxide. The first tunneling layer may include titanium oxide having a phase and crystal lattice structure such that the second dielectric constant is less than 10. The first electrode may include a first material and the second electrode may include a second material that is different from the first material. A work function associated with first electrode may be less than a work function associated with the second electrode. The first electrode may include titanium nitrite and the second electrode may include platinum. A tunneling distance may include a length of the crested barrier device layers when 0 V is applied.
A further understanding of the nature and advantages of various embodiments may be realized by reference to the remaining portions of the specification and the drawings, wherein like reference numerals are used throughout the several drawings to refer to similar components. In some instances, a sub-label is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an
After receiving an input signal at the plurality of inputs 102, each of the plurality of inputs 102 may transmit pulses 106 to one or more neurons 104. The neural network 100 illustrates these pathways between the inputs 102 and the neurons 104 as a plurality of synapses 110. In a biological nervous system, a synapse is a structure that permits a neuron or nerve cell to pass an electrical or chemical signal to another neuron. In the neural network 100, biological synapses may be modeled using synapses 110 that pass a signal that is amplified/attenuated by synapse weights between the inputs 102 and the neurons 104 that represents the magnitude of the signal received by the inputs 102. The synapses 110 may also be weighted. For example, a single one of the plurality of inputs 102 may receive an input signal that is weighted differently by the synapses as it is sent to different neurons 104. The weighting of synapses 110 is what allows a neural network to “learn” to recognize specific input patterns and perform specific output tasks. When modeling the synapses 110 in a neural network, they may be represented by a semiconductor device that can receive a plurality of sequential input pulses and generate a corresponding output. For example, each input pulse may cause the synapse output to gradually increase between a logic 0 and a logic 1 level.
The synapses 110 may connect the inputs 102 to one or more neurons 104. These connections may be made in a one-to-many topology between the inputs 102 and the neurons 104. The neurons 104 in the neural network may be modeled after biological neurons, which are electrically excitable cells that communicate with other cells between connecting synapses. After receiving a sufficient number of input impulses, a neuron 104 may “fire” or transition into an excited state. The state may be associated with a sensory response (e.g., touch, sound, light, etc.) and/or motor controls from the brain. To approximate the behavior of a biological neuron, the neurons 102 in the neural network 100 may be implemented using any device that can receive a plurality of input pulses from one or more synapses 110, and after receiving a threshold number of input pulses, cause the outputs 108 of the neurons 104 to toggle between logic 0 and logic 1 states.
A neural network represents only one of many applications that may utilize the devices described in detail below. It should be understood that the example of a neural network is not meant to be limiting, but provides just one example of an operating environment that may benefit from the low-power characteristics of these devices.
Many different devices may be used to represent synapses in the circuit network 200. In some embodiments, the synapses 202 may be implemented using semiconductor devices that can receive a plurality of input pulses and provide a proportional output to the neurons 204. Additionally, the neurons 204 may also be represented by discrete circuit devices. However, in contrast to the synapses 202 that gradually change their conductance with arriving excitation pulses, the neurons 204 may be configured to receive a plurality of pulses from the synapses 202 and fire after threshold number of pulses have been received. This basic network of circuit connections between the inputs 206 and the output neurons 204 may be augmented using hidden layers of transistors and/or other two-terminal resistive devices representing hidden layers of neurons and synapses as described above. When implementing the circuit network 200, it therefore may be beneficial to use semiconductor devices that can implement both the analog behavior of the synapses and the digital behavior of the neurons.
In some embodiments, many different types of devices may be used to implement the basic components of a neural network. For example, some embodiments may use a specific type of transistor known as a ferroelectric field-effect transistor (FeFET). A FeFET is a logic transistor that can maintain its logical state even when power is removed. FeFETs are similar to traditional metal oxide silicate (MOS) transistors, except that the logic gate dielectric is replaced with a ferroelectric material, which is a dielectric that “remembers,” or stores electric fields to which it has been exposed. In a FeFET, a persistent dipole may be formed within the gate dielectric itself, thereby splitting the threshold voltage of the FeFET into two stable states that can represent binary logic states. Other embodiments may use ferroelectric FinFET devices.
In the embodiments described herein, the synapses may be represented by individual two-terminal memory elements. When using memory devices to model synapses, the circuit network 200 may be viewed as a form of non-volatile memory array. Each of the memory elements representing synapses 202 may be arranged in a rectangular grid pattern. In some embodiments, the grid pattern may be three-dimensional such that multiple grids lie above and below each other, as in a crosspoint memory array. Each of the memory elements may be configured to receive an applied voltage, and based on the polarity of the applied voltage, the memory elements representing the synapses 202 may change a physical state of a material in the memory element to represent a saved logic state, such as a logic 1 and a logic 0. When the voltage is no longer applied, the memory elements 202 may save the logic state induced by the applied voltage, and thus may operate as non-volatile memory elements.
In order to apply the voltage needed to read/write to the memory elements, signals may be received from the horizontal lines from the plurality of inputs 206. These horizontal lines may act as a word line in a traditional memory array. The bit lines may run in a perpendicular direction and connect to the output neurons 204. Therefore, applying a voltage between a single one input of the word lines and a single input of the bit lines may cause voltage to be applied across a single one of the memory elements representing synapses 202. This process can be used to select a single synapse 202 for a read and/or write operation.
Many different technologies may be used to implement the memory device 212, such as phase-change memories (PCMs), oxide-resistive random-access memory (oxRRAMs) or conductive-bridging memories (CBRAM) to name a few. The embodiments described herein may use a specific type of memory device known as a resistive random-access memory (ReRAM). A ReRAM is a type of non-volatile, random-access computer memory that operates by changing a resistance across a dielectric solid-state material. Generally, filamentary ReRAM devices generate oxygen ion/vacancy pairs in an oxide layer. These oxide ions/vacancies can subsequently conduct electrical current while oxygen ions can drift under an electric field. The motion of oxygen atoms through these vacancies in the oxide is similar to the motion of electrons and holes in a traditional semiconductor device. Applying a voltage to the ReRAM device generates these oxide vacancies to decrease the resistance of the device. When the voltage is removed, the oxide vacancies may remain in place and thereby store a nonvolatile state of the conductance level of the ReRAM device.
Some specific ReRAM devices may be referred to as bulk ReRAM devices. Bulk ReRAM devices may change a conductance state by moving species (vacancies, ions, etc.) from one side to other side of the device. Bulk ReRAM devices may be used to mimic the specific type of synaptic behavior in a neural network as described above. Specifically, bulk-switching ReRAM devices may exhibit an analog response to received input pulses. As more input pulses are received by the device, the mobile species may gradually start to move from one part of the device to other part of the ReRAM device, and consequently the resistance of the device will gradually decrease. By gradually applying voltage pulses to the ReRAM device, the conductivity of the ReRAM device may be modulated in an analog fashion depending on the polarity, frequency, and duration of the applied voltage pulses. When used in this fashion, ReRAM devices may provide a very compact circuit footprint for mimicking synaptic behavior in the circuit network 200.
The active layer of the memory 300 may include a plurality of ions (or any other charged, mobile species, such as oxygen vacancies) 308 in the active layer 306. The active layer 306 may be formed using any transitional metal oxide (TMO) with high ionic mobility—or any TMO doped with other material incorporated in host lattice—having a relatively high dielectric constant and a relatively high defect and ionic mobility. For example, some embodiments may use titanium oxide and doped titanium oxide as an active layer 306. The ions 308 may include negative oxygen ions or positively charged oxygen vacancies that reside between the crystal lattice of the titanium oxide in the active layer 306. Without a voltage being applied across the bottom electrode 302 on the top electrode 304, the ions or any other mobile species 308 may reside near the center or at any other position of the active layer 306. The location of the mobile species 308 is illustrated by the peak 312 of the band diagram 310 that increases as the ions 308 are approached, then decreases as the band diagram 310 moves from the bottom electrode 302 to the top electrode 304. In some embodiments, the position of the mobile species 308 may be associated with a logical 0 for the memory active layer 300.
The energy levels of the various regions of the band diagram 310 may be characterized according to a vacuum level 356. Each of the electrodes 302, 304 may be characterized by a work function 350, 354 defining the energy to be transferred to the electron to ionize the electron to the vacuum level. The work function difference between the electrodes 302, 304 and the vacuum level 356 may represent a work function differential between the two electrodes. Similarly, the energy level of the active layer 306 may be characterized by an electron affinity 352 defining the energy difference between the conduction band of the active layer 306 and the vacuum level 356.
The active layer 508 may be between approximately 6 nm and approximately 13 nm thick. For example, the active layer 508 may be 6 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, and/or the like in width. The combined width of the amorphous silicon layer 504 and the silicon dioxide layer 506 may be between approximately 1 nm and approximately 5 nm. For example, the combined width may be between approximately 1 nm-2 nm, 2 nm-3 nm, 3 nm-4 nm, 4 nm-5 nm, and/or the like. The amorphous silicon layer 504 may act as a selector device, the silicon dioxide layer 506 may act as a barrier layer, and the titanium oxide layer 508 may act as an active layer. This creates a combined selector and memory device (i.e., a self-rectifying memory device) with a barrier.
An additional problem with the memory device described above is that the voltage level required to cause the movement of ions from one position in active layer to another position is approximately 4 V or higher, as illustrated by voltage 608 in graph 600. The embodiments described herein also shift the peak voltage 608 required to move ions in the device to the left (e.g., to lower voltages), thus compressing the clockwise and counterclockwise voltage path illustrated in the graph 600. This allows the device to be fully operated with lower voltage levels, thus reducing the power required for the memory array or neural network as a whole. While the performance is improved over the devices described in the figures above, this device 500 still has a number of drawbacks that prevent it from being optimal for use in neural networks. Specifically, the device 500 does not exhibit a high degree of selectivity. The current increase is still too abrupt and large as a small amount of voltage is applied across the device, which leads to a large leakage current when devices around the device 500 are activated in the neural network. Additionally, as illustrated in
To solve these and other problems, some embodiments may combine the barrier layer 506 and the active layer 508 into a single layer that acts as both a barrier and an active layer simultaneously.
For example, as an electron 730 enters the conduction band of the tunneling self-rectifying layer 722, it will be stopped by the relatively large energy band and thickness of the active layer 708. This energy band forms a barrier over which the electron 730 must proceed in order to get to the bottom electrode 704. The energy band of the active layer 708 may be overcome by applying a voltage sufficient to lift the energy of the electron 730 over the energy band of the active layer 708. Tunneling through the barrier of the active layer 708 is unlikely given the magnitude of the energy band of the active layer 708 compared to the energy of the electron 730 in the self-rectifying tunneling layer 722. Essentially, this difference between the energy band levels of the tunneling layers 722, 724 and the active layer 708 acts as a barrier to replace the large silicon dioxide barrier found in previous devices. Furthermore, the dielectric constant of the tunneling layers 722, 724 may be significantly lower than the dielectric constant of the active layer 708 as described below. The difference between the conduction band offsets may be at least 0.7 eV (the electron affinity of the tunneling self-rectifying layers may be higher), while the valence band offset may be relatively small or even negative. For example, holes may see a barrier when tunneling from the active layer to the tunneling oxide. Thus, the valence band of tunneling layer may be energetically lower compared to valence band of active region.
Examining the energy bands of
The drop in operating voltage for the crested barrier device may be understood in comparison to the device of
One way to characterize the crested barrier device in
In addition to characterizing the active layer 708 in comparison to the tunneling layers 722, 724 by differences in the dielectric constants, some embodiments may also characterize the active layer 708 by comparing the relative electron affinity between the active layer 708 and the tunneling layers 722, 724. For example, for an active layer of TiOx, the electron affinity will be approximately 3.4 eV to 4.0 eV. In comparison, the Co3O4 used in the tunneling layers 722, 724 may have an electron affinity of approximately 4.8 eV-5.5 eV. Generally, the electron affinity of the tunneling layers 722, 724 may be higher than the electron affinity of the active layer. In some embodiments, the electron affinity of the tunneling layers 722, 724 may be greater than 4.8 eV, while the electron affinity of the active layer 708 may be less than approximately 4.0 eV. Some embodiments may also tune the electron affinity and alignment of the various energy bands by doping the active layer TiOx with other materials, such as C, Cr, Mo, W, C, N, Nb, Ta, Zr, Hf, S, Se, P, and/or the like.
In another embodiment, the tunneling layers 722, 724 may be replaced with amorphous silicon or MnO3 or CrO3 or V2O5, WO3, NiO, Cr2O3, SnS2, or any other high-affinity, small-bandgap oxide, rather than cobalt oxide. Moreover, by alloying using different materials new tunneling barriers can be engineered as described below. In these embodiments, the dielectric constant of the tunneling layers 722, 724 may be lowered to approximately 4. As described above, the dielectric constant of the active layer 708 using titanium oxide is approximately 30 to approximately 60. In this embodiment, the dielectric constant of the active layer 708 may be between approximately 7 times greater and 15 times greater than the dielectric constant of the tunneling layers 722, 724.
In another embodiment, titanium oxide may be used as the tunneling layers 722, 724. However, a different form of crystal lattice for the titanium oxide may be used such that the dielectric constant of the tunneling layers 722, 724 is approximately 25. The crystal lattice of the titanium oxide can come in various forms depending on its phase and how it is grown. Depending on the crystal lattice and the phase, the dielectric constant of different forms of titanium oxide can range from 12-100. In this embodiment, the titanium oxide has a much lower dielectric constant and does not act as an active layer. Instead, doped hafnium oxide may be used as the material for the active layer 708, which has a dielectric constant of approximately 40. In these embodiments the dielectric constant of the active layer 708 may be between approximately 1.5 and approximately 2.5 times greater than the dielectric constant of the active layer which in turn can reduce the operating voltage even more.
In some embodiments, TiOx may be used as an active layer, and alloying different materials may be used to create a tunneling layer. Alloying may include the direct chemical combination of different oxides. The combination of a few high-affinity oxides may be used to create a tunneling layer while maintaining the crested barrier shape illustrated in
Although
In some embodiments, different materials for the top electrode and the bottom electrode may be used such that there is a work function differential between the two electrodes. The work function of a metal electrode is similar to, or higher than the electron affinity for the tunneling layer and other layers in the device. In other words, the work function of the metal electrode corresponds to the amount of energy required for an electron to break free of the material and ionize to the vacuum energy level.
For example, the top electrode 702 may be constructed by depositing a layer of platinum. Instead of using a layer of platinum for the bottom electrode 704, the bottom electrode 704 may be formed using a different material having a different work function. In this example, the bottom electrode 704 may be constructed by depositing a layer of titanium nitrite, which has a work function that is less than the work function of the top electrode 702 made of platinum. This creates a differential between the two work functions that may be balanced by shifting the energy bands of the other layers in the band diagram 800. For example, if the work function of the bottom electrode 704 is 4.6 eV, and the work function of the top electrode 706 is 5.6 eV, and the length of the tunneling layers 722, 724 and the active layer 708 are approximately 10 nm, this work function differential will generate an electric field of 1.0 MV/cm across the device. Because the natural state of the device will tend to pull the potential of both electrodes to the same level (e.g., 0 V), the rest of the band diagram may tend to bend to create this equilibrium. This workfunction differential may be used for tuning the position of the lobe described in
Creating a work function differential between the top electrode 702 and the bottom electrode 704 affects the operation of the crested barrier device in a number of ways. First, this induces an electric field across the device 900 in order to maintain 0 V at both electrodes 702, 704. This induced electric field can require additional voltage to be applied to the device before it begins to conduct. The applied voltage may need to first overcome the induced electric field before conduction begins. Thus, at the low voltage levels typically seen in memory arrays or in neural networks, the device will not begin to conduct the relatively high levels of leakage current illustrated in
In addition to inducing an electric field, the work function differential between the bottom electrode 704 and the top electrode 702 may also cause the ions 710 in the active layer to move to one side of the active layer 708. The magnitude of the leakage current is at least partially dependent on the position of the ions 710. The induced electric field creates an internal bias in the device that delays the movement of the ions 710 to the towards the opposing electrode. This delay keeps the leakage current low until a higher voltage is applied. In some embodiments, a work function difference of at least 0.2 eV may be used between the top and bottom electrodes. In other embodiments, the work function difference may be approximately 0.2 eV-0.5 eV, approximately 0.3 eV-0.6 eV, and so forth. Differentials greater than 0.6 eV may lose memory retention as the field generated may be strong enough that even at 0 V applied, the ions may be pushed completely to the other side of the device.
The advantages of the crested barrier device are evident in these diagrams. First, the operating voltage of the device is reduced to approximately 2.6 V when fully conducting. Additionally, the leakage current at less than 0.5 V is very small in comparison to other devices. When a voltage is initially applied to the device, the device begins conducting at location 810 in graph 800 of
As the device begins to conduct, the ions (or any other mobile species) will move to one side according to the direction of the voltage applied.
The examples described above apply a single voltage across the device to illustrate the behavior of the device. However, these embodiments are also fully functional when voltage pulses are applied to the device instead of or in addition to constant voltages. The progression around the various CW and CCW voltage and current pathways illustrated in
More selectivity makes the crested barrier device ideal for large arrays, and increasing of the lobe and ON/OFF ratio makes it ideal for multi-state memory implementations. When the lobe 1202 is large enough, multiple states 1206 may be readily distinguished in the lobe 1202. Instead of simply providing a binary 0/1 set of states for a traditional binary memory. Some embodiments may include a plurality of states 1206 in between the 0/1 states at both ends of the lobe 1202. As described above, because the device is responsive to individual voltage pulses, predetermined voltage levels may be applied to the device to generate a current response at one of the desired intermediate states 1206.
The method may also include forming a first tunneling layer (1304). The first tunneling layer may be formed on top of the first electrode. In some embodiments, no intervening layers may be included between the first electrode and the first self-rectifying layer. The first self-rectifying layer may be deposited as a layer of a cobalt oxide, such as Co3O4. Some embodiments may also use a layer of amorphous silicon or any other high-affinity oxide. Some embodiments may instead use a layer of titanium oxide. Layers of titanium oxide may be used that have a phase and/or crystal lattice that generates a relatively low dielectric constant in comparison to the active layer described below.
The method may also include forming an active layer (1306). The active layer may be formed on top of the first tunneling layer, and may be formed using any known process for forming an active layer. In some embodiments, no intervening layers may be formed between the first tunneling layer and the active layer. Specifically, some embodiments do not include a barrier layer or a layer of silicon dioxide between the active layer and the first self-rectifying layer. The active layer may be formed out of titanium oxide, TaOx/T2O5 oxide or BiFeO3, and may be formed using deposition processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or the like. The active layer may be formed to have any of the characteristics described above in this disclosure. For example, the active layer may have its doping controlled to produce at least a minimum dielectric constant. Doping may be controlled by controlling the power with which titanium and/or oxygen are added to a deposition vapor. The active layer may be formed to have a dielectric constant that is at least 1.5 times larger than the first self-rectifying layer. In some embodiments, the active layer may be formed from hafnium oxide. The active layer may be configured to have a phase and crystal lattice structure to provide a dielectric constant that is higher than the dielectric constant of the first self-rectifying layer as described above. Additional comparisons between these dielectric constants are disclosed above.
The method may also include forming a second tunneling layer (1308). The second tunneling layer may be formed on top of the active layer. In some embodiments, no intervening layers may be included between the active layer and the second tunneling layer. The second tunneling layer may be deposited as a layer of a cobalt oxide, such as Co3O4. Some embodiments may also use a layer of amorphous silicon or any other high-affinity oxide. Some embodiments may instead use a layer of titanium oxide. Layers of titanium oxide may be used that have a phase and/or crystal lattice structure that generates a relatively low dielectric constant in comparison to the active layer described above. A second electrode or top electrode may then be added having a higher work function than the first or bottom electrode (1310) as described above.
Some of the embodiments described herein may use a ferroelectric device combined with additional layers that provide interface switching modulation (ISM) effect to overcome these challenges by overcompensating for the parasitic charge trapping and creating a memory window in a hybrid ferroelectric device that is large enough to represent more than four states and enable the reliable operation of a memory device with more than a 2-bit capacity. The ISM layers that may be added to a ferroelectric device may create material dipoles that react to applied voltages in much the same way that ferroelectric dipoles react to applied voltages. However, the material dipoles in the ISM layers tend to interact constructively with the effect of the ferroelectric dipoles. Both the ferroelectric dipoles in the material dipoles have an effect that moves around the threshold voltage of device in a counterclockwise direction. Therefore, instead of the countering effect of the ferroelectric dipoles like the charge trapping phenomena described above, these embodiments instead increase the size of the memory window by additively combining the effects of the ferroelectric dipoles and the material dipoles.
In addition to additively increasing the memory window, the ISM material dipole described below is reversible, such that they may be both reset and set to represent binary 0 and binary 1 levels. The ISM materials may also follow the reversibility and reorientation of the ferroelectric dipole. The resulting dipoles caused by both the ferroelectric material and the ISM layers may generate individual internal electric fields oriented in the same direction. The individual electric fields may combine their effective strength additively to form an overall internal electric field within the active layers (ferroelectric and ISM) of the device. This overall internal electric field may be used for the development of enhanced ferroelectric tunnel junction devices (ISM e-FTJs) where the ISM layers are used as an enhancer of the polarization in the ferroelectric tunnel junction. These materials may also be used to form enhanced ferroelectric field effect transistors (ISM e-FeFETs) where the ISM layers enhance the internal field generated by polarization of the ferroelectric material within the FeFET.
The hafnium oxide 1402 may have a strong affinity for oxygen ions. Therefore, the hafnium oxide may remove oxygen ions from the silicon oxide 1406 such that the silicon oxide 1406 becomes depleted. The result is an excess of oxygen ions in the ISM layers. Additionally, because the titanium oxide exists as a monolayer as ions, an excess of titanium ions may also roam freely in this area around the other materials. Therefore, the resulting material in the gate device has available titanium ions and oxygen ions.
When a negative voltage is applied to the gate 1410, the positive titanium ions will be attracted to the top of the gate 1410, while the negative oxygen ions will be repelled towards the bottom of the gate towards the channel 1408. This effectively creates a dipole using the positive titanium ions and the negative oxygen ions. This dipole forms an electric field in the device and in turn changes the conductivity of the channel 1408 to a positive polarity by attracting majority carriers and setting the device into an accumulation mode in the case of p-type semiconductors. In consequence, a threshold voltage shift toward higher gate voltages or a higher voltage may be need to be applied to a gate of the device to turn on the transistor.
Each of the individual layer combinations illustrated in
As the strength of the internal electric field 1540 increases, its impact on inversion and accumulation of channel, and its effect on the memory window for the device may also increase. Not only is the electric field 1540 strengthened, but the effect of the reversal of this internal electric field 1540 during program/erase cycles is counterclockwise in the drain-current/gate voltage hysteresis diagram, which aligns with the counterclockwise effect of the ferroelectric dipoles described above.
Each combination of a hafnium oxide layer, a titanium oxide monolayer, and a silicon oxide layer may be referred to herein as an ISM layer. For example, layers 1504, 1520, and 1512 may form a first ISM layer; layers 1510, 1522, and 1508 may form a second ISM layer; and layers 1506, 1524, and 1504 may form a third ISM layer. Throughout this disclosure, any instance of a single ISM layer may be replaced with multiple ISM layers. Single ISM layers are illustrated in most of the figures for the sake of clarity. However, in any embodiment and in any of the examples described herein, a single ISM layer may represent one or more ISM layers stacked on top of each other without limitation.
In additional to multiple ISM layers being present within the device 1500 that are not specifically illustrated in
The vertical axis of the band diagram 1700 illustrates the thickness of the various layers. In this embodiment, each of the layers is approximately 2 nm thick. Other embodiments may increase or decrease this thickness. For example, some embodiments may use silicon-based layers 1512, 1508, 1504 that have a greater/lesser thickness than the hafnium-based layers 1514, 1510, 1506, while other embodiments may be fabricated such that each of the silicon-based layers and hafnium-based layers are approximately the same thickness. The thickness of each layer may range from between approximately 1 nm and approximately 15 nm. Increasing the thickness of each of the layers beyond the 2 nm illustrated in
Although hafnium oxide, silicon oxide, and titanium oxide are used as examples for materials in the ISM, other materials having similar properties may be used as substitutes. In any embodiments, the hafnium oxide may be replaced with materials such as ZrOx, HfOx, ZrOx doped with various elements such as Si, Al, Y, Sr, Gd, N, La, and/or any combination of these materials.
A number of different device applications are possible that use the ISM layers described above to enhance the effects of semiconductor devices. For example, ISM layers may be combined with ferroelectric layers to enhance the effect of the ferroelectric layers. Ferroelectric dipoles may be present in ferroelectric layers, and the polarity of these ferroelectric dipoles may be controlled by the direction of an applied voltage through the ferroelectric layer. When combined with ISM layers, the internal electric field generated by the ferroelectric dipoles may be enhanced by material dipoles formed in the ISM layers. As described above, the ISM layers tend to form material dipoles in response to an applied voltage. The internal electric field formed by these material dipoles may be aligned in the same direction with the internal electric fields formed by the ferroelectric dipoles such that they enhance the cumulative internal electric field effects. The stronger internal electric field may be used to increase a memory window of the device, or to increase the magnitude of the bending of the energy bands in tunnel junction devices.
In some embodiments, ISM layers may be combined with the crested barrier device described above. For example, the titanium oxide active layer may be replaced by one or more ISM layers. Tunneling layers, such as cobalt oxide may be placed on one or both sides of the one or more ISM layers. As is the case with the ferroelectric transistors and tunnel junction devices, adding the reinforcing electric fields generated by the ISM layers may enhance the band-bending effect of the crested barrier device. The ISM layers may also be used to increase the ON/OFF ratio of the device. For example, replacing the titanium oxide as an active layer switching layer with the ISM layers may be used to modulate the band bending and tunneling barrier, and in turn modulating the ON/OFF ratio for the device, whereby increasing the thickness or number of ISM layers may increase the ON/OFF ratio. Utilizing the ISM layers as active switching layers in tunnel junction fashion and combining the ISM layers with a low bandgap dielectric tunneling layer can be used to create a crested barrier device similar to those described above.
To form a crested barrier device, a tunneling layer 1822 may be added between a top electrode 1802 and the one or more ISM layers 1890. A second tunneling layer 1824 may be added between the one or more ISM layers 1890 and the bottom electrode 1804. The tunneling layers 1822, 1824 may be created using any of the characteristics for these layers described above in the previous discussion of the crested barrier device. The thickness of the tunneling layers 1822, 1824 may range from between approximately 1 nm to approximately 15 nm. In some embodiments of the crested barrier device using the one or more ISM layers 1890, each of the tunneling layers 1822, 1824 may be approximately 10 nm thick. The tunneling layers 1822, 1824 may be fabricated using a cobalt oxide or any other similar material described above.
In some cases, the tunneling layers 1822, 1824 may be characterized by comparing their dielectric constants to the dielectric constants of the materials in the one or more ISM layers 1890. For example, in order for the one or more ISM layers 1892 act as an energy barrier when a voltage is not applied to the device, the dielectric constant of at least one of the ISM layers 1890 may be approximately 1.5 times higher than the dielectric constant of the tunneling layers 1822, 1824. Other embodiments may use greater ratios for the dielectric constants. For example, the dielectric constant of the silicon dioxide layers may be at least 1.5, 2.0, 2.5, 3.0, 3.5, or 4.0 times higher than the dielectric constant of the tunneling layers 1822, 1824. Some embodiments may also define the tunneling layers 1822, 1824 by comparing the bandgap energies 1856 of the tunneling layers 1822, 1824 to the bandgap energies 1858, 1860 of the one or more ISM layers 1890. For example, the bandgap energy 1860 of the silicon dioxide layer may be at least twice the bandgap energy 1856 of the tunneling layers 1822, 1824. As described above, some embodiments may specifically not include a barrier layer in front of the tunneling layers 1822, 1824, such as a silicon dioxide layer between the tunneling layers 1822, 1824 and the electrodes 1802, 1804.
As described above, different materials for the top electrode 1802 and the bottom electrode 1804 may be used such that there is a work function differential between the two electrodes 1802, 1804. The work function of a metal electrode is similar to, or higher than the electron affinity for the tunneling layer and other layers in the device. In other words, the work function of the metal electrode corresponds to the amount of energy required for an electron 1830 to break free of the material and ionize to the vacuum energy level 1859.
For example, the top electrode 1802 may be constructed by depositing a layer of platinum. Instead of using a layer of platinum for the bottom electrode 1804, the bottom electrode 1804 may be formed using a different material having a different work function. In this example, the bottom electrode 1804 may be constructed by depositing a layer of titanium nitrite, which has a work function that is less than the work function of the top electrode 1802 made of platinum. This creates a differential between the two work functions that may be balanced by shifting the energy bands of the other layers in the band diagram of
The one or more ISM layers 890 may have a thickness of between approximately 0.5 nm and approximately 3.0 nm. In this embodiment, each layer of the one or more ISM layers 1890 may be approximately 1 nm. Increasing the thickness of each of the internal layers of the ISM layers 1890 may increase or shift the ON/OFF ratio. However, as the overall thickness of the one or more ISM layers 1890 increases, the operating voltage of the device also increases. Some embodiments have found a layer thickness of between approximately 1.0 nm and approximately 2.0 nm with three individual ISM layers to be optimal for some applications.
The method may also include forming a first tunneling layer (2004). The first tunneling layer may be formed on top of the first electrode. In some embodiments, no intervening layers may be included between the first electrode and the first self-rectifying tunneling layer. The first self-rectifying tunneling layer may be deposited as a layer of a cobalt oxide, such as Co3O4. Some embodiments may also use a layer of amorphous silicon, InP, GaO or any other high-affinity oxide. Some embodiments may instead use a layer of titanium oxide. Layers of titanium oxide may be used that have a phase and/or crystal lattice that generates a relatively low dielectric constant in comparison to the active layer described below.
The method may also include forming an active layer (2006). As described above, each of the ISM layers may be fabricated from three individual layers. For example, an ISM layer may include a layer of hafnium oxide, a monolayer of titanium oxide, and a layer of silicon oxide. Other similar materials may be substituted for these materials as described above. Each of these layers may be formed using deposition processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or the like. The one or more ISM layers may be configured to have a dielectric constant that is higher than the dielectric constant of the first tunneling layer as described above. Additional comparisons between these dielectric constants are disclosed above.
The method may also optionally include forming a second tunneling layer (2008). The second tunneling layer may be formed on top of the active layer. In some embodiments, no intervening layers may be included between the active layer and the second self-rectifying tunneling layer. The second self-rectifying tunneling layer may be deposited as a layer of a cobalt oxide, such as Co3O4. Some embodiments may also use a layer of amorphous silicon or any other high-affinity oxide. Some embodiments may instead use a layer of titanium oxide. Layers of titanium oxide may be used that have a phase and/or crystal lattice structure that generates a relatively low dielectric constant in comparison to the active layer described above. A second electrode may then be added having a higher work function than the first electrode (2010) as described above. Alternatively, the first electrode and the second electrode may have the same work function.
It should be appreciated that the specific steps illustrated in
In the foregoing description, for the purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of various embodiments. It will be apparent, however, to one skilled in the art that embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.
Throughout this disclosure, the term “approximately” may be used to describe values that occur within a range of −15% to +15% of the stated value. For example, a capacitance of approximately 100 nm may fall within the range of 85 nm to 115 nm.
The foregoing description provides exemplary embodiments only, and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the foregoing description of the example embodiments will provide those skilled in the art with an enabling description for implementing an example embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of various embodiments as set forth in the appended claims.
Specific details are given in the foregoing description to provide a thorough understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may have been shown as components in block diagram form in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may have been shown without unnecessary detail in order to avoid obscuring the embodiments.
Also, it is noted that individual embodiments may have been described as a process which is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may have described the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed, but could have additional steps not included in a figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination can correspond to a return of the function to the calling function or the main function.
In the foregoing specification, aspects various embodiments are described with reference to specific embodiments, but those skilled in the art will recognize that the invention is not limited thereto. Various features and aspects of the above-described embodiments may be used individually or jointly. Further, embodiments can be utilized in any number of environments and applications beyond those described herein without departing from the broader spirit and scope of the specification. The specification and drawings are, accordingly, to be regarded as illustrative rather than restrictive.
