Patent Application
20220108159
This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0129509, filed on Oct. 7, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
The present disclosure relates to hardware apparatuses related to neuromorphic computing, and to analog multiply-accumulate (MAC) operation methods using the same.
In order to overcome structural limits of chips based on the conventional Von Neumann structure, integrated circuit (IC) chip developers have been developing neural network hardware and/or neuromorphic computing hardware. Such hardware may be based on neural networks that include neurons, which are the basic units of the human brain, and synapses connecting the neurons. Neural networks may exceed limits of conventional machine learning algorithms, and in particular show potential in image recognition, pattern learning, and cognitive ability, and may be able to approach abilities close to those of human beings. Neural network hardware and/or neuromorphic computing hardware is used in various fields. In addition, dedicated application specific integrated chips (ASIC) for rapidly performing an operation work of neural networks using low power are being considered and developed.
The inventive concepts relate to an array apparatuses based on compressed-truncated singular value decomposition (C-TSVD) capable of reducing the number of sub-arrays in array partitioning while minimizing deterioration of inference accuracy and latency and analog multiply-accumulate (MAC) operation methods using the same.
According to some aspects of the inventive concepts, there is provided a compressed-truncated singular value decomposition (C-TSVD) based crossbar array apparatus, that includes an original crossbar array in an m×n matrix having n row input lines and m column output lines and including cells of a resistance memory device, or two partial crossbar arrays obtained by partitioning the original crossbar array based on C-TSVD, where n and m are natural numbers. The apparatus also comprises an analog to digital converter (ADC) configured to convert output values of column output lines of sub-arrays obtained by partitioning the original crossbar array or the two partial crossbar arrays through array partitioning, an adder configured to sum up results of the ADC to correspond to the column output lines, and a controller configured to control application of the original crossbar array or the two partial crossbar arrays. The C-TSVD based crossbar array apparatus may correspond to one layer of a neural network in neuromorphic computing. Input values may be input to the row input lines, a weight may be multiplied by the input values, and accumulated results may be output as output values of the column output lines, and the weight corresponds the original crossbar array or the two partial crossbar arrays.
According to some aspects of the inventive concepts, there is provided a C-TSVD based crossbar array apparatus, including two partial crossbar arrays obtained by partitioning an original crossbar array in an m×n matrix having n row input lines and m column output lines and including cells of a resistance memory device based on C-TSVD, where n and m are natural numbers. The apparatus also includes an analog to digital converter (ADC) configured to convert output values of column output lines of sub-arrays obtained by partitioning the two partial crossbar arrays through array partitioning, and an adder configured to sum up results of the ADC to correspond to the column output lines. The C-TSVD based crossbar array apparatus may correspond to one layer of a neural network in neuromorphic computing. Input values may be input to the row input lines, a weight may be multiplied by the input values and accumulated results are output as output values of the column output lines, and the weight may correspond the two partial crossbar arrays.
According to some aspects of the inventive concepts, there is provided an analog multiply-accumulate (MAC) operation methods, including calculating an original crossbar array in an m×n matrix connected by n row input lines and m column output lines (where n and m are natural numbers) and including cells of a resistance memory device, selectively performing compressed-truncated singular value decomposition (C-TSVD) partitioning the original crossbar array into two partial crossbar arrays, partitioning the original crossbar array, or the two partial crossbar arrays, into sub-arrays in accordance with a result of selectively performing the C-TSVD inputting input values to row input lines of the sub-arrays, multiplying a weight by the input values and accumulating the multiplication results in the sub-arrays and outputting output values to the column output lines of the sub-arrays, analog to digital (AD) converting the output values of the column output lines by using an analog to digital converter (ADC), and summing up the ADC results to correspond to the column output lines by using an adder. A crossbar array apparatus corresponding to one layer of a neural network may be used in neuromorphic computing. The crossbar array apparatus may include the original crossbar array or the two partial crossbar arrays, the ADC, the adder, and the controller. In the selectively performing of the C-TSVD, application of the original crossbar array or the two partial crossbar arrays may be controlled by the controller.
Embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
Hereinafter, some embodiments of the inventive concepts will be described in detail with reference to the accompanying drawings. Like reference numerals refer to like elements throughout and previously given description of the elements will be omitted.
Referring to
In some embodiments, the weights may be in a matrix, and the weights may be represented as a crossbar array 110 including cells of resistance memory devices 112, as illustrated in
An operation of the crossbar array 110 may be described with voltages and currents. When input values corresponding to the voltages are input to word lines WL of the crossbar array 110, output values corresponding to the currents are output to bit lines BL. The currents of the output values may correspond to results of the multiplication and accumulation operations performed by the neural network. The operation of the crossbar array 110 is represented by Equation 1, as follows.
Im×τGmnVn (1)
In Equation 1, Im represents the currents that are the output values, Vn represents the voltages that are the input values, and Gmn represents conductances. In Equation 1, m and n are natural numbers that may correspond respectively to the number of output values and the number of input values.
Equation 1 may be represented by in the concept of a matrix as seen in Equation 2, as follows.
z=W*a (2)
In Equation 2, a may represent an n×1 column matrix, W may represent an m×n matrix, and z may represent an m×1 column matrix. In connection with Equation 2, components of a may correspond to the voltages that are the input values, components of z may correspond to the currents that are the output values, and components of W may correspond to conductances.
When weight matrix is mapped to the crossbar array 110 a size of the weight matrix may be very large, and high precision may be required when the multiplication and accumulation operation results are to be converted from analog to digital through an analog-to-digital converter (ADC) (refer to 120 of
Referring to
In greater detail, when the crossbar array 110 corresponding to the weight matrix with the size of 512×128 is partitioned into the sub-arrays with the size of 32×32, the number of sub-arrays may be 512/32*128/32=16*4=64. In addition, when AD conversion is performed by the ADC 120a on columns of each of the sub-arrays, the number of operations of the ADC 120a may be 64*32=2048. When the results of the ADC 120a are summed up through the adders 130, 16 ADC results may be obtained for one column. As noted from
When a size of the ADC 120a is large, it may be difficult to arrange one ADC 120a in each column, and one ADC 120a may commonly perform AD conversion for multiple columns by using a multiplexer MUX. One adder 130 may be arranged in each of the stages of the adder tree 130T so that the summing up may be performed. However, according to some embodiments, various numbers of adders 130 may be arranged in each stage.
The following TABLE 1 illustrates equations of the number of sub-arrays # of sub-arrays, the number of operations of an ADC # of ADCs, the number of operations of adders # of additions, the number of adder stages # of adder stages, and operation currents # of cell currents by generalizing a size of a matrix of the crossbar array.
In Table 1, a weight represents a size of a matrix of an original crossbar array, and b means the number of cells required per weight element. For example, in a case in which the weight element is 8 bits, when a cell is a single level cell (SLC) of 1 bit, b is 8; in a case when a cell is a multilevel cell of 2 bits, b is 4; and in a case when a cell is a quad level cell of 4 bits, b is 2. On the other hand, when a cell is a triple level cell (TLC) of 3 bits, because b=8/3=2.xx, which is not an integer, b may not be commonly considered. However, if b is to be considered, b may be represented as eight TLCs by binding three weight elements. For reference, in TABLE 1, b may be calculated as 1.
Herein, ceil( ) is a roundup function (or ceiling function) and ceil(x) represents a minimum integer of no less than x. The number of operations of the adders 130 may be induced as {ceil(m/s)−1}*ceil(n/s)*b*s=ceil(m/s)*ceil(n/s)*b*s−ceil(n/s)*b*s=Ns*s−ceil(n/s)*b*s={Ns−ceil(n/s)*b}*s.
A crossbar array apparatus 100 according to some embodiments of the inventive concepts may reduce (and in some embodiments may remarkably reduce) the number of sub-arrays by decomposing the crossbar array 110 into several partial crossbar arrays (refer to 110a of
Referring to
The rank k is no more than minimum values of m and n. That is, the rank k is no more than a smaller value of m and n. At this time, when only a part is selected from the diagonal matrix components of the matrix S in large order, k may be reduced. When k is reduced by selecting a part of the diagonal matrix components, the matrix W may become an approximation, which is referred to as TSVD. When the TSVD is not applied, the matrix W may be implemented by array partitioned 1 stage. When the TSVD is applied, because the three matrices U, S, and VT must be implemented, the matrix W may be implemented by array partitioned 3 stages. When the matrix W is implemented by array partitioned 3 stages, the size of the matrix W may be remarkably reduced.
In
In
Each of the partial crossbar arrays 110a1, 110a2, and 110a3 may be partitioned into sub-arrays through array partitioning like the crossbar array 100a. In
In order to actually use the TSVD, two matters need to be considered. The first is acceptability of the deterioration of inference precision of a neuron network, which may be caused by replacing the matrix W by an approximation. The second is that an advantage caused by reduction in size of a matrix should be greater, and preferably much greater, than a disadvantage caused by 3-stage implementation. The inference precision will be described with reference to
Referring to
A regularization term may be divided by a regularization parameter during learning. As regularization is reinforced, matrix components close to 0 may increase so that it may be estimated that the approximation of the matrix W is closer to a true value of the matrix W when the same number of components are taken. Describing in more detail, in
For reference, regularization as one of DNN learning methods of reducing over-fitting by reducing the number of weight matrix components may be more widely used as a size of the DNN increases. The regularization parameter may correspond to a hyper parameter of the regularization term introduced in order to prevent over-fitting when learning is performed so that loss is minimized with the concept of a loss function or a cost function. For example, the regularization parameter may correspond to the hyper parameter of the regularization term used for ridge regression, least absolute shrinkage and selection operator (LASSO) regression, or elastic net regression, although the present disclosure is not limited thereto.
Referring to
The following TABLE 2 illustrates inference accuracy in accordance with a regularization parameter and a taken ratio, ‘trained’ illustrates inference accuracy by the original crossbar array matrix W calculated through learning, and ‘TSVD’ illustrates inference accuracy by matrices partitioned through TSVD.
It may be noted from TABLE 2 that, although the taken ratio is no more than 10% in the regularization parameters 0.10 and 0.20, there is little loss of inference accuracy.
Referring to
Then, inference may be performed in operation S170. The inference may mean extracting an output value by inputting a new input value to a weight matrix and the weight matrix may mean the matrices of the partial crossbar arrays obtained through the TSVD and matrices of sub-arrays for the matrices of the partial crossbar arrays. Inference accuracy may be determined based on how much the output value is similar to a true value, and may be based on comparing the output value with the true value. As described above, when the learning method illustrated in
Referring to
Then, learning may be performed with a matrix of a second original crossbar array in operation S270. Here, the matrix of the second original crossbar array may correspond to a matrix obtained by integrating the matrices of the partial crossbar arrays including the k′ components and may be different from the matrix of the first original crossbar array. Through learning, a matrix of a new original crossbar array may be calculated. In addition, in the learning, a regularization term for preventing over-fitting may be included.
Then, inference may be performed in operation S290. In some embodiments, before performing the inference, operations S130 to S150 of
Referring to
First, the number of sub-arrays may be calculated as follows. When a matrix W of an original crossbar array has a size of m×n and is implemented by 1 stage, the number of sub-arrays is Ns(W)=ceil(m/s)*ceil(n/s)*b. Therefore, when the matrix W of the original crossbar array has a size of 512×128, Ns(W)=16*4*1=64.
On the other hand, when 2 stages are implemented through C-TSVD, the number of sub-arrays is Ns(Wt)=Nu+Nv=ceil(m/s)*ceil(k/s)*b+ceil(k/s)*ceil(n/s)*b. Here, Nu means the number of sub-arrays of a matrix U and Nv means the number of sub-arrays of a matrix S*VT. When the matrix W of the original crossbar array has the size of 512×128 and has a taken ratio of 10%, Ns(Wt)=16+4=20. For reference, because the taken ratio is 10%, k′=128*0.1=12.8 and is less than 32. Therefore, when k is replaced by k′, ceil(k/s) is 1.
When the taken ratio is reduced so that k′ is no more than a half of m or n, it may be estimated that the number of sub-arrays is reduced in array partitioning. For example, when the taken ratio is taken to be less than 0.5, in general, Ns(Wt) is less than Ns(W), the number of operations of an ADC and adders may be reduced, and an operating current may be reduced. In TABLE 3, the number of sub-arrays, the number of operations of the ADC, the number of operations of the adders, the number of adder stages, and the operating current in a case in which the taken ratio is 10% will be comparatively illustrated.
For reference, when the 2 stages are implemented through the C-TSVD, the number of operations of the ADC, the number of operations of the adders, the number of adder stages, and the operating current are respectively represented as Ns(Wt)*s, {Ns(Wt)−(ceil(k/s)+ceil(n/s))*b}*s, ceil(log2 ceil(m/s)), and Ns(Wt)*s*s. Therefore, the resultant values illustrated in TABLE 3 may be derived.
It may be noted from TABLE 3 that, excluding the number of adder stages, the number of sub-arrays, the number of operations of the ADC, and the operating current are reduced to 31% and the number of operations of the adders are reduced to 25%. Reduction in operating current may result in a corresponding reduction in energy, which may mean that power is further reduced as the number of stages increases from the 1 stage to the 2 stages.
In general, as a size of a matrix increases, such a degree of reduction may further increase. That is, as a size of a matrix increases, power may be further reduced. TABLE 4 illustrates ratios at which the number of sub-arrays, the number of operations of the ADC, and the operating current are reduced while a size of a matrix increases. As noted from TABLE 3, because the reduction ratios are the same for each of these parameters, in TABLE 4, the reduction ratios may be represented by one value.
It may be noted from TABLE 4 that, as the size of the matrix of the original crossbar array increases, the value of the reduction ratio may be reduced. In calculation by the taken ratio of 10%, for 256, 256*0.1=25.6 is calculated as one sub-array and, for 512, 512*0.1=51.2 may be calculated as two sub-arrays.
Referring to
In the original method, in the last step of each layer, activation may be performed by an activation function circuit 140 such as a rectified linear unit (Relu). That is, an output value of the adder tree 130T may be activated by the activation function circuit 140. On the other hand, in the C-TSVD method, because each layer is operated while being divided into a matrix SVT and a matrix U, an output from the matrix SVT may be transmitted to the matrix U as it is. Therefore, an identity function circuit 160 may be arranged in the last step of the matrix SVT so that the output value of the matrix SVT, that is, an output value of an adder tree 130T1, may be input to the matrix U as it is. In addition, in the last step of the matrix U, which may be the last step of each layer, like in the original method, an activation function circuit 140a may be arranged so that activation may be performed. That is, an output value of an adder tree 130T2 may be activated by the activation function circuit 140a.
On the other hand, in order to let a user select the original method or the C-TSVD method, an identity function may be implemented in the activation function circuit and setting is to be performed by a controller 150 during mapping. By doing so, when it may be difficult to allow even slight accuracy loss and latency loss accompanied by application of the C-TSVD method, the original method may be mapped and used by using the controller 150. In other words, the user may selectively apply the original method or the C-TSVD method.
The following TABLE 5 illustrates equations for calculating latency of the 1 stage of the original method and latency of the 2 stages of the C-TSVD method when the matrix of the original crossbar array has the size of m×n. Here, the latency may mean a time spent on performing an operation of a corresponding method.
Here, cell read as a time spent on reading one cell may mean a time t_cell immediately before a current reading a cell is input to a sense amplifier (S/A) and starts to determine 0/1. In addition, because all cells may be simultaneously read, it also takes t_cell to read all the cells.
Next, q-bit ADC may be determined by inputting 2{circumflex over ( )}q−1 references when the precision of the ADC is q-bit. When it takes t_sa for S/A to determine 0/1 per one reference, it may take t_sa*(2{circumflex over ( )}q−1) to output 0 or 1 for all references. Because the ADC has a large size, it may be difficult to provide the ADC in each bit line (or a column of a sub-array). Therefore, when one ADC is allocated to p_mux bit lines and it takes t_mux to change a bit line connected to the ADC, it may take t_mux+t_sa*(2{circumflex over ( )}q−1) for one bit line. In addition, because s bit lines are provided per sub-array, it may take s*(t_mux+t_sa*(2{circumflex over ( )}q 1) for one sub-array. On the other hand, assuming that all the sub-arrays respectively have ADC circuits and simultaneously perform ADC, the ADC time of all the sub-arrays may be the same as an ADC time of one sub-array.
Each of the ADC results may be sent to the adder tree in order to sum up them when ADC is performed in each sub-array. At this time, the adder tree includes ceil(log2 ceil(m/s)) stages as described above. When the number of bit lines that may be processed by each stage at one time is p_at and a clock cycles_at is needed to process one bit line, it may take s/p_at*cycles_at for one sub-array to perform one stage of the adder tree. Because ceil(n/s) sub-arrays are provided in one array in a column direction, it may take ceil(n/s)*(s/p_at)*cycles_at for all the arrays to perform one stage of the adder tree. When the number of stages is multiplied, it may take ceil(log2 ceil(m/s))*ceil(n/s)*(s/p_at)*cycles_at to perform the adder tree.
Activation may mean a time spent on performing activation after the adder tree is performed. When the number of bit lines that may be activated at one time is p_ac, it may take s/p_ac*cycles_ac per sub-array in one array. Because ceil(n/s) sub-arrays are provided in one array in a column direction, it may take ceil(n/s)*s/p_ac*cycles_ac for all the arrays.
Finally, in the C-TSVD method, because the matrix with the size m×n is partitioned into two matrices respectively having sizes k×n and m×k, corresponding times may be obtained for the respective matrices and summed up by the above-described method.
TABLE 6 illustrates a latency increase ratio of the 2 stages in the C-TSVD method to the 1 stage in the original method when the taken ratio is taken as 10% in various sizes of the matrix of the original crossbar array.
Here, t_cell is set as 10 ns, p_mux is set as 8, t_mux is set as 1 cycle, t_sa is set as 10 ns, q is set as 3 bits, each of p_at and p_ac is set as 8, cycles_at is set as 1 cycle, cycles_ac is set as 1 cycle, and a frequency is set as 1 GHz.
In general, as a size of a matrix increases, an increase ratio may be reduced. Therefore, even when the size of the matrix is no less than 256×256, the increase ratio may be no more than 9%, which is much less than the reduction ratios 69% (100%→31%) of the number of sub-arrays, the number of operations of the ADC, the number of operations of the adder, and the operating current, which is described above as an advantage. Therefore, when the deterioration of the inference accuracy and the deterioration of the latency are permitted to some degree, the crossbar array apparatus 100b according to some embodiments may adopt the configuration of the 2 stages of the C-TSVD method. However, when the deterioration of the inference accuracy and/or the deterioration of the latency are not permitted, the crossbar array apparatus 100b according to some embodiments may adopt the configuration of the 1 stage of the original method.
Referring to
When it is determined to perform the C-TSVD (Yes branch from operation S320), the matrix of the original crossbar array may be decomposed into the matrices of the two partial crossbar arrays through the C-TSVD in operation S330. Additionally, the two partial crossbar arrays may be partitioned into sub-arrays in operation S333. Otherwise, when the C-TSVD is not performed (No branch from operation S320), the original crossbar array may be partitioned into sub-arrays in operation S335.
Then, input values may be input to input lines of the sub-arrays in operation S340, multiplication and accumulation operations may be performed in each of the sub-arrays and output values of output lines may be output in operation S350, the output values may be AD converted through the ADC 120a in operation S360, and the results of the ADC 120a may be summed up through the adder tree 130T in operation S370. As described above, by summing up the results of the ADC 120a, the analog MAC operation method in one layer may be completed.
Referring to
Referring to
Then, the results of the adder tree 130T may be maintained through the identity function circuit 160 in operation S390, input values may be input to input lines of sub-arrays corresponding to the second partial crossbar array in operation S340b, the multiplication and accumulation operations may be performed in each of the sub-arrays and the output values of the output lines are output in operation S350, the output values may be AD converted through the ADC 120a in operation S360, the results of the ADC 120a may be summed up through the adder tree 130T in operation S370, and activation may be performed by the activation function circuit 140a and the activation result may be converted into an input value of a next layer in operation S380.
While the inventive concepts have been particularly shown and described with reference to some embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 1020200129509 | Oct 2020 | KR | national |
