Patent Application
20180167366
There are many different types of electronic communication today. Standards have been developed for different types of communication, including different types of cryptography (encryption and decryption) for data being communicated. Often a single communication device is capable of several different types of communication. For example, a smart phone may employ one type of cryptography for voice communications and another type of cryptography for Internet data traffic. To accommodate different types of cryptography, physically separate, dedicated circuits for each type of cryptography are provided in a single device, and the appropriate circuit is selected based on the type of communication involved.
An example of cryptographic device includes: a data input; a data output; a cipher circuit configured to perform a cipher algorithm on cipher-algorithm input data to produce cipher-algorithm output data; and a network coupled to the data input, the data output, and the cipher circuit, the network comprising a plurality of switches and a plurality of logical signal combiners that are configured to provide the cipher-algorithm input data to the cipher circuit and to provide device output data to the data output using the cipher-algorithm output data and that, in combination with the cipher circuit, are configured to implement a plurality of different cryptographic algorithms that each include the cipher algorithm that the cipher circuit is configured to perform.
Implementations of such a device may include one or more of the following features. The cipher circuit is a single instance of the cipher circuit. The network includes a controller configured to be programmed to actuate the plurality of switches differently to implement the plurality of different cryptographic algorithms. The controller is configured to be programmed to actuate the plurality of switches differently to cause different logical combinations of signals to provide different cipher-algorithm input data from the data input to the cipher circuit and/or to cause different logical combinations of the cipher-algorithm output data to provide the device output data to the data output to implement the plurality of different cryptographic algorithms. The controller is configured to be programmed to actuate the plurality of switches differently to effect values of respective variables in equations representing the plurality of different cryptographic algorithms to implement the plurality of different cryptographic algorithms. The controller is configured to be programmed to actuate the plurality of switches differently to effect values of respective variables in an initial-state encryption equation, a steady-state encryption equation, an initial-state decryption equation, and a steady-state decryption equation to implement the plurality of different cryptographic algorithms. The controller implements a state machine. The controller comprises a memory and a processor communicatively coupled to the memory, the memory comprising processor-readable instructions configured to cause the processor to actuate the plurality of switches selectively.
Also or alternatively, implementations of such a device may include one or more of the following features. The device further includes an authentication circuit coupled to the network and configured to determine an authentication tag, the network being configured to provide a constant logical zero signal to the authentication circuit during a time when the cryptographic device is active but the authentication circuit is not determining the authentication tag. The device further includes an authentication circuit coupled to the network and configured to determine an authentication tag in combination with the network, the authentication circuit being separate from the cipher circuit, where the network is configured such that at least a same one of the plurality of switches and/or at least a same one of the plurality of logical signal combiners is used to perform at least one of the plurality of different cryptographic algorithms and to determine the authentication tag. The network and the cipher circuit are configured to implement the plurality of different cryptographic algorithms without an unregulated loop.
Another example of a cryptographic device includes: a data input configured to receive cryptographic algorithm input data; a data output; and means, coupled to the data input and the data output, for implementing a plurality of different cryptographic algorithms, the means for implementing comprising: cipher means for performing a cipher algorithm on cipher-algorithm input data to produce cipher-algorithm output data; and network means, coupled to the cipher means, for producing, based upon the cryptographic algorithm being implemented, cipher-algorithm input data from the cryptographic algorithm input data, for providing the cipher-algorithm input data to the cipher means, for producing, based upon the cryptographic algorithm being implemented, cryptographic algorithm output data from the cipher-algorithm output data, and for providing the cryptographic algorithm output data to the data output.
Implementations of such a device may include one or more of the following features. The network means are for selectively logically combining data based upon the cryptographic algorithm being implemented. The network means are configured to actuate a plurality of switches differently to implement the plurality of different cryptographic algorithms. The network means are configured to provide different combinations of data inputs to one or more logical signal combiners to implement the plurality of different cryptographic algorithms. The network means are configured to provide the different combinations of data inputs to effect values of respective variables in an initial-state encryption equation, a steady-state encryption equation, an initial-state decryption equation, and a steady-state decryption equation to implement the plurality of different cryptographic algorithms.
Also or alternatively, implementations of such a device may include one or more of the following features. The means for implementing further comprise authentication means, coupled to the network means, for determining an authentication tag associated with the cryptographic algorithm output data, the network means being further for providing a constant logical zero signal to the authentication means during a time when the cryptographic device is active but the authentication means are not determining the authentication tag. The means for implementing further comprise authentication means, coupled to the network means, for determining an authentication tag associated with the cryptographic algorithm output data, the network means and the authentication means sharing at least one switch and/or at least one logical signal combiner.
An example of a cryptographic method includes: receiving cryptographic algorithm input data at a cryptographic device; directing the cryptographic algorithm input data in the cryptographic device through a network of switches and logical signal combiners to produce cipher-algorithm input data; performing a cipher algorithm on the cipher-algorithm input data in a cipher circuit to produce cipher-algorithm output data; and directing the cipher-algorithm output data in the cryptographic device through the network of switches and logical signal combiners to produce cryptographic algorithm output data; where the cryptographic algorithm input data and the cipher-algorithm output data are directed through the network of switches and logical signal combiners based upon a selected cryptographic algorithm from a plurality of cryptographic algorithms implementable by different paths through the network of switches and logical signal combiners, with each path including the cipher circuit.
Implementations of such a device may include one or more of the following features. Directing the cryptographic algorithm input data, performing the cipher algorithm, and directing the cipher-algorithm output data implement values of respective variables in an initial-state encryption equation, a steady-state encryption equation, an initial-state decryption equation, and a steady-state decryption equation applicable to the plurality of different cryptographic algorithms to implement the selected cryptographic algorithm. The method further includes determining an authentication tag, associated with the cryptographic algorithm output data, using an authentication circuit to perform a one-way function. The method further includes providing a constant logical zero signal to the authentication circuit while the authentication circuit is idle. The authentication tag is determined using at least one logical signal combiner, in the network of switches and logical signal combiners, through which data pass in implementing the selected cryptographic algorithm.
Also or alternatively, implementations of such a device may include one or more of the following features. The cryptographic algorithm input data are first cryptographic algorithm input data, the cipher-algorithm input data are first cipher-algorithm input data, and the cryptographic algorithm output data are first cryptographic algorithm output data corresponding to a first cryptographic algorithm of the plurality of cryptographic algorithms, the method further comprising: receiving second cryptographic algorithm input data at the cryptographic device; directing the second cryptographic algorithm input data in the cryptographic device through the network of switches and logical signal combiners to produce second cipher-algorithm input data; performing the cipher algorithm on the second cipher-algorithm input data in the cipher circuit to produce second cipher-algorithm output data; and directing the second cipher-algorithm output data in the cryptographic device through the network of switches and logical signal combiners to produce second cryptographic algorithm output data corresponding to a second cryptographic algorithm of the plurality of cryptographic algorithms, the second cryptographic algorithm being different from the first cryptographic algorithm.
An example of a non-transitory, processor-readable storage medium includes processor-readable instructions configured to cause a processor to: receive cryptographic algorithm input data; receive an indication of a selected cryptographic algorithm from a plurality of different cryptographic algorithms; produce, based upon the selected cryptographic algorithm, cipher-algorithm input data from the cryptographic algorithm input data; perform a cipher algorithm on the cipher-algorithm input data to produce cipher-algorithm output data; and produce, based upon the cryptographic algorithm being implemented, cryptographic algorithm output data from cipher-algorithm output data.
Implementations of such a device may include one or more of the following features. The instructions configured to produce the cipher-algorithm input data and/or the instructions configured to cause the processor to produce the cryptographic algorithm output data are configured to cause the processor to selectively logically combine data based upon the selected cryptographic algorithm. The instructions configured to cause the processor to selectively logically combine data are configured to cause the processor to provide a particular combinations of data, based upon the selected cryptographic algorithm, to be logically combined. The instructions configured to cause the processor to provide the particular combination of data are configured to cause the processor to provide the particular combination of data to effect values of respective variables in an initial-state encryption equation, a steady-state encryption equation, an initial-state decryption equation, and a steady-state decryption equation to implement the selected cryptographic algorithm. The storage medium further includes instructions configured to cause the processor to determine an authentication tag associated with the cryptographic algorithm output data.
Techniques are discussed herein for implementing multiple cryptographic modes using shared circuitry. For example, a single instance of a cipher circuit and/or a shared signal-modifying network can be used to implement multiple cryptographic modes. Input data may be selectively manipulated before being provided, as cipher-algorithm input data, to a cipher circuit such that while the cipher circuit performs the same cipher algorithm, different cipher-algorithm input data are produced by the selective manipulation such that different output data are produced for the same input data depending upon the cryptographic mode that is programmed to be performed. These examples, however, are not exhaustive.
Items and/or techniques described herein may provide one or more of the following capabilities, as well as other capabilities not mentioned. Multiple cryptographic modes may be implemented in a single interconnection network. Space, size, and/or cost may be reduced for providing multiple encryption mode capability. Future cryptographic modes may be accommodated without requiring a hardware change to a cryptographic engine. Other capabilities may be provided and not every implementation according to the disclosure must provide any, let alone all, of the capabilities discussed. Further, it may be possible for an effect noted above to be achieved by means other than that noted, and a noted item/technique may not necessarily yield the noted effect.
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The cryptographic engine 44, in particular the decryption engine 46 and the encryption engine 48, under control of the controller 50, is configured to implement multiple cryptographic algorithms (called modes or cryptographic modes) using a shared hardware, here a shared cryptography circuit 52. A mode as used herein is an algorithm for the cryptographic transformation of data that features a symmetric cipher algorithm. The controller 50 is configured to cause various data to be provided to the shared cryptography circuit, and to cause selective portions of the shared cryptography circuit to be used, in order to implement a selected cryptographic algorithm out of a set of different cryptographic algorithms that the cryptographic engine 44 is configured to implement. The shared cryptography circuit 52 is shown separately from the decryption engine 46 and the encryption engine 48, but is part of both the decryption engine 46 and the encryption engine 48 and thus shared by the decryption engine 46 and the encryption engine 48. The shared cryptography circuit 52 includes a cipher circuit 54 and a digest circuit 56.
The cipher circuit 54 is preferably, but not necessarily, a single instance of a circuit configured to perform a symmetric cipher algorithm. The cipher circuit 54 may have portions that are physically separate from each other, but the cipher circuit 54 is one collection of circuitry configured to perform a cipher algorithm. The device 12 could also have other circuitry to perform other functions, and may even have other cipher circuitry, but the multiple cryptographic algorithms can be implemented by the cipher circuit 54 in combination with other non-cipher circuitry without having other instances of the cipher circuitry. For example, the multiple cryptographic algorithms can be implemented without multiple separate circuits for implementing different modes, with the different circuits each having a cipher circuit of the same configuration (i.e., configured to implement the same cipher algorithm). The cipher circuit 54 is preferably configured to perform a cipher algorithm on input data to produce cipher-algorithm output data. While examples are discussed herein for operating on blocks of data, symmetric ciphers may be applied to blocks of data or streams of data and the discussion herein, including the various components discussed and the claims, includes both of these possibilities unless a possibility is explicitly excluded. The controller 50 is configured to control portions of the decryption engine 46 and the encryption engine 48 to use desired input data to produce cipher-algorithm input data, possibly by logically combining the input data, and to provide the cipher-algorithm input data to the cipher circuit 54. The controller 50 is further configured to control portions of the decryption engine 46 and the encryption engine 48 to use cipher-algorithm output data from the cipher circuit 54 to produce device output data, possibly by logically combining the cipher-algorithm output data with other data. The controller 50 is configured to selectively logically combine data based upon the cryptographic algorithm being implemented.
The digest circuit 56 is configured to produce an authentication tag associated with encrypted data produced by the encryption engine 48. The digest circuit 56 is configured to perform a digest algorithm, that preferably implements a one-way cryptographic function, on data input to the digest circuit 56. The one-way cryptographic function is irreversible, at least from a practical standpoint. The controller 50 is configured to control portions of the encryption engine 48 to use desired input data to produce digest input data, possibly by logically combining the input data based on the cryptographic algorithm being implemented, and to provide the digest input data to the digest circuit 56. The controller 50 is further configured to control portions of the encryption engine 48 to use digest output data from the digest circuit 56 as an authentication tag for corresponding cipher text.
The following table illustrates expressions for implementing several standard cryptographic algorithms.
Table 1 shows expressions for processing an initial (i=0) and subsequent (i>0) blocks of data of a message according to cryptographic algorithms: ECB (Electronic Codebook), CBC (Cipher Block Chaining), PCBC (Propagating Cipher Block Chain), CFB (Cipher Feedback), OFB (Output Feedback), and CTR (Counter). Still other modes could be used, such as XCBC, EAX, CCM, XTS, GCM, F8, F9, etc. In Table 1, IV is an initialization vector, which may be a random number, and the symbol ⊕ indicates a logical XOR (exclusive-OR) operation. The expressions shown are for symmetric cryptography modes where a plaintext message P is decomposed into blocks of a uniform block size such that
P=P0,P1,P2, . . . Pn-1 (1)
For 0≤n−1, the length of the plaintext block Pi is the block size. If the length of the last plaintext block, Pn-1, is less than the block size, then appropriate padding is added to reach the block size. Further, in Table 1, Ek( )) and Dk( )) represent encryption and decryption functions, respectively, or a symmetric cipher with a shared secret k. Lastly, the cipher text indicated in Table 1 and resulting from encryption of the plaintext P may be expressed as
C=C0,C1,C2, . . . ,Cn-1 (2)
The block size is the amount of data that the decryption engine 46 is configured to process to decrypt (or that the encryption engine 48 is configured to encrypt) at any one time. This amount of data may be of various sizes (e.g., 128 bits, 512 bits, etc.).
It has been discovered that the expressions in Table 1 may be condensed to fewer expressions that include variables (that may be set to various values to achieve a particular one of the expressions shown in Table 1). In particular, it has been found that the expressions in Table 1 may be reduced to the expressions shown below in Table 2.
Each of the variables X, Y, Z, S, and T can be given an appropriate non-zero value, or a value of zero, in order to make the corresponding expression into one of the expressions in Table 1. A subscript of 0 indicates an initialization value of the variable, i.e., for an initial block of a message processed for the respective cryptographic algorithm and a subscript if i indicates a steady-state value for the variable, i.e., for any block, after the initial block, of a message for the respective cryptographic algorithm. Table 3 shows the values of the variables in
In Table 3, a dash (-) indicates that this variable is not used. The values of Xi and Si for CTR mode being nonce ∥ IV indicate that the argument for the Ek and Dk functions, respectively, are nonce ∥ IV.
The controller 50 is configured to assign the values to the variables according to Table 3 to implement the desired cryptographic algorithm. The controller 50 may implement a finite state machine or a processor and software with instructions configured to be executed by the processor to perform the appropriate functions. Referring to
It has further been discovered that the expressions in Table 2 may be condensed to fewer expressions that include variables that may take on plaintext, cipher text, or initialization vector values. In particular, it has been found that the expressions in Table 2 may be reduced to the expressions shown below in Table 4.
In this case, the values of A and B may be plaintext, cipher text, and IV, etc., and values of X, Y, Z, S, and T are assigned as appropriate to achieve the desired expression shown in Table 1. The controller 50 may be configured to provide the appropriate values of the variables to implement a desired mode.
Referring to
The network 116 is configured to provide a constant logical zero signal to various components. For example, the network 116 may provide a logical signal to the cipher circuit 118 or the digest circuit 120 when device 12, and in particular the cryptographic engine 44, is active but the cipher circuit 118 or the digest circuit 120 is idle and thus not producing ciphertext, plaintext, or an authentication tag, respectively. By providing a constant logical zero signal to the cipher circuit 118 or the digest circuit 120, prevents the cipher circuit 118 or the digest circuit 120 from seeing a variable data on its respective input, and thus prevents power consumption corresponding to the cipher circuit 118 or the digest circuit 120 processing the variable data. The constant logical zero signal may have a voltage that varies over time but that stays within a range corresponding to a logical zero, i.e., does not change in logical value. For example, a signal may be considered a logical zero if it's voltage is at or below 0.5 V. In this example, the constant logical zero signal may vary in value from 0 V to 0.5 V and still be considered a constant logical zero signal. The network 116 may provide a logical zero signal to a multiplexer when the output of the multiplexer is not being used.
The data input 112 is configured to receive several types of information and to provide the information to the network 116. The counter sub-input 130 may be a passive input that receives a counter value or may be a counter that generates and provides a counter value. The data sub-input 132 is coupled and configured to receive plaintext messages to be encrypted and cipher text messages to be decrypted. The initialization vector sub-input 134 may be a passive input that receives an initialization vector or may be a device configured to generate and provide an initialization vector. For example, the initialization vector sub-input 134 may be a random-number generator or a pseudo-random-number generator and the initialization vector may be a random number or a pseudo-random number (or other value). The alternative initialization vector sub-input 136 may be a passive input that receives an alternative initialization vector or may be a device configured to generate and provide an alternative initialization vector. The mask sub-input 138 may be a passive input that receives a mask value or may be a device configured to generate and provide a mask value.
The network 116 is configured to convey and manipulate data from the data input 112 to the cipher circuit 118 and the digest circuit 120, from the cipher circuit 118 to the data output 114 and/or to the cipher circuit 118, and from the digest circuit 120 to the data output 114 and/or the digest circuit 120. The network 116 is configured to convey data from any of the sub-inputs 130, 132, 134, 136, 138 to the cipher circuit 118 and/or the digest circuit 120 as appropriate. For example, the network 116 may route plaintext from the data sub-input 132 and/or an initialization vector from the initialization vector sub-input 134 to the cipher circuit 118. The network 116 may logically combine the plaintext and/or the initialization vector with each other and/or with other data to form cipher-algorithm input data and provide the cipher-algorithm input data to the cipher circuit 118. Alternatively, the network 116 may provide data from the data sub-input 132 (e.g., plaintext or cipher text) or from the initialization vector sub-input 134 to the cipher circuit 118 without altering any of these data, e.g., without logically combining the data (e.g., plaintext, cipher text, initialization vector) with any other data. The network 116 may route and/or logically combine data from others of these sub-inputs 130, 132, 134, 136, 138 to produce the cipher-algorithm input data and/or to produce digest input data and provide the digest input data to the digest circuit 120. Further, the network 116 is configured to convey an output of the digest circuit 122 to the authentication sub-output 142 and/or back to the digest circuit 120. For example, the network 116 may store results of the processing by the cipher circuit 118 in a register 144 and store results of the processing of the digest circuit 120 in a register 146. The network 116 is also configured to convey data output from the cipher circuit 118, e.g., as stored in the registers 144, 146, to the data sub-output 140 and/or back to the cipher circuit 118. While routing the data output from the cipher circuit 118, the network 116 may logically combine the data output from the cipher circuit 118 with other data, such as mask data from the mask sub-input 138, before providing the data to the data sub-output 140.
To convey the data from the data input 112 to the cipher circuit 118 and/or the digest circuit 120, and from the cipher circuit 118 and/or the digest circuit 122 the data output 114 and/or back to the cipher circuit 118 or the digest circuit 120, respectively, the network 116 routes the data through one or more of the logical signal combiners 117 and one or more of the switches S (here multiplexers) as appropriate. The network 116 is configured such that these logical signal combiners 117 and these switches S can provide cipher-algorithm input data to the cipher circuit 118, which is a single instance of a cipher circuit, and to provide device output data to the data output 114 using cipher-algorithm output data from the cipher circuit 118. The network 116, in combination with the single instance of the cipher circuit 118, is configured to implement the different cryptographic algorithms implementable by the cryptographic engine 44, with each of the cryptographic algorithms including the cipher algorithm that the single instance of the cipher circuit 118 is configured to perform.
The network 116 includes the controller 50 which is configured to be programmed to actuate the switches S in the network 116 to route data and to cause the logical combinations of data. The controller 50 is configured to be programmed to actuate the switches S differently to implement the different cryptographic algorithms. In particular, the controller 50 is configured to be programmed to actuate the switches S differently to cause different logical combinations of signals in the logical signal combiners 117 to provide different cipher-algorithm input data from the data input 112 to the cipher circuit 118. Also or alternatively, the controller 50 may cause different logical combinations of cipher-algorithm output data from the cipher circuit 118 to provide device output data to the data output 114, and in particular the data sub-output 140, and (as appropriate) back to the cipher circuit 118, to implement the different cryptographic algorithms. The controller 50 may be configured to be programmed to actuate the switches S differently to affect values of respective variables and equations representing the different cryptographic algorithms, e.g., as shown in Table 2 and Table 4, to implement the different cryptographic algorithms. In particular, the controller 50 may be configured to be programmed to actuate the switches S to affect values of respective variables in an initial-state encryption equation, a steady-state encryption equation, an initial-state decryption equation, and a steady-state decryption equation to implement the different cryptographic algorithms. Further, the network 116 is configured such that the network 116 and the cipher circuit 118 may implement the different cryptographic algorithms without forming an unregulated loop.
The network 116 is also configured to provide, in accordance with control signals from the controller 50, data to the digest circuit 120 to provide an authentication mechanism for producing an authentication tag, e.g., corresponding to cipher text produced by the cipher circuit 118. The digest circuit 120 is configured to perform a one-way function on received data. The network 116 is preferably configured to feedback output of the digest circuit 120 until all the data to be authenticated has been processed, yielding an authentication tag that is smaller than the data being authenticated, and preferably an authentication tag of the same size regardless of the size of the authenticated data message.
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At stage 212, the method 210 includes receiving cryptographic algorithm input data at a cryptographic device. For example, counter data, plaintext, cipher text, an initialization vector, an alternative initialization vector, and/or mask data may be received by the data input 112 of the device 12. Receiving the cryptographic algorithm input data may include producing the cryptographic algorithm input data, e.g., producing a counter value, producing a random number or pseudorandom number as an initialization vector or alternative initialization vector.
At stage 214, the method 210 includes directing the cryptographic algorithm input data in the cryptographic device through a network of switches and logical signal combiners to produce cipher-algorithm input data. For example, the network 116 selectively routes data from the data input 112 through one or more of the switches S and one or more of the logical signal combiners 117 to produce cipher-algorithm input data. Which data are routed through which switch(es) S and through which logical signal combiner(s) 117 and whether the data are altered or not by the logical signal combiner(s) 117 is controlled by the controller 50 selectively actuating (i.e., actuating or not actuating) the switch(es) S, and selectively actuating (i.e., actuating or not actuating) one or more data sub-inputs such as the counter sub-input 130. The different routing and logical combinations produce the cipher-algorithm input data in accordance with the selected cryptographic algorithm, which may be programmed, e.g., either by programming a state machine or by programming software that is executed by a processor.
At stage 216, the method 210 includes performing a cipher algorithm on the cipher-algorithm input data in a single instance of a cipher circuit to produce cipher-algorithm output data. For example, the cipher circuit 118 processes the cipher-algorithm input data according to a cipher algorithm that the cipher circuit 118 is configured to perform. The cipher algorithm is preferably a symmetric cipher algorithm in which case the cipher circuit 118 ciphers a block of the cipher-algorithm input data, forming cipher text from plain text, or forming plaintext from cipher text, or transforming cipher text into text that may be further manipulated into plaintext, e.g., by logically combining the text with further data. The cipher algorithm is performed using the cipher circuit 118 regardless of which of multiple cryptographic algorithms (modes) is being implemented. Thus, the cipher algorithm for multiple modes is performed without using separate physical cipher circuits each of which can perform the same cipher algorithm.
At stage 218, the method 210 includes directing the cipher-algorithm output data in the cryptographic device through the network of switches and logical signal combiners to produce cryptographic algorithm output data. For example, the network 116 routes a block of data output from the cipher circuit 118 from the register 146 to the data sub-output 140 of the data output 114. In other examples, the network 116 may route the cipher-algorithm output data through one or more switches and/or one or more logical signal combiners as appropriate for an implemented cryptographic algorithm.
The cryptographic algorithm input data and the cipher-algorithm output data are directed through the network of switches and logical signal combiners based upon a selected cryptographic algorithm from multiple cryptographic algorithms implementable by different paths through the network, with each path including the single instance of the cipher circuit. Thus, multiple different cryptographic algorithms may be implemented by routing data through the network differently, combining data logically as appropriate for the particular cryptographic algorithm being implemented. For example, directing the cryptographic algorithm input data, performing the cipher algorithm, and directing the cipher-algorithm output data implement values of respective variables in an initial-state encryption equation, a steady-state encryption equation, an initial-state decryption equation, and a steady-state decryption equation applicable to the plurality of different cryptographic algorithms to implement the selected cryptographic algorithm. Examples of such equations are provided in Tables 2 and 4 above. A cryptographic algorithm may be selected by, e.g., programming the controller 50 or providing a selection indication to the controller 50. In a software implementation, an indication of a selected cryptographic algorithm may be received, e.g., by receiving an indication of a cryptographic algorithm (e.g., “CBC”) or by receiving indications of values of variables (e.g., for the expressions shown in Table 4) that correspond to a particular cryptographic algorithm.
The method 210 may further include other features and/or stages. For example, the method 210 may further include determining an authentication tag, associated with the output data, using an authentication circuit to perform a one-way function, e.g., as discussed with respect to
Other Considerations
Other examples and implementations are within the scope and spirit of the disclosure and appended claims. For example, due to the nature of software and computers, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.
Also, as used herein, “or” as used in a list of items prefaced by “at least one of” or prefaced by “one or more of” indicates a disjunctive list such that, for example, a list of “at least one of A, B, or C,” or a list of “one or more of A, B, or C” means A or B or C or AB or AC or BC or ABC (i.e., A and B and C), or combinations with more than one feature (e.g., AA, AAB, ABBC, etc.).
As used herein, unless otherwise stated, a statement that a function or operation is “based on” an item or condition means that the function or operation is based on the stated item or condition and may be based on one or more items and/or conditions in addition to the stated item or condition.
Further, an indication that information is sent or transmitted, or a statement of sending or transmitting information, “to” an entity does not require completion of the communication. Such indications or statements include situations where the information is conveyed from a sending entity but does not reach an intended recipient of the information. The intended recipient, even if not actually receiving the information, may still be referred to as a receiving entity, e.g., a receiving execution environment. Further, an entity that is configured to send or transmit information “to” an intended recipient is not required to be configured to complete the delivery of the information to the intended recipient. For example, the entity may provide the information, with an indication of the intended recipient, to another entity that is capable of forwarding the information along with an indication of the intended recipient.
A wireless communication system is one in which communications are conveyed wirelessly, i.e., by electromagnetic and/or acoustic waves propagating through atmospheric space rather than through a wire or other physical connection. A wireless communication network may not have all communications transmitted wirelessly, but is configured to have at least some communications transmitted wirelessly. Further, the term “wireless communication device,” or similar term, does not require that the functionality of the device is exclusively, or evenly primarily, for communication, or that the device be a mobile device, but indicates that the device includes wireless communication capability (one-way or two-way), e.g., includes at least one radio (each radio being part of a transmitter, receiver, or transceiver) for wireless communication.
Substantial variations may be made in accordance with specific requirements. For example, customized hardware might also be used, and/or particular elements might be implemented in hardware, software (including portable software, such as applets, etc.), or both. Further, connection to other computing devices such as network input/output devices may be employed.
The terms “machine-readable medium” and “computer-readable medium,” as used herein, refer to any medium that participates in providing data that causes a machine to operate in a specific fashion. Using a computer system, various computer-readable media might be involved in providing instructions/code to processor(s) for execution and/or might be used to store and/or carry such instructions/code (e.g., as signals). In many implementations, a computer-readable medium is a physical and/or tangible storage medium. Such a medium may take many forms, including but not limited to, non-volatile media and volatile media. Non-volatile media include, for example, optical and/or magnetic disks. Volatile media include, without limitation, dynamic memory.
Common forms of physical and/or tangible computer-readable media include, for example, a floppy disk, a flexible disk, hard disk, magnetic tape, or any other magnetic medium, a CD-ROM, any other optical medium, punchcards, papertape, any other physical medium with patterns of holes, a RAM, a PROM, EPROM, a FLASH-EPROM, any other memory chip or cartridge, a carrier wave as described hereinafter, or any other medium from which a computer can read instructions and/or code.
Various forms of computer-readable media may be involved in carrying one or more sequences of one or more instructions to one or more processors for execution. Merely by way of example, the instructions may initially be carried on a magnetic disk and/or optical disc of a remote computer. A remote computer might load the instructions into its dynamic memory and send the instructions as signals over a transmission medium to be received and/or executed by a computer system.
The methods, systems, and devices discussed above are examples. Various configurations may omit, substitute, or add various procedures or components as appropriate. For instance, in alternative configurations, the methods may be performed in an order different from that described, and that various steps may be added, omitted, or combined. Also, features described with respect to certain configurations may be combined in various other configurations. Different aspects and elements of the configurations may be combined in a similar manner. Also, technology evolves and, thus, many of the elements are examples and do not limit the scope of the disclosure or claims.
Specific details are given in the description to provide a thorough understanding of example configurations (including implementations). However, configurations may be practiced without these specific details. For example, well-known circuits, processes, algorithms, structures, and techniques have been shown without unnecessary detail in order to avoid obscuring the configurations. This description provides example configurations only, and does not limit the scope, applicability, or configurations of the claims. Rather, the preceding description of the configurations provides a description for implementing described techniques. Various changes may be made in the function and arrangement of elements without departing from the spirit or scope of the disclosure.
Also, configurations may be described as a process which is depicted as a flow diagram or block diagram. Although each may describe the operations as a sequential process, some operations may be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process may have additional stages or functions not included in the figure. Furthermore, examples of the methods may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware, or microcode, the program code or code segments to perform the tasks may be stored in a non-transitory computer-readable medium such as a storage medium. Processors may perform one or more of the described tasks.
Components, functional or otherwise, shown in the figures and/or discussed herein as being connected or communicating with each other are communicatively coupled. That is, they may be directly or indirectly connected to enable communication between them.
Having described several example configurations, various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the disclosure. For example, the above elements may be components of a larger system, wherein other rules may take precedence over or otherwise modify the application of the invention. Also, a number of operations may be undertaken before, during, or after the above elements are considered. Accordingly, the above description does not bound the scope of the claims.
Further, more than one invention may be disclosed.
