Patent Grant
8280330
The present invention generally relates to radio frequency receivers and particularly to clock generation for radio receivers that do not require a crystal or a reference clock to generate an accurate reference clock.
Radio frequency receivers have been widely used in various electronic products such as AM and FM radios, television sets, and GPS (global positioning system) navigation devices. Typically there are multiple channels within the allocated spectrum. In order to receive the signal in a desired channel, the radio frequency input signal is usually mixed with a signal generated by a local oscillator (LO) to translate the incoming radio frequency signal to a lower-frequency signal suitable for further processing using cost effect components and/or for superior performance. The frequency translated signal may be a baseband signal, low-IF (intermediate frequency) or IF signal. The low frequency characteristic of the frequency translated signal makes itself ideal for digital signal processing at lower clock speed to conserve power consumption. In addition, the use of digital signal processing technique provides high flexibility for processing the underlying signal. Therefore, the radio receiver usually includes digital signal processing circuitry to perform the required receiving functions such as filtering, demodulation, and de-multiplexing (for FM stereo broadcast).
In order to receive a desired channel, the incoming radio frequency signal is mixed with a selected LO signal to translate the frequency of incoming radio frequency signal to a lower frequency signal. A bandpass or a low pass filter is applied to the mixed signal in order to filter out possible interfering signals. The proper mixer operation requires a desired LO signal to be generated responsive to the channel selection. The LO signal usually is generated by a tunable clock generation circuit which typically includes a voltage controlled oscillator coupled with phase locked loop circuitry. The LO frequency has to be substantially accurate to ensure proper system operation and good sound quality. Furthermore, system clocks for various parts of the radio receiver such as digital clock and sampling clocks for analog-to-digital converter (ADC) and digital-to-analog (DAC), also have to be substantially accurate to ensure proper system operation and high system performance. In order to meet the LO frequency and system clocks accuracy, a crystal is often used to provide the required accurate reference clock so that the LO signal and system clocks can be accurately generated using techniques such as phase-locked-loop to lock the LO frequency and the system clocks with the reference clock. Alternatively, a reference clock complying with the required frequency tolerance may also be used. The LO frequency may be locked to the external reference clock. The use of a crystal may increase the system cost. The use of an externally supplied reference clock will relieve the need for a crystal. However, an externally supplied reference clock may not be always available. For example, in a stand-alone radio receiver application, the external reference clock may not be available.
In light of the foregoing discussions, therefore it is desirable to provide systems and methods for clock generation that do not require a crystal or a reference clock. The clock generation should provide an accurate LO frequency for the receiver to tune to a desired channel and provide an accurate system clocks to the receiver for proper operation without the need of a crystal or a reference clock.
The present invention discloses systems and methods for clock generation shared by the mixer and various parts of the system such as the digital signal processing circuitry, analog-to-digital converter (ADC) and digital-to-analog converter (DAC). A frequency-tunable voltage controlled oscillator (VCO) coupled with phase locked loop (PLL) circuitry is used to generate a local oscillator (LO) signal and system clocks. The LO signal is derived from the VCO signal and is provided to the mixer. The system clocks are derived from the VCO signal using a PLL circuit and various frequency dividers. The clock generation circuit does not include a crystal or a reference clock. In order to obtain an accurate reference clock, the clock generation circuit relies on a pilot signal transmitted in a channel. For example, the stereo FM station in the United States transmits an accurate pilot tone signal at 19 kHz. The pilot signal can be used as the reference signal by the clock generation circuit to generate accurate clocks as required.
In one embodiment, the present invention discloses a clock generation method that comprises providing a first clock signal, The clock generation method then collaborates with the radio receive to scan the plurality of channels by tuning frequency of the first clock signal until the radio receiver detects a candidate channel having a pilot signal. The pilot signal is then used to generate clocks for the radio receiver. A system for clock generation according to the above method is also disclosed.
In another embodiment, the present invention discloses a clock generation method that comprises providing a first clock signal and a second clock signal to the radio receiver, wherein a frequency synthesis method is used to generate the second clock signal from the first clock signal according to a frequency ratio. The clock generation method then collaborates with the radio receive to scan the plurality of channels by tuning frequency of the first clock signal until the radio receiver detects a candidate channel having a pilot signal. A candidate channel may be determined based on received signal strength. When the pilot signal is detected, a first control value is determined according to the frequency of the pilot signal and the frequency of the second clock signal. The method then calls for adjusting frequency of the first clock signal according to the first control value and a second control value, wherein the second control value is related to the frequency of the pilot signal and a target frequency of the second clock signal. The method further calls for adjusting the frequency ratio to compensate the change in the frequency of the second clock signal caused by the adjusting frequency of the first clock.
In yet another embodiment of the present invention, the accuracy of the generated clock can be iteratively improved by repeating the steps a) determining the first control value according to the frequency of the pilot signal and the frequency of the second clock signal, b) adjusting frequency of the first clock signal according to the first control value and a second control value, and c) adjusting the frequency ratio to compensate the change in the frequency of the second clock signal caused by the adjusting frequency of the first clock until a stop criterion is satisfied. In yet another embodiment of the present invention, the accuracy of the generated clock is further improved after the above iterative steps by using the intermediate frequency (IF) counter technique, wherein the frequency of the first clock signal is adjusted according to a value of the IF counter for a tuned channel and a computed IF counter value corresponding to the target frequency of the second clock signal.
The present invention also discloses a clock generation circuit for a radio receiver to receive radio frequency signals. The clock generation circuit comprises a first circuit to provide a first clock signal to the radio receiver and a frequency synthesis circuit coupled to receive the first clock signal to provide a second clock signal to the radio receiver. The frequency synthesis circuit generates the second clock signal from the first clock signal according to a frequency ratio. A scan control logic as part of frequency control logic is included in the clock generation circuit to provide a control signal to the first circuit and the frequency synthesis circuit, wherein the control signal causes the radio receiver to scan the plurality of channels by tuning frequency of the first clock signal until a candidate channel having a pilot signal is detected. Furthermore, the frequency control logic is coupled to receive a first control input to provide a first control output to the first circuit and a second control output to the frequency synthesis circuit, wherein the first control input is related to frequency of the pilot signal and frequency of the second clock signal, the first control output is provided to the first circuit to adjust frequency of the first clock signal according to the first control input and a target frequency of the second clock signal, and the second control output is provided to the frequency synthesis circuit to adjust the frequency ratio to compensate change in the frequency of the second clock signal due to change in the frequency of the first clock caused by the first control output. In yet another embodiment of the present invention, the frequency control logic that is coupled to further receive value of an IF counter for a tuned channel provides a further first control output based on the IF counter and a target IF count value, wherein the IF counter is clocked by the second clock signal.
In the following description, numerous details are set forth to provide a more thorough explanation of embodiments of the present invention. It will be apparent, however, to one skilled in the art, that embodiments of the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present invention.
Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Further, the order of blocks in process flowcharts or diagrams representing one or more embodiments of the invention do not inherently indicate any particular order nor imply any limitations in the invention.
Embodiments of the present invention are discussed herein with reference to
Although the present invention has been described in terms of specific embodiments it is anticipated that alterations and modifications thereof will no doubt become apparent to those skilled in the art. It is therefore intended that the following claims be interpreted as covering all such alterations and modification as fall within the true spirit and scope of the invention.
Upon the analog to digital conversion, the digitized signals can be conveniently processed by digital signal processing (DSP) circuitry 110. The digital signal processing circuitry 110 may be implemented in digital logics, field programmable gate array (FPGA), digital signal processor, or a combination of digital logics and microcontroller. The digital signal processing circuitry 110 will perform necessary receiving functions to receive the intended signal. For example, in an FM audio receiver, the DSP circuitry 110 will perform digital filtering, FM demodulation, de-emphasis, and stereo de-multiplexing to produce a pair of stereo audio signals.
The integrated receive unit 100 includes clock generation circuitry 130 to supply clocks required to operate various parts of the integrated receive unit 100. The clock generation circuitry 130 is responsible to generate the mixing signal 134 required by the mixer 104. The frequency of the local oscillator signal 134 is determined according to the channel selection signal 142. In the field of radio frequency receiver system, the mixing signal 134 is also called LO signal sometimes. The clock generation circuit 130 is also responsible to provide system clock 132 for digital circuits of the receiver such as various parts of the DSP module 110 and ADC 108. While a single output clock signal line 132 is shown in
In a conventional receiver, the clock generation circuit needs a stable and accurate reference clock so as to provide stable and accurate clocks for the system. The reference clock fref 144 provided to the clock generation circuit usually is generated using a crystal or a reference clock. When a stable and accurate reference clock is available to the clock generation circuit, the clock generation circuit may use a technique, known as phase-locked-loop (PLL) in the field, to generate an oscillating signal having frequency related to reference clock. The oscillating frequency usually is much higher than the required LO frequency. The oscillating frequency is then divided down and compared with the reference clock and a feedback signal is generated according to the phase/frequency difference between the divided-down oscillating signal and the reference clock signal. The feedback control signal will then adjust the tuning circuit of the oscillating circuit to cause the divided-down oscillating frequency equal to the reference clock frequency.
An exemplary prior-art clock generation circuit based on phase-locked-loop technology and a voltage controlled oscillator (VCO) is shown in
As shown in
The reference clock usually has a desired accuracy as required by the system and the reference clock may be generated using a crystal or a reference clock. The frequency can be selected as the one that the associated crystal is commonly available at low cost or the frequency is commonly available from other part of the system. For example, a crystal for real-time clock at 32.768 kHz is commonly available at low cost. Other crystals such as 12, 13 or 19.2 MHz can also be used at a slightly higher cost. For very low-cost applications, the crystal cost may still represent noticeable cost for the ASIC chip of an integrated radio frequency receiver even though the crystal cost is already low. In some applications, the system may have an accurate clock and there is no need for a crystal in these applications. Nevertheless, such accurate clock may not be always available. For example, in a stand-alone radio frequency receiver, any clock signal has to be generated internally within the clock generation system. Therefore, it is desirable to eliminate the need for a crystal or a reference clock signal to save system cost.
The scan logic 410 is responsible to cause the VCO to generate frequencies required to scan all channels intended to receive by the radio receiver and also to cause the PLL to provide a desired system clock so that the DSP circuit 310 will operate properly. Since there is no accurate reference clock available to the system at this time, the frequencies generated by the VCO are subject to substantial frequency offset, which may be as larger as 10% (10 MHz offset for an intended LO frequency of 100 MHz) or more. Nevertheless, even in the worst case of frequency offset, at least some channels will be received because the spectrum of total channels is wider than the maximum frequency offset of VCO. The scan logic 410 is coupled to receive the valid channel detected signal 342 as an indication that a candidate channel has been determined. The scan logic 410 will then stay tuned at the detected channel.
The mixer output is processed by the loop filter 456 to smooth out short term fluctuations on the ratio t. It will take some time for the NCO loop to settle down with a stable ratio t. When the ratio t is determined, the value is compared with the ratio of the frequency of the pilot signal 340 to the target frequency fSYS
The scan logic 410 is shown inside the frequency control logic 420 in
One implementation to utilize this feature is to use an intermediate frequency (IF) counter 540. The IF counter 540 value is obtained by counting the IF frequency over a period of time where the time is measured using a clock related to the system clock. The frequency of the IF signal is the difference between the frequency of the current RF input and the frequency of the LO signal. The frequency of the IF signal is pre-determined for a radio receiver. For example, 10.8 MHz has been popularly used in conventional FM broadcast radio receive. However, in modern digital implementation, the IF signal usually has much lower frequency, such as 225 kHz. The LO frequency and the system clock frequency are related because both are derived from the VCO signal. If the VCO frequency is accurate, the frequencies of LO and system clock will be known precisely. The IF counter value IFcnt 540 counted by the receiver can be compared with a computed IF count value IFcnt
Another embodiment of the present invention includes an iterative procedure as shown in
The invention may also involve a number of functions to be performed by a computer processor, a digital signal processor, a microprocessor, or field programmable gate array (FPGA). These processors can be configured to perform particular tasks according to the invention, by executing machine-readable software code or firmware code that defines the particular methods embodied by the invention. The software code or firmware codes may be developed in different programming languages and different format or style. The software code may also be compiled for different target platform. However, different code formats, styles and languages of software codes and other means of configuring code to perform the tasks in accordance with the invention will not depart from the spirit and scope of the invention.
The invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described examples are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.
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