Current amplifier circuit and a current amplifying type differential current converter circuit

Abstract

A current amplifier circuit includes a first, second, third and fourth transistor, each having the same polarity. The first transistor is connected in series with the second transistor and both have the collector and base thereof electrically connected. The third and fourth transistors are connected in series and the fourth transistor has a resistor connected between the base and collector. The third transistor has its base connected to the collector of the first transistor. A bias current is applied to the collector of the first transistor and an input current to be amplified is applied to the base of the fourth transistor. An amplified output current is obtained across the collector to emitter of the third transistor. In a differential amplifier circuit, a fifth transistor having the same polarity is connected with its base connected to the collector of the fourth transistor through a resistor. Additionally a resistor is connected between the base of the third transistor and the collector of the first transistor. The differential current outputs are taken across the third transistor and fifth transistor.

Description

BACKGROUND OF THE INVENTION

This invention relates to a current amplifier circuit and a current amplifying type differential amplifier converter circuit.

Conventionally, there is a current amplifier circuit, for example, shown in FIG. 5. In operation, if bias currents flowing through transistors T.sub.6, T.sub.7 and transistors T.sub.8, T.sub.9 are represented by I, I.sub.B and I.sub.X, respectively, the base voltage of transistor T.sub.8 is given by

2.multidot.(KT/q.multidot.I/I.sub.S) where K is the Bolzmann constant, T is an absolute temperature, q is the electron charge and I.sub.S is the collector reverse saturation current. When T=300.degree. K., KT/q=2.multidot.26.multidot.10.sup.-3, and the base voltage of the transistor T.sub.8 is given by 2.multidot.(26.multidot.10.sup.-3 ln I/I.sub.S)=26.multidot.10.sup.-3 .multidot.(ln I.sub.B /I.sub.S +ln I.sub.X /I) ln (I/I.sub.S).sup.2 =ln I.sub.B I.sub.X /I.sub.S.sup.2

Rearranging this equation as I.sub.B =I.sub.X /hFE,

I.sup.2 =I.sub.X.sup.2 /hFE Then I.sub.X =I.sqroot.hFE

Thus the biasing current I.sub.X flowing through transistor T.sub.8 is .sqroot.hFE times as large as the biasing current I.

The current gain is approximately hFE/2 if an input current is represented by i.

In the above circuit arrangement, the biasing current I.sub.X and the current gain are greatly dependent on hFE and influenced by variations in the elements used, so that the arrangement is difficult to design and not suitable for integration.

The object of this invention is to provide a current amplifier circuit and a current amplifying type differential current converter circuit in which the biasing current and the current gain are less dependent on hFE and not influenced by variation in the elements used.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an electric circuit diagram showing one example of an electric amplifier circuit according to this invention.

FIG. 2 is an electric circuit diagram showing another embodiment.

FIG. 3 is an electric circuit diagram showing one example of an electric current amplifier differential current converter circuit.

FIG. 4 is an electric circuit diagram showing another embodiment.

FIG. 5 is an electric circuit diagram showing one example of conventional current amplifier circuits.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In FIG. 1, a first transistor T.sub.1 in diode connection is connected in series with a second transistor T.sub.2 in diode connection and having a resistor R.sub.1 connected across the collector and base thereof. The collector of transistor T.sub.1 is connected to the base of a third transistor T.sub.3. A fourth transistor T.sub.4 with a resistor R.sub.2 across the collector and base thereof is connected in series with transistor T.sub.3.

In the above arrangement, if the biasing currents flowing through transistors T.sub.1, T.sub.2 are shown by I and biasing currents flowing through transistors T.sub.3, T.sub.4 are shown by I.sub.X, the base potential of transistor T.sub.3 is given by

26.multidot.10.sup.-3 ln I/I.sub.S +26.multidot.10.sup.-3 ln I/I.sub.S +RI/hFE=26.multidot.10.sup.-3 ln I.sub.X /I.sub.S +26.multidot.10.sup.-3 ln I.sub.X /I.sub.S +RI.sub.X /hFE wherein R.sub.1 =R.sub.2 =R. Therefore, 2.multidot.26.multidot.10.sup.-3 ln I/I.sub.X =(I.sub.X -I).multidot.R/hFE when I.sub.X =I, the right and left sides are equal. Namely, the currents flowing through transistors T.sub.3, T.sub.4 are equal to those flowing through transistors T.sub.1, T.sub.2.

If an input current applied to the base of transistor T.sub.4 is shown by i, it is divided into i.sub.1, i.sub.2, namely,

i=i.sub.1 +i.sub.2

Thus a signal current component I.sub.cs of the collector current flowing through transistor T.sub.4 is given by

I.sub.cs =hFE.multidot.i.sub.1

A voltage drop across the emitter resistance RE of each of transistors T.sub.3, T.sub.4 due to this current is given by

2R.multidot.I.sub.cs =2R.sub.E .multidot.hFE.multidot.i.sub.1 wherein R.sub.E is the AC emitter resistance of transistor T.sub.3 and R=R.sub.1 =R.sub.2.

This voltage drop serves to reduce the voltage applied to resistor R to thereby reduce the current flowing through resistor R.sub.2. This reduced portion equals current i.sub.2, then

i.sub.2 =2R.sub.E hFE.multidot.i.sub.1 /R

The current gain of this circuit is given by ##EQU1##

When hFE is large, Ics/i becomes approximately R.sub.E and hence the gain is determined irrespective of hFE. Accordingly, current Ix flowing through the collector of transistor T.sub.3 can be represented as ##EQU2## when R<<hFE

As just described above, the biasing current and current gain of the circuit according to this invention are not dependent on hFE of the transistors, so that the circuit is easy to design and suitable for integration.

FIG. 2 shows another embodiment which includes a circuit obtained by eliminating resistor R.sub.1 from the structure of FIG. 1. This circuit also provides substantially the same effect as the first mentioned embodiment except for biasing currents I and Ix given by

I/I.sub.x =Exp ((R.sub.2 I.sub.x /hFE)/2.multidot.26.multidot.10.sup.-3) when R.sub.2 =0, I=I.sub.x.

A current amplifying type differential current converter circuit constructed by utilizing the above techniques will now be described. In FIG. 3, first and second transistors T.sub.1, T.sub.2 are in diode connection through resistors R.sub.3 and R.sub.1, respectively. The collector of transistor T.sub.1 is connected through a resistor R.sub.4 to the base of third transistor T.sub.3 to which a fourth transistor T.sub.4 in diode connection through resistor R.sub.2 is connected in series with transistor T.sub.3. The collector of transistor T.sub.4 is connected through a resistor R.sub.5 to the base of a fifth transistor T.sub.5.

In the above arrangement, if the biasing currents flowing through transistors T.sub.1, T.sub.3, T.sub.5 are shown by I, I.sub.1, I.sub.2, respectively, the collector voltage of transistor T.sub.1 is given by ##EQU3## when R.sub.1 =R.sub.2 =R.sub.3 =R.sub.4 =R.sub.5 =R.

The collector voltage of transistor T.sub.4 is given by

26.multidot.10.sup.-3 ln I.sub.1 /I.sub.S +RI.sub.1 /hFE26.multidot.10.sup.-3 ln I.sub.2 /I.sub.S +RI.sub.2 /hFE (2)

Rearranging this equation,

26.multidot.10.sup.-3 ln I.sub.1 /I.sub.2 =R.multidot.(I.sub.2 -I.sub.1)/hFE (3)

This equation holds when I.sub.1 =I.sub.2, so that I.sub.1 =I.sub.2. Substituting this into equation (1),

2(26.multidot.10.sup.-3 ln I/I.sub.1)=2.multidot.R(I.sub.1 -I)/hFE (4)

This equation holds when I.sub.1 =I, so that I.sub.1 =I.

Namely, biasing currents I, I.sub.1, I.sub.2 are equal currents.

If a signal current i is applied to the base of transistor T.sub.4, it is divided into i.sub.1 and i.sub.2. If the emitter resistances of transistors T.sub.3 and T.sub.4 are shown by R.sub.E, then

i.sub.2 =(i.sub.1 hFE.multidot.2R.sub.E +R.multidot.i.sub.1 hFE/hFE)/R (5) i=i.sub.1 +i.sub.2 (6)

Substituting equation (6) into (5) and eliminating i.sub.2,

i=2i.sub.1 +(i.sub.1 .multidot.hFE.multidot.2R.sub.E)/R (7) LU i.sub.i /i=1/(2+(2R.sub.E .multidot.hFE)/R) (8)

Since the current flowing through transistor T.sub.4 is hFE.multidot.i, the current gain of transistor T.sub.4 is given by

i.sub.1 hFE/i=hFE/(2R.sub.E .multidot.hFE)/R) (9)

In this equation, as hFE increases, the current gain becomes approximately R/2R.sub.E.

If the amplified current is given by I.sub.a, the signal current I.sub.x flowing through transistor T5 is given by ##EQU4## from the relationship with the collector voltage of transistor T.sub.1. Transforming this equation,

26.multidot.10.sup.-3 ln I.sup.2 /(I+I.sub.a)(I+I.sub.x)=R/hFE(I+I.sub.a +I+I.sub.x -2I) (11)

When currents I.sub.a, I.sub.x are at a small-signal level, the equation (11) holds when I.sub.x=-I.sub.a. Therefore, I.sub.x =-I.sub.a, so that a current flows through transistor T.sub.5, which current has a phase opposite to that of a signal current flowing through transistor T.sub.4.

Accordingly, collector current I.sub.1 of the transistor T.sub.4 and collector current I.sub.2 of the transistor T.sub.5 are represented as,

I.sub.1 =I+I.sub.a =i+R/(2R.sub.E)i I.sub.2 =I+I.sub.x =I-I.sub.a .apprxeq.I-Ri/2R.sub.E

Thus, the above arrangement provides an electric current amplifying type differential conversion circuit.

FIG. 4 shows an embodiment in which transistors T.sub.1, T.sub.2 have no resistors across the bases and emitters thereof and have an effect similar to that of the previous embodiment. In this circuit, the relationship between biasing currents I, I.sub.1, and I.sub.2 is given by

I.sub.1 =I.sub.2 I/I.sub.1 =Exp (R.multidot.I.sub.1 /26.multidot.10.sup.-3 hFE) (12) When R=R.sub.2 =R.sub.4 =R.sub.5 =0, I=I.sub.1.

According to this invention, the biasing currents and the current gain are less dependent on hFE, and less influenced by variations in the components, so that the circuit is easy to design and is suitable for integration.

Claims

1. An electric current amplifier circuit comprising: a first, a second, a third and a fourth transistor each having the same polarity, wherein the first transistor has an electrically connected collector and base and is connected in series with the second transistor having an electrically connected collector and base, wherein the collector of the first transistor is connected to a base of the third transistor, wherein the fourth transistor has an emitter with a resistance R.sub.E and a collector and base connected through a resistor having a resistance R and the fourth transistor is connected in series with the third transistor, wherein the first transistor is receptive of a bias current I flowing therethrough, and wherein the base of the fourth transistor is receptive of an input signal current i supplied thereto to produce an amplified output signal current approximately I+R.multidot.i/2R.sub.E flowing through the third transistor.

2. An electric current amplifier circuit according to claim 1, wherein the collector and the base of the first transistor are directly electrically connected and the collector and the base of the second transistor are electrically connected through a resistor.

3. An electric current amplifier circuit according to claim 1, wherein the collector and the base of the first transistor are directly electrically connected and the collector and the base of the second transistor are directly electrically connected.

4. An electrical current amplifier circuit according to claim 1, wherein the first transistor has an emitter connected to the collector of the second transistor to effect the series connection thereof and wherein the third transistor has an emitter connected to the collector of the fourth transistor to effect the series connection thereof.

5. An electric current amplifying type differential current conversion circuit comprising a first, a second, a third, a fourth and a fifth transistor, each having the same polarity, wherein the first transistor has an electrically connected collector and base and is connected in series with the second transistor having an electrically connected collector and base, wherein the collector of the first transistor is connected to a base of the third transistor through a first resistor, wherein the fourth transistor has an emitter with a resistance R.sub.E and a collector and base connected through a second resistor, wherein the fourth transistor is connected in series with the third transistor, wherein the fifth transistor has a base connected to the collector of the fourth transistor through a third resistor wherein the resistance of the first, second and third resistors is R, wherein the first transistor is receptive of a bias current I flowing therethrough and wherein the base of the fourth transistor is receptive of an input signal current i to produce differential amplified output signal currents of approximately I+R.multidot.i/2R.sub.E, I-R.multidot.i/2R.sub.E, flowing through the third transistor and the fifth transistor respectively.

6. An electric current amplifying type differential current conversion circuit according to claim 5, wherein the collector and the base of the first transistor are electrically connected through a resistor and the collector and the base of the second transistor are electrically connected through a resistor.

7. An electric current amplifying type differential current conversion circuit according to claim 5, wherein the collector and the base of the first transistor are directly electrically connected and the collector and the base of the second transistor are directly electrically connected.

8. An electrical current amplifying type differential current conversion circuit according to claim 5, wherein the first transistor has an emitter connected to the collector of the second transistor to effect the series connection thereof and wherein the third transistor has an emitter connected to the collector of the fourth transistor to effect the series connection thereof.

9. A current amplifier circuit comprising:

first and second series connected transistors having the same polarity and each having an electrically connected base and collector;

third and fourth series connected transistors having the same polarity as the first and second transistors, wherein the third transistor has a base connected to the collector of the first transistor and the fourth transistor has a collector and a base and a resistor having a resistance R connected between the collector and base thereof;

means for applying a bias current I to the collector of the first transistor;

input means for applying input current i to be amplified to the base of the fourth transistor; and

output means for providing an amplified output current across a collector and emitter of the third transistor.

10. The circuit according to claim 9, wherein the fourth transistor has an emitter resistance of R.sub.E and the output current is approximately I+R.multidot.i/2R.sub.E.

11. The circuit according to claim 9, wherein the base and collector of the first transistor are directly connected and wherein the base and collector of the second transistor are connected through a resistor.

12. The circuit according to claim 9, wherein the base and collector of the first transistor are directly connected and wherein the base and collector of the second transistor are directly connected.

13. The circuit according to claim 9, wherein the first transistor has an emitter connected to the collector of the second transistor to effect the series connection thereof and wherein the third transistor has an emitter connected to the collector of the fourth transistor to effect the series connection thereof.

14. A differential current amplifier circuit comprising:

first and second series connected transistors having the same polarity and each having an electrically connected base and collector;

third and fourth series connected transistors having the same polarity as the first and second transistors, wherein the third transistor has a base connected to the collector of the first transistor through a first resistor and the fourth transistor has a collector and a base and a second resistor connected between the collector and base thereof;

a fifth transistor having the same polarity as the first and second transistors and a base connected to the collector of the fourth transistor through a third resistor;

means for applying a bias current I to the collector of the first transistor;

input means for applying input current i to be amplified to the base of the fourth transistor; and

output means for providing two amplified differential output current across a collector and emitter of the third transistor and the fifth transistor.

15. The circuit according to claim 14, wherein the first, second and third resistors have a resistance R and wherein the fourth transistor has an emitter resistance of R.sub.E and the differential output currents across the third and fifth transistors respectively are approximately I+R.multidot.i/2R.sub.E and I-R.multidot.i/2R.sub.E.

16. The circuit according to claim 14, wherein the base and collector of the first transistor are connected through a resistor and wherein the base and collector of the second transistor are connected through a resistor.

17. The circuit according to claim 14, wherein the base and collector of the first transistor are directly connected and wherein the base and collector of the second transistor are directly connected.

18. The circuit according to claim 14, wherein the first transistor has an emitter connected to the collector of the second transistor to effect the series connection thereof and wherein the third transistor has an emitter connected to the collector of the fourth transistor to effect the series connection thereof.