Current amplifying integrated circuit

Abstract

Present invention proposes a dramatic improvement of CMOS IC technology by providing high speed bipolar current amplifiers compatible with CMOS technological process while retaining the footprint compatible to one of standard CMOS devices. This invention promises further increase of speed of ICs as well as a reduction of power dissipation.

Description

DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the circuit of this invention ready for use as a current amplifier, such as to replace reading transistors in a memory IC. There are two implementations of the circuit of the invention shown in the drawing. One is for replacement of an N-type field effect transistor and the other one is for replacement of a P-type field effect transistor.

For the P-type circuit: The source 2 of the circuit and the gate 1 of the circuit are to be connected in place of the source and gate of the transistor being replaced. The emitter 5 of the circuit is to be connected in place of the drain of the transistor to be replaced. The drain 4 of the FET is the base of the NPN transistor. The collector 3 of the NPN transistor is the well of the FET and connected to a positive power supply rail.

For the N-type circuit: The source 7 of the circuit and the gate 8 of the circuit are to be connected in place of the source and gate of the transistor being replaced. The emitter 9 of the circuit is to be connected in place of the drain of the transistor to be replaced. The drain 10 of the FET is the base of the PNP transistor.

The collector 6 of the PNP transistor is the well of the FET and connected to a negative power supply rail.

FIG. 2 shows the cross-sections of two types of the circuits of the invention. One is having a P-type collector/well area 6 for the N-type FET and the other one having an N-type collector/well area 3 for the P-type FET. Those cross-sections correspond to the circuits shown in FIG. 1. Emitter regions 5, 9 as they are shown in the drawing are placed inside a semiconductor body within base regions 4, 10; as it is known to those skilled in the art emitters 5, 9 could be formed in additional poly-silicon layer having a direct contact to the base regions 4, 10 as it may be more convenient for manufacturing.

The principle application of the circuit of this invention is an inverting amplifier made into a complimentary configuration.

FIG. 3 shows the circuit of this invention as it is employed to form a complimentary inverter circuit such as to replace a CMOS inverter circuit in an IC. The inverter circuit comprises two complimentary circuits of this invention where collectors are connected to power rails 12, 14 and the sources of field effect transistors are connected to their collectors. The input 11 of the inverter is the gates of the field effect transistors connected together as the gates of the inverter being replaced. The emitters connected together form the output 13 of the inverter.

FIG. 4 shows the cross-sections of the inverter utilizing the circuits of the invention. The circuit of first polarity is having a P-type collector/well area 12 and the other one is having an N-type collector/well area 14. Those cross-sections correspond to the circuits shown in FIG. 3. Emitter regions 13 as they are shown in the drawing are placed inside a semiconductor body within base regions; as it is known to those skilled in the art, emitters could be formed in an additional poly-silicon layer having a direct contact to the base regions as it may be more convenient for manufacturing. Each pare of the field effect and bipolar transistors is having its reinforced well/collector region. It is preferred that the well of the inverter or the gate, employing a current amplifier, will be separated by P+ or N+ regions from the well containing adjacent CMOS circuits or other current amplifiers.

FIG. 5 shows the circuit of this invention as it is employed to form a complimentary NAND circuit such as to replace a CMOS NAND circuit in an IC. The inverter circuit comprises two complimentary circuits of this invention where collectors are connected to power rails 15, 18. The NAND circuit is comprised of four FETs and two bipolar transistors. Those are grouped in complimentary circuits, each including two FETs and one bipolar. One circuit is connected to a positive power rail 18 and contains two P-channel FETs having a common drain which is the base of bipolar transistor. The sources of these FETs are connected to a positive power supply 18. Complimentary circuit is connected to a negative power rail 15 and contains two N-channel FETs so the drain of one FET is the source of another; yet another source is connected to a negative power rail 15 and another drain as the base of a bipolar transistor. The inputs 16, 17 of the circuit are the gates of the field effect transistors connected together as the inputs of the NAND circuit being replaced. The emitters connected together form the output 19 of the NAND circuit.

FIG. 6 shows the cross-sections of the NAND circuit utilizing the invention. One is having a P-type collector/well area 15 and another one having an N-type collector/well area 18. Those cross-sections correspond to the circuits shown in FIG. 5. Emitter regions 19 as they are shown in the drawing are placed inside a semiconductor body within base regions; as it is known to those skilled in the art emitters could be formed in an additional poly-silicon layer having a direct contact to the base regions as it may be more convenient for manufacturing.

Claims

1. A monolithic circuit comprising: a bipolar transistor having emitter, base and collector regions;at least one field effect transistor having source and drain regions;said emitter region positioned within said base region;said drain and said source regions positioned within said collector region;at least one drain region is the same and one with said base region.

2. An isolating structure for a monolithic circuit formed in a body of semiconductor material having flat surface: said structure having adjacent to the surface internal region, wall-like preferably orthogonal to the surface peripheral region, and preferably parallel to the surface bottom region;said peripheral region and said bottom region being formed by impurities of relatively high concentration compare to the concentration of the impurities in the internal region;said peripheral region and said bottom region forming together complete conductive barrier on all sides of the structure but the surface;said peripheral region being connected from the surface to a constant electric potential, such as positive or negative power rail.

3. A monolithic circuit comprising: a bipolar transistor having emitter, base and collector regions;at least one field effect transistor having source and drain regions;said emitter region positioned within said base region;said drain and said source regions positioned within said collector region;at least one drain region is the same and one with said base region;said collector having adjacent to the surface internal region, wall-like preferably orthogonal to the surface peripheral region, and preferably parallel to the surface bottom region;said peripheral region and said bottom region being formed by impurities of relatively high concentration compare to the concentration of the impurities in the internal region;said peripheral region and said bottom region forming together complete conductive barrier on all sides of the collector but the surface;said peripheral region being connected from the surface to a constant electric potential, such as positive or negative power rail.