Current control driver and display device

Abstract

In a current control driver that drives an active matrix device, a write current can be set larger and unevenness in currents can be reduced between elements receiving the currents. In the current control driver having an element circuit for each of the elements comprising a converting unit for converting an applied current into a voltage, a retaining unit for retaining the voltage converted by the converting unit, and a driving unit that converts the voltage retained by the retaining unit into an output current and supplies the output current, the converting unit is shared between two or more of the element circuits and a switch located between the shared converting units connects two or more of the converting units to one of the elements during a current supply period for the element.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a circuit showing a current control driver of a first embodiment of the present invention;

FIG. 2 is a timing chart showing how scanning lines are selected in the circuit in FIG. 1;

FIG. 3 is a circuit diagram showing one state of operation in the circuit shown in FIG. 1;

FIG. 4 is a timing chart showing how the scanning lines are selected for the state of operation shown in FIG. 3;

FIG. 5 is a circuit diagram showing another state of operation in the circuit in FIG. 1;

FIG. 6 is a timing chart showing how the scanning lines are selected for the state of operation of the circuit shown in FIG. 5;

FIG. 7 is a circuit diagram showing still another state of operation of the circuit shown in FIG. 1;

FIG. 8 is a timing chart showing how the scanning lines are selected for the state of operation of the circuit shown in FIG. 7;

FIG. 9 is a diagram of a circuit showing a current control driver of a second embodiment of the present invention;

FIG. 10 is a timing chart showing how scanning lines are selected in the circuit in FIG. 9;

FIG. 11 is a circuit diagram showing a state of operation in the circuit shown in FIG. 9;

FIG. 12 is a timing chart showing how the scanning lines are selected for the state of operation shown in FIG. 11;

FIG. 13 is a circuit diagram showing another state of operation of the circuit in FIG. 9;

FIG. 14 is a timing chart showing how the scanning lines are selected for the state of operation in the circuit shown in FIG. 13;

FIG. 15 is a diagram of a circuit showing a current control driver of a third embodiment of the present invention;

FIG. 16 is a timing chart showing how scanning lines are selected for a state in the circuit shown in FIG. 15;

FIG. 17 is a circuit diagram showing another state of operation of the circuit in FIG. 15;

FIG. 18 is a timing chart showing how the scanning lines are selected for the state of operation of the circuit shown in FIG. 17;

FIG. 19 is a circuit diagram showing still another state of operation of the circuit shown in FIG. 15;

FIG. 20 is a timing chart showing how the scanning lines are selected for the state of operation of the circuit shown in FIG. 19;

FIG. 21 is a diagram of a circuit showing a current control driver of a fourth embodiment of the present invention;

FIG. 22 is a timing chart showing how scanning lines are selected for a state in the circuit shown in FIG. 21;

FIG. 23 is a circuit diagram showing another state of operation of the circuit in FIG. 21;

FIG. 24 is a timing chart showing how the scanning lines are selected for the state of operation of the circuit shown in FIG. 23;

FIG. 25 is a circuit diagram showing still another state of operation of the circuit shown in FIG. 21;

FIG. 26 is a timing chart showing how the scanning lines are selected for the state of operation of the circuit shown in FIG. 25;

FIG. 27 is a diagram of a circuit showing a current control driver of a fifth embodiment of the present invention;

FIG. 28 is a timing chart showing how scanning lines are selected for a state in the circuit shown in FIG. 27;

FIG. 29 is a circuit diagram showing another state of operation of the circuit in FIG. 27;

FIG. 30 is a timing chart showing how the scanning lines are selected for the state of operation of the circuit shown in FIG. 29;

FIG. 31 is a circuit diagram showing an example of a conventional current control driver;

FIG. 32 is a block diagram showing a conventional current control driver;

FIG. 33 is a circuit diagram showing another example of a conventional current control driver; and

FIG. 34 is a circuit diagram showing still another example of a conventional current control driver.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 shows a current control driver of a first embodiment of the present invention. This current control driver is for driving OLEDs (organic EL elements) of an organic EL display device as an example, and only circuits for 3 pixels (pixels Gn−1, Gn, and Gn+1) aligned consecutively in a column are shown for the sake of simplification. The current control driver shown in FIG. 1 is connected to the previously described scanning line driver 1 and the data line driver 2 shown in FIG. 32 to comprise the display device. In this embodiment, 3 scanning lines are used for each row as will be described later.

In the current control driver in this embodiment, a circuit Pn for a pixel Gn comprises an organic EL element (OLED), a capacitor (Cs), and TFTs (T1, T2, T3, T4 and T5). The anode of OLED is connected to a positive power source VDD. The drain of T2 is connected to the cathode of OLED and the source thereof is grounded. The capacitor Cs is connected between the gate of T2 and a ground (a reference voltage point). The drain of T4 is connected to a data line 10 while the gate thereof is connected to a first scanning line ScanA[n]. The drain of T3 is connected to the source of T4 while the source thereof is connected to the gate of T2. The gate of T3 is connected to a second scanning line ScanB[n]. The drain and the gate of T1 are electrically short-circuited to form a so-called diode connection and connected to the source of T4 and the drain of T3, respectively. The source of T1 is grounded. The gate of T5 is connected to a third scanning line ScanC[n] and the drain thereof is connected to the drain of T3.

In this embodiment, N-channel MOS FETs are used as T1 and T2 while P-channel MOS FETs are used as T3, T4, and T5.

As shown in FIG. 1, circuits Pn−1 and Pn+1 for the pixels Gn−1 and Gn+1 are basically formed in the same manner as the circuit Pn for the pixel Gn. The drain and the source of T5 of each of the pixel circuits are respectively connected to the source and the drain of T5 in the neighboring pixel circuits.

In the circuit Pn−1, Pn, or Pn+1 having the above configuration, T4 functions as a first scanning switch for selectively supplying a current Idata from the data line 10 to T1. The transistor T1 functions as a converting unit for converting the current Idata supplied from the data line 10 via T4 into a voltage, and T1 also forms a current mirror, circuit together with the transistor T2.

The transistor T3 functions as a second scanning switch for selectively supplying the voltage converted from the current by T1 to the capacitor Cs. The capacitor Cs functions as a retaining unit for retaining the voltage converted from the current by T1 and supplied via T3. The transistor T2 converts the voltage retained by the capacitor Cs into a current, and causes OLED to emit light by supplying the current to OLED. In other words, T2 functions as a driving unit. The element OLED is an electric optical element whose luminance changes according to the current flowing therethrough.

The operation of writing luminance data in the circuit Pn−1, Pn, or Pn+1 of the above configuration will be described. As has been described above, the first to third scanning lines ScanA, ScanB, and ScanC are located for one row in this embodiment. How the three scanning lines are selected in each row, that is, the scanning lines ScanA[n−1], ScanB[n−1], and ScanC[n−1] for a row n−1, the scanning lines ScanA[n], ScanBB[n], and ScanC[n] for a row n, and the scanning lines Scan[n+1], ScanB[n+1], and ScanC[n+1] for a row n+1, is basically shown by a timing chart shown in FIG. 2. In FIG. 2, the low level of each waveform refers to a state of the corresponding line being selected while the high level thereof refers to a non-selected state.

At the time of writing in the row n−1, for example, the three scanning lines ScanA[n−1], ScanB[n−1], and ScanC[n−1] are all in selected states in a write period time1 as shown by circles shown in a timing chart in FIG. 4, and the transistors T4, T3, and T5 in the row n−1 are all changed to become conductive as shown in FIG. 3. In FIG. 3 (and hereinafter), the transistors T4, T3 and T5 are shown as symbols representing switches, for the sake of easier understanding of conductive or non-conductive states.

At the time of writing in the row n, the three scanning lines ScanA[n], ScanB[n], and ScanC[n] are all selected in a write period time2 as shown by circles in a timing chart shown in FIG. 6. In response, the transistors T4, T3, and T5 in the row n are set to become conductive as shown in FIG. 5. A current Idata in accordance with luminance data is supplied to the data line 10 in this state. The current Idata is supplied to T1 via T4 that is in the conductive state. By the current Idata flowing through T1, a voltage corresponding to the current Idata occurs at the gate of T1. The voltage is retained by the capacitor Cs via T3 that is in the conductive state.

As shown by FIG. 6, the scanning line ScanA[n−1] for the immediately preceding row n−1 is also in the selected state in the write period time2. Therefore, T4 in the row n−1 is also in a conductive state as shown by FIG. 5. In addition, the scanning line ScanC[n] is selected and T5 of the row n is in the conductive state. (At this time, T5 and T3 for the row n−1 are not conductive). Therefore, T1 of the row n−1 and T1 of the row n are in parallel connection, and the drain-gate voltage generated by the current Idata is averaged and retained by the capacitor Cs.

A current in accordance with the voltage retained by the capacitor Cs flows to OLED via T2. In this manner, OLED starts emission of light. When the scanning lines ScanB[n], ScanC[n] and ScanA[n−1] become non-selected thereafter (that is, at high level), the operation of writing the luminance data to the pixel Gn is completed. In FIG. 5 (and hereinafter), the capacitor Cs retaining the voltage is surrounded by a broken circle.

As has been described above, this embodiment has been designed to let the current Idata flow also in T1 of the row n−1, which is the immediately preceding row in the scanning order, upon writing into the pixel Gn in the row n. Therefore, if I1 refers to a current that causes emission of light at a minimum value of the write current Idata, that is, at a minimum luminance value, the data line 10 allows a current whose value is double of I1 to flow therethrough. Allowing the larger current to flow through the data line 10 leads to writing by the accurate current Idata corresponding to a desired luminance value while reducing effects caused by a wiring capacitance and a driver capacitance.

Furthermore, in this embodiment, the current determined by a characteristic of T1 in the row n as well as T1 in the row n−1 is supplied to OLED upon writing in the pixel Gn of row n. Likewise, upon writing in the pixel Gn+1 in the row n+1, a current determined by the characteristic of T1s in the rows n+1 and n is supplied to OLED. Therefore, even in the case where the characteristic varies between T1s in the respective rows, the characteristic is averaged. Consequently, large fluctuation due to the variation in the characteristic of T1s can be prevented in the currents supplied to OLEDs, and uneven display (uneven luminance) between the pixels can be suppressed.

At the time of writing in the row n+1, the three scanning lines ScanA[n+1], ScanB[n+1], and ScanC[N+1] are all in selected states at a write period time3 as shown by the circles in a timing chart in FIG. 8. The scanning line ScanA[n] is also in the selected state in the write period time3. Therefore, the circuit is in a state shown in FIG. 7, and a current Idata in the data line 10 flows in T1s of the rows n+1 and n in the write period time3. Consequently, a larger current can be supplied to the data line 10, and writing can be carried out by the accurate current Idata corresponding to a desired luminance value while the effects caused by wiring capacitance and driver capacitance can be reduced. Uneven display (uneven luminance) between the pixels caused by variation in the characteristic of T1s can also be reduced, as has been described above.

A current control driver of a second embodiment of the present invention will be described next with reference to FIGS. 9 to 14. The current control driver in this embodiment is to drive organic EL elements (OLEDs) in an organic EL display device as an example. FIG. 9 shows the configuration of the driver, which is the same as the first embodiment. In FIG. 9 (and hereinafter), the same components as in FIG. 1 have the same reference codes, and detailed description thereof is omitted unless specifically necessary. In the second embodiment, how three scanning lines ScanA, ScanB, and ScanC are selected is different from the first embodiment, and is shown by a timing chart in FIG. 10.

In the current control driver in this embodiment, scanning lines ScanA[n−1] and ScanB[n−1] are selected in a write period time2 as shown by circles in a timing chart in FIG. 12 at the time of writing in a row n−1, for example. A scanning line ScanC[n−1] is not selected in this case. The scanning lines ScanA[n] and ScanC[n] in a row n located immediately after the row n−1 are also selected in the write period time2. Therefore, the circuit is in a state shown in FIG. 11 in the write period time2, and a current Idata in a data line 10 is supplied to T1 of the row n−1 and to T1 of the row n. A voltage occurring at the gate of T1 in the row n is retained by a capacitor Cs in the row n−1 via T5 in the row n.

At the time of writing in the row n, the scanning lines ScanA[n] and ScanB[n] are selected in a write period time3 as shown by circles in a timing chart in FIG. 14 while the scanning line ScanC[n] is not selected. In the write period time3, scanning lines ScanA[n+1] and ScanC[n+1] are also selected in a row n+1 that immediately follows the row n. Consequently, the circuit is in a state shown by FIG. 13 in the write period time3. A current Idata in the data line 10 is supplied to T1 of the row n and to T1 of the row n+1. A voltage occurring at the gate of T1 in the row n+1 is retained by a capacitor Cs in the row n via T5 of the row n+1.

As has been described above, in this embodiment, letting the current Idata flow through the two T1s allows the larger current to flow in the data line 10. Therefore, writing can be carried out by the accurate current Idata corresponding to desired luminance while effects caused by a wiring capacitance and a driver capacitance can be suppressed. Uneven display (uneven luminance) between pixels caused by variation in a characteristic of T1s can also be reduced, as has been described above.

A current control driver of a third embodiment of the present invention will be described next with reference to FIGS. 15 to 20. The current control driver in this embodiment is to drive organic EL elements (OLEDs) in an organic EL display device as an example. FIG. 15 shows the configuration of the driver, which is the same as the first embodiment. In the third embodiment, how three scanning lines ScanA, ScanB, and ScanC are selected is different from the first embodiment, and is shown by a timing chart in FIG. 16.

Upon writing in a row n−1 in the current control driver in this embodiment, for example, scanning lines ScanA[n−1], ScanB[n−1], and ScanC[n−1] are all selected in a write period time1 as shown by circles in the timing chart in FIG. 16. A scanning line ScanA[n−2] is also selected in the write period time1 in a row n−2 that immediately precedes the row n−1. In addition, the scanning lines ScanA[n] and ScanC[n] are also selected in a row n that immediately follows the row n−1. Therefore, the circuit is in a state shown by FIG. 15 in the write period time1, and a current Idata in a data line 10 is supplied to T1 in the row n−1 as well as to T1s in the rows n−2 and n.

At the time of writing in the row n, the scanning lines ScanA[n] and ScanC[n] as well as a scanning line ScanB[n] are all selected in a write period time2 as shown by circles in a timing chart in FIG. 18. The scanning line ScanA[n−1] in the immediately preceding row n−1 and scanning lines ScanA[n+1] and ScanC[n+1] in the immediately following row n+1 are also selected in the write period time2. Therefore, the circuit is in a state shown by FIG. 17 in the write period time2, and a current Idata in the data line 10 is supplied to T1 of the row n and to T1s in the rows n−1 and n+1.

Upon writing in the row n+1, the scanning lines ScanA[n+1] and ScanC[n+1] as well as a scanning line ScanB[n+1] are all selected in a write period time3 as shown by circles in a timing chart in FIG. 20. In addition, the scanning line ScanA[n] in the immediately preceding row n and scanning lines ScanA[n+2] and ScanC[n+2] in the immediately following row n+2 are also selected in the write period time3. Therefore, the circuit is in a state shown by FIG. 19, and a current Idata in the data line 10 is supplied not only to T1 in the row n+1 but also to T1s in the rows n and n+2.

As has been described above, upon writing in one of pixels in one of the rows in this embodiment, the current Idata also flows to T1s in the immediately preceding and following rows. Therefore, if I1 denotes a current causing emission of light at a minimum value of the write current Idata, that is, at a minimum luminance value, the data line 10 allows the current that is triple of I1 to flow therethrough. Letting the larger current to flow through the data line 10 in this manner enables writing by the accurate current Idata corresponding to desired luminance while effects caused by a wiring capacitance and a driver capacitance can be suppressed.

A current control driver of a fourth embodiment of the present invention will be described with reference to FIGS. 21 to 26. The current control driver in this embodiment is also to drive OLEDs (organic EL elements) in an organic EL display device as an example, and the configuration thereof is shown in FIG. 21. In this embodiment, the scanning line ScanC in the first embodiment is omitted, and T5 as well as T3 in each row are set to be in conductive states or in non-conductive states by a scanning line ScanB of the same row. In the fourth embodiment, how the scanning line ScanB as well as a scanning line ScanA are selected is shown by a timing chart shown in FIG. 22.

Upon writing in a row n−1 in this embodiment, two scanning lines ScanA[n−1] and ScanB[n−1] are all selected in a write period time1 as shown by circles in the timing chart in FIG. 22. Transistors T3, T5 as well as T4 in the row n−1 are all in conductive states as shown by FIG. 21.

At the time of writing in a row n, the two scanning lines ScanA[n] and ScanB[n] are selected in a write period time2 as shown by circles in a timing chart in FIG. 24. In response, transistors T4, T3, and T5 in the row n are all in conductive states as shown by FIG. 23. In addition, the scanning line ScanA[n−1] in the immediately preceding row n−1 is also in the selected state, and T4 in the row n−1 is in the conductive state as shown by FIG. 23. Furthermore, T5 in the row n is in the conductive state due to the scanning line ScanB[n] being selected. Therefore, a current Idata in a data line 10 is supplied to T1 in the row n and to T1 in the row n−1. A voltage occurring in response to the current in T1s is retained by a capacitor Cs in the row n.

At the time of writing in a row n+1, two scanning lines ScanA[n+1] and ScanB[n+1] are selected in a write period time3 as show by circles in a timing chart in FIG. 26. In response, transistors T4, T3, and T5 in the row n+1 are all in conductive states as shown by FIG. 25. Since the scanning line ScanA[n] in the immediately preceding row n is also in the selected state in the write period time3, T4 in the row n is in the conductive state as shown by FIG. 25. Furthermore, the transistor T5 in the row n+1 is conductive due to the scanning line ScanB[n+1] being selected. Therefore, a current Idata in the data line 10 is supplied to T1 in the row n+1 as well as to T1 in the row n. A voltage occurring in response to the current in T1s is retained by a capacitor Cs in the row n+1.

As has been described above, upon writing in a pixel Gn in the row n in this embodiment, the current Idata can flow in T1 of the immediately preceding row n−1. If I1 refers to a current causing emission of light at a minimum value of the write current Idata, that is, at a minimum luminance value, the data line 10 allows the current whose value is double of I1 to flow therethrough. Allowing the larger current to flow through the data line 10 in this manner leads to reduction of effects caused by a wiring capacitance and a driver capacitance and to writing by the accurate current Idata corresponding to desired luminance.

A current control driver of a fifth embodiment of the present invention will be described below with reference to FIGS. 27 to 30. The current control driver in this embodiment is also to drive OLEDs (organic EL elements) in an organic EL display device as an example, and the configuration thereof is shown in FIG. 27. In this embodiment, the scanning line ScanC in the first embodiment is omitted, and T5 in each row is set to be in a conductive or non-conductive state by a scanning line ScanB of the immediately preceding row. In the fifth embodiment, how the scanning line ScanB as well as a scanning line ScanA are selected is shown by a timing chart shown in FIG. 28.

Upon writing in a row n−1 in this embodiment, scanning lines ScanA[n−1] and ScanB[n−1] are all selected in a write period time1 as shown by circles in a timing chart in FIG. 28. Transistors T5 and T3 in the row n−1 become conductive as shown in FIG. 27. In the write period time1, a transistor T5 in the immediately following row n is set to become conductive by selection of the scanning line ScanB[n−1].

Therefore, a current Idata in a data line 10 is supplied to T1 in the row n−1 and to T1 in the row n in the write period time1. A voltage occurring in response to the current in the two transistors is retained by a capacitor Cs in the row n−1.

At the time of writing in the row n thereafter, the two scanning lines ScanA[n] and ScanB[n] are all selected in a write period time2 as shown by circles in a timing chart in FIG. 30. In response, transistors T4 and T3 in the row n become conductive as shown in FIG. 29. In the write period time2, a transistor T5 in the immediately following row n+1 is set to become conductive by the scanning line ScanB being selected.

Therefore, a current Idata in the data line 10 is supplied to T1 in the row n and to T1 in the row n+1 in the write period time2, and a voltage occurring in response to the current is retained by a capacitor Cs in the row n.

As has been described above, at the time of writing in a pixel Gn in the row n in this embodiment, the current Idata also flows through T1 in the immediately following row n+1. Therefore, if I1 refers to a current causing emission of light at a minimum value of the write current Idata, that is, at a minimum luminance value, the data line 10 allows the current whose value is double of I1 to flow therethrough. Allowing the larger current to flow through the data line 10 in this manner leads to reduction of effects caused by a wiring capacitance and a driver capacitance and to writing by the accurate current Idata corresponding to desired luminance.

Although the embodiments applied to the display devices using the organic EL elements as light emitting elements have been described above, the present invention can be applied to a display device using other current driving light emitting elements. In addition, the current control drivers of the present invention can be applied not only to such a display device but also to an optical scanning reading apparatus or optical scanning recording apparatus that generates reading light or recording light with constant luminance of a changeable value by sequential scanning of light emitting elements laid out in the form of a matrix, for example. In this case, the effects of the present invention can also be obtained in the same manner.

Claims

1. A current control driver of an active matrix method in a device in which elements that receive current supply are laid out in the form of a matrix, the elements being selected in the current control driver by sequential line scanning while output currents being controlled by applied currents from a plurality of data lines and supplied respectively to the selected elements, the current control driver comprising an element circuit for each of the elements, the element circuit comprising: a converting unit for converting a corresponding one of the applied currents into a voltage;a retaining unit for retaining the voltage converted by the converting unit; anda driving unit for converting the voltage retained by the retaining unit into a corresponding one of the output currents and supplying the output current, whereinthe converting unit is shared between two or more different element circuits, andtwo or more of the converting units are connected to the retaining unit of one of the elements during a current supply period for the element by a switch located between the shared converting units.

2. The current control driver as claimed in claim 1, the current control driver having: the converting unit comprising a field effect transistor whose drain and gate are electrically short-circuited, the field effect transistor generating the voltage between the gate and the source thereof by the applied current from a corresponding one of the data lines;the retaining unit comprising a capacitor that retains the voltage generated between the gate and the source of the field effect transistor; andthe driving unit comprising a field effect transistor that controls the output current based on the voltage retained by the capacitor.

3. The current control driver as claimed in claim 1, the current control driver having: a first scanning switch for selectively conducting the applied current from the data line;the converting unit for converting the current via the first scanning switch into the voltage;a second scanning switch for selectively supplying the voltage converted by the converting unit;the retaining unit for retaining the voltage supplied via the second scanning switch;the driving unit for converting the voltage retained by the retaining unit into the output current and supplying the output current; anda third scanning switch for allowing the converting unit to be shared by the two or more element circuits.

4. The current control driver as claimed in claim 2, the current control driver having: a first scanning switch for selectively conducting the applied current from the data line;the converting unit for converting the current via the first scanning switch into the voltage;a second scanning switch for selectively supplying the voltage converted by the converting unit;the retaining unit for retaining the voltage supplied via the second scanning switch;the driving unit for converting the voltage retained by the retaining unit into the output current and supplying the output current; anda third scanning switch for allowing the converting unit to be shared by the two or more element circuits.

5. The current control driver as claimed in claim 3, the current control driver having: the first scanning switch comprising a first field effect transistor connected to a first scanning line;the converting unit comprising a second field effect transistor whose drain and gate are electrically short-circuited, the second field effect transistor generating the voltage between the gate and the source thereof by the current supplied via the first field effect transistor;the second scanning switch comprising a third field effect transistor whose gate is connected to a second scanning line;the retaining unit comprising the capacitor that retains the voltage generated between the gate and the source of the second field effect transistor and supplied via the third field effect transistor;the driving unit comprising a fourth field effect transistor that is connected serially to a corresponding one of the elements and drives the element based on the voltage retained by the capacitor; andthe third scanning switch comprising a fifth field effect transistor whose gate is connected to a third scanning line.

6. The current control driver as claimed in claim 4, the current control driver having: the first scanning switch comprising a first field effect transistor connected to a first scanning line;the converting unit comprising a second field effect transistor whose drain and gate are electrically short-circuited, the second field effect transistor generating the voltage between the gate and the source thereof by the current supplied via the first field effect transistor;the second scanning switch comprising a third field effect transistor whose gate is connected to a second scanning line;the retaining unit comprising the capacitor that retains the voltage generated between the gate and the source of the second field effect transistor and supplied via the third field effect transistor;the driving unit comprising a fourth field effect transistor that is connected serially to a corresponding one of the elements and drives the element based on the voltage retained by the capacitor; andthe third scanning switch comprising a fifth field effect transistor whose gate is connected to a third scanning line.

7. The current control driver as claimed in claim 1, the current control driver having a configuration such that upon the current supply to each of the selected elements the element circuit thereof shares the converting unit of an immediately preceding one of the element circuits along a scanning direction.

8. The current control driver as claimed in claim 1, the current control driver having a configuration such that upon the current supply to each of the selected elements the element circuit thereof shares the converting unit of an immediately following one of the element circuits along a scanning direction.

9. The current control driver as claimed in claim 1, wherein the transistors comprising the converting unit and the driving unit are N-channel MOS transistors and the transistors comprising the scanning switches are P-channel MOS transistors.

10. A display device having light emitting elements laid out in the form of a matrix in which luminance of the elements changes in accordance with currents applied thereto, the display device comprising a current control driver of an active matrix method in which the elements that receive current supply are selected by sequential line scanning while output currents are controlled by the applied currents from a plurality of data lines and are supplied respectively to the selected elements, the current control driver in the display device comprising a pixel circuit for each of the light emitting elements, the pixel circuit comprising: a converting unit for converting a corresponding one of the applied currents into a voltage;a retaining unit for retaining the voltage converted by the converting unit; anda driving unit for converting the voltage retained by the retaining unit into a corresponding one of the output currents and supplying the output current, whereinthe converting unit is shared between two or more of the pixel circuits that are different from each other, andtwo or more of the converting units are connected to the retaining unit of one of the light emitting elements during a current supply period for the light emitting element by a switch located between the shared converting units.

11. The display device as claimed in claim 10, the display device having: the converting unit comprising a field effect transistor whose drain and gate are electrically short-circuited, the field effect transistor generating the voltage between the gate and the source thereof by the applied current from a corresponding one of the data lines;the retaining unit comprising a capacitor that retains the voltage generated between the gate and the source of the field effect transistor; andthe driving unit comprising a field effect transistor that controls the output current based on the voltage retained by the capacitor.

12. The display device as claimed in claim 10, the display device having: a first scanning switch for selectively conducting the applied current from the data line;the converting unit for converting the current via the first scanning switch into the voltage;a second scanning switch for selectively supplying the voltage converted by the converting unit;the retaining unit for retaining the voltage supplied via the second scanning switch;the driving unit for converting the voltage retained by the retaining unit into the output current and supplying the output current; anda third scanning switch for allowing the converting unit to be shared by the two or more of the pixel circuits.

13. The display device as claimed in claim 11, the display device having: a first scanning switch for selectively conducting the applied current from the data line;the converting unit for converting the current via the first scanning switch into the voltage;a second scanning switch for selectively supplying the voltage converted by the converting unit;the retaining unit for retaining the voltage supplied via the second scanning switch;the driving unit for converting the voltage retained by the retaining unit into the output current and supplying the output current; anda third scanning switch for allowing the converting unit to be shared by the two or more of the pixel circuits.

14. The display device as claimed in claim 12, the display device having: the first scanning switch comprising a first field effect transistor connected to a first scanning line;the converting unit comprising a second field effect transistor whose drain and gate are electrically short-circuited, the second field effect transistor generating the voltage between the gate and the source thereof by the current supplied via the first field effect transistor;the second scanning switch comprising a third field effect transistor whose gate is connected to a second scanning line;the retaining unit comprising the capacitor that retains the voltage generated between the gate and the source of the second field effect transistor and supplied via the third field effect transistor;the driving unit comprising a fourth field effect transistor that is connected serially to a corresponding one of the light emitting elements and drives the light emitting element based on the voltage retained by the capacitor; andthe third scanning switch comprising a fifth field effect transistor whose gate is connected to a third scanning line.

15. The display device as claimed in claim 13, the display device having: the first scanning switch comprising a first field effect transistor connected to a first scanning line;the converting unit comprising a second field effect transistor whose drain and gate are electrically short-circuited, the second field effect transistor generating the voltage between the gate and the source thereof by the current supplied via the first field effect transistor;the second scanning switch comprising a third field effect transistor whose gate is connected to a second scanning line;the retaining unit comprising the capacitor that retains the voltage generated between the gate and the source of the second field effect transistor and supplied via the third field effect transistor;the driving unit comprising a fourth field effect transistor that is connected serially to a corresponding one of the light emitting elements and drives the light emitting element based on the voltage retained by the capacitor; andthe third scanning switch comprising a fifth field effect transistor whose gate is connected to a third scanning line.

16. The display device as claimed in claim 10, the display device having a configuration such that upon the current supply to each of the selected light emitting elements the pixel circuit thereof shares the converting unit of an immediately preceding one of the pixel circuits along a scanning direction.

17. The display device as claimed in claim 10, the display device having a configuration such that upon the current supply to each of the selected light emitting elements the pixel circuit thereof shares the converting unit of an immediately following one of the pixel circuits along a scanning direction.

18. The display device as claimed in claim 10, wherein the transistors comprising the converting unit and the driving unit are N-channel MOS transistors and the transistors comprising the scanning switches are P-channel MOS transistors.