CURRENT CONTROL OF MOTOR DRIVES WITH OUTPUT SINEWAVE FILTER

Information

  • Patent Application
  • 20180138849
  • Publication Number
    20180138849
  • Date Filed
    November 15, 2016
    8 years ago
  • Date Published
    May 17, 2018
    6 years ago
Abstract
Disclosed examples include power conversion systems, methods and computer readable mediums to operate an inverter to drive a motor load through an output filter, in which a control output value is computed according to a current reference value and a current feedback value using a proportional-integral (PI) current regulator, the control output value is filtered using a lag compensator filter to compute an inverter output command value, and the inverter is controlled according to the inverter output command value.
Description
BACKGROUND INFORMATION

The subject matter disclosed herein relates to power conversion, and more specifically to controlling a power converter.


BRIEF DESCRIPTION

Various aspects of the present disclosure are now summarized to facilitate a basic understanding of the disclosure, wherein this summary is not an extensive overview of the disclosure, and is intended neither to identify certain elements of the disclosure, nor to delineate the scope thereof. Rather, the primary purpose of this summary is to present various concepts of the disclosure in a simplified form prior to the more detailed description that is presented hereinafter. The present disclosure provides power conversion systems, methods and computer readable mediums to operate an inverter to drive a motor load through an output filter, in which a control output value is computed according to a current reference value and a current feedback value using a proportional-integral (PI) current regulator, the control output value is filtered using a lag compensator filter to compute an inverter output command value, and the inverter is controlled according to the inverter output command value.





BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1 is a schematic diagram of a motor drive power conversion system with an inverter driving a motor load through an output filter and a transformer.



FIG. 2 is a schematic diagram of motor control and motor speed estimation components of the motor controller in FIG. 1.



FIG. 3 is a flow diagram illustrating a method to control an inverter to drive a motor load through an intervening filter in the apparatus of FIGS. 1 and 2.



FIG. 4 is a schematic diagram of an example motor drive power conversion system showing details of an example inverter controller with a current PI regulator and filters.



FIG. 5 is a schematic diagram of a system equivalent electrical circuit corresponding to the motor drive power conversion system of FIG. 4.



FIG. 6 is a schematic diagram of the closed loop current control loop in the system of FIGS. 4 and 5.



FIG. 7 is a graph showing a magnitude log-log Bode plot of the transfer function of the system of FIG. 6 for an inverter operating fundamental frequency of zero.



FIG. 8 is a graph showing a magnitude log-log Bode plot for a non-zero inverter operating fundamental frequency.



FIG. 9 is a graph showing a magnitude log-log Bode plot curves for the system object of FIG. 6 and the current control open loop with ordinary PI regulator.



FIG. 10 is a graph showing a magnitude log-log Bode plot curves for the system object of FIG. 6 and the current control open loop with PI controller of FIG. 4 including a single lag filter.



FIG. 11 is a graph showing a magnitude log-log Bode plot curves for the system object of FIG. 6 and the current control open loop with PI controller of FIG. 4 including two lag filters.





DETAILED DESCRIPTION

Referring now to the figures, several embodiments or implementations are hereinafter described in conjunction with the drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the various features are not necessarily drawn to scale. FIG. 1 shows an example motor drive power conversion system 40 with an inverter 46 to drive an output load, such as a motor 20 through an intervening filter 30, referred to herein as an output filter or a sine wave filter. In certain implementations, as shown in FIG. 1, a transformer 50 can be connected between the output filter 30 and the driven motor load 20. Power conversion systems typically include an inverter stage to generate and provide AC output power to a load, such as a single or multi-phase AC motor. Pulse width modulated (PWM) output inverters provide output currents and voltages that include a number of pulses. Accordingly, output filters, such as sine wave filters with inductors and capacitors are sometimes employed between the inverter output and the driven load to reduce the high frequency content caused by pulse width modulation of the inverter switches. To control stability, output filters can be equipped with damping resistors in series with the filter capacitors. However, filter damping resistors contribute to power loss in the system. Without on-board damping resistors, operation at or near a resonance frequency of a low damping output filter can lead to large oscillations and instability problems. Deep well pumping applications and other systems that have a motor driven through an output filter, a transformer and a potentially long motor cable often use voltage control as a function of frequency (V/Hz drives) which do not regulate currents and do not use position estimation for control. V/Hz drives typically suffer from higher drive and motor losses.


The disclosed techniques and apparatus facilitate current control using a current proportional-integral (PI) regulator with a lag compensator to filter the control output from the PI regulator and/or to filter a current feedback signal consumed by the PI regulator to operate an inverter of a motor drives with an output sine wave filter, a transformer, long cable, and motor. PI regulator together with one or multiple lag compensators further call PI controller. One or multiple first order lag compensator(s) can be designed based upon characteristics of the sine wave filter. In certain implementations, the filtering is implemented by one or more processors of a drive controller, and the lag compensation is tuned according to various parameters of the system, such as a current control loop resonance frequency of a current control loop, an inverter operating fundamental frequency, a peak resonance frequency of the output filter, a PI regulator corner frequency of the PI current regulator, a desired amplitude margin below unity at the resonance frequency of the current control loop, a desired current control loop crossover frequency of the current control loop, and a plant corner frequency. Certain embodiments can be successfully employed to facilitate accurate stable control of voltages and currents provided to the load in the presence of the output filter between the power conversion system and the load where the power delivered to the load is different from that delivered to the input of the filter. The output inverter stage of the motor drive in certain examples can be controlled according to feedback signals measured at the inverter output terminals, but these feedback values generally do not represent the currents or voltages ultimately provided to the load. Feedback sensors can be provided at the load itself for direct measurement of the load parameters, but this increases system cost, and may not be possible in all applications. The disclosed examples can be used, for example, in sensorless position control applications, such as deep well pump motor control where direct sensing of the motor load position and/or speed is difficult or impractical. In certain applications, a step-up transformer is used to boost the motor drive output voltage, allowing use of a low-voltage drive to power a medium voltage induction motor, and/or to reduce I2R losses and facilitate use of a smaller diameter cable wire for long cable runs between the motor drive and the driven motor. Certain applications also employ output filters between the motor drive inverter output and the transformer primary in order to suppress reflected wave voltage spikes associated with pulse width modulated (PWM) variable frequency drives. Use of sensorless voltage-frequency control techniques may lead to problems, particularly where a transformer and/or sine wave filter is connected between the motor drive and the motor load. Sensorless field-oriented-control (FOC) or other open loop speed control techniques have thus far been largely unsuitable for low-speed motor drive operation where output filters and transformers are used, such as in electric submersible pumps (ESPs), and these difficulties are particularly problematic in driving permanent magnet synchronous motors (PMSMs). Moreover, motors in sensorless speed control applications also suffer from oscillation in rotor velocity about the setpoint speed following load transitions or speed setpoint adjustments, particularly at low speeds. In certain situations, moreover, the driven motor may be unable to start successfully from a stopped condition due to unstable motor speed oscillations. Furthermore, operation at high speeds is sometimes prevented or inhibited by the resonant frequency of the connected output filter. In this regard, conventional motor drives and control techniques often suffer from instability problems at high motor speeds.


As seen in FIG. 1, disclosed examples include power conversion systems 40, inverter control methods and controllers or control apparatus 100 to drive a motor load 20 through an intervening filter 30, which can also be used in combination with a transformer 50 and a potentially lengthy cables 60 coupled between the filter output and the driven motor load 20. FIG. 1 shows a motor drive power conversion system 40 with an inverter 46 and an inverter controller 100 configured to control current of a driven motor load 20 based on sensed or computed inverter output current signals or values iu, iv, iw representing output currents flowing at an AC output 46B of the inverter 46. The controller 100, moreover, is configured to compensate for the presence of an output filter 30 connected between the motor drive output 46B and the driven motor 20 using a current controller 101. In particular, the inverter controller 100 in one example includes a processor 102 and an associated electronic memory 104 which stores program instructions to implement a current controller 101 including one or more proportional-integral (PI) regulators or PI control components 106, and one or more filters 108.


The motor drive 40 receives single or multiphase AC input power from a power source 10 and converts this to a DC bus voltage using a rectifier 42 which provides a DC output voltage to a DC link circuit 44 having a capacitor C. The rectifier 42 can be a passive rectifier including one or more diode rectifier components, or may be an active front end (AFE) system with one or more rectifier switching devices (e.g., IGBTs, etc.) and an associated rectifier controller (not shown) for converting input AC electrical power to provide the DC bus voltage in the link circuit 44. Other configurations are possible in which the drive 40 receives input DC power from an external source (not shown) to provide an input to the inverter 46, in which case the rectifier 42 may be omitted. The DC link circuit 44 may include a single capacitor C or multiple capacitors connected in any suitable series, parallel and/or series/parallel configuration to provide a DC link capacitance across inverter input terminals 46A. The illustrated motor drive 40 is a voltage source converter configuration including one or more capacitive storage elements in the DC link circuit 44. The various concepts of the present disclosure may be implemented in association with current source converter architectures in which a DC link circuit 44 includes one or more inductive storage elements, such as one or more series-connected inductors situated between the source of DC power (e.g., rectifier 42 or external DC source) and the input 46A of the inverter 46. In other possible implementations, the motor drive 40 includes a direct DC input to receive input power from an external source (not shown), and in certain embodiments the rectifier 42 and DC link circuit 44 may both be omitted.


The DC input 46A of the inverter 46 includes first and second (e.g., plus and minus) terminals connected to the DC link circuit 44, as well as a plurality of switching devices S1-S6 coupled between the DC input 46A and the motor drive AC output 46B. In operation, the inverter switching devices S1-S6 are actuated by inverter switching control signals 101 provided by the controller 100 to convert DC electrical power received at the DC input 46A to provide AC electrical output power as inverter output voltages, Vu, Vv, and Vw and inverter output currents iu, iv, and iw at the AC output 46B. The filter circuit 30 receives the AC output from the inverter 46 of the motor drive 40. Although illustrated as driving a permanent magnet synchronous motor 20, the motor drive 40 can be employed in connection with other types of AC motor loads 20 and/or other forms of power converters to drive non-motor loads 20 using an output inverter 46. One or more feedback signals or values may be provided from the motor 20 itself, including a motor (e.g., rotor) position or angle signal θr and a motor speed or velocity signal ωr, although not a strict requirement of all embodiments of the present disclosure. The concepts of the present disclosure advantageously facilitate the sensorless speed estimation by the inverter controller 100, and thus direct feedback from the driven motor load 20 is not required in all implementations. The motor drive 40 in certain embodiments implements a motor speed and/or position and/or torque control scheme in which the inverter controller 100 selectively provides the switching control signals 101 in a closed and/or open-loop fashion according to one or more setpoint values such as a motor speed setpoint. The setpoint in one example is a signal or value generated by the controller 100, or a fixed setpoint value, or such setpoint value can be received from an external system (not shown). In practice, the motor drive 40 may also receive a torque setpoint and/or a position (e.g., angle) setpoint, and such desired signals or values (setpoint(s)) may be received from a user interface and/or from an external device such as a distributed control system, etc. (not shown). As used herein, a signal can be an analog signal, such as a current or a voltage signal, or a signal can include digital values generated or consumed by the processor 102.


The inverter 46 of the motor drive 40 is connected to the load 20 through the intervening filter circuit 30. In the example of FIG. 1, the filter 30 is an “L-C” configuration in which each of the power converter output lines is connected to the motor through a series-connected filter inductor Lr (Lr,u, Lr.v and Lr.w in the illustrated example). This example includes a corresponding filter capacitor C1 connected between the corresponding motor line and a common connection point (a neutral of a Y-connected set of filter capacitors C1.u, C1.v and C1.w in the illustrated example). Other implementations are possible, in which the filter capacitors C1 are connected in a “Delta” configuration. In the illustrated (Y-connected) configuration, the filter circuit neutral point can be optionally connected to a circuit ground or other, connection point associated with the motor drive 40, although not a strict requirement of the present disclosure. The disclosed apparatus and techniques can be employed in connection with other forms and types of filter circuits 30, including without limitation L-C-L circuits, etc.


The output of the filter circuit 30 provides motor phase currents iout to control the motor load 20. The filter capacitor currents iC flow in the filter capacitors C1 and non-zero voltages vL (i.e., filter voltages) may develop across one or more of the filter inductors Lr, whereby simple closed-loop control based on measured inverter output current signals or values iu, iv, iw may result in less than optimal operation of the driven load 20. At the same time, however, directly measuring the motor currents iout and/or motor voltages would require additional hardware and cabling, which may not be economically feasible or technically possible in certain applications. Nevertheless, for those cases where motor currents and/or motor voltages, such as Vu, Vv, Vw, Vf_out_v, and Vf_out_w in FIG. 1, are measured, those signals can be used to enhance or replace the inverter current and/or voltage signals in the computation of the compensation signals. Certain embodiments of the inverter controller 100, however, advantageously provide steady-state compensation with respect to capacitor current based on the plant transfer function or functions 110, 112, 114 independent of the voltage feedback information. As seen in FIG. 1, moreover, the illustrated drive 40 may also include one or more current sensors configured to measure, sense, or otherwise detect at least one inverter output feedback signal or value (e.g., output currents iu, iv, iw) which represent the output current at the AC output 46B of the inverter 46. The inverter controller 100 thus accommodates the presence of the filter circuit 30 (e.g., and any optionally included transformer 50 and potentially lengthy motor cable 60) between the motor drive output 46B and the driven motor load 20, without requiring addition of external sensors to sense the actual conditions at the motor load 20.


The controller 100 and the components thereof may be any suitable hardware, processor-executed software, processor-executed firmware, logic, or combinations thereof that are adapted, programmed, or otherwise configured to implement the functions illustrated and described herein. The controller 100 in certain embodiments may be implemented, in whole or in part, as software components executed using one or more processing elements, such as one or more processors 102. The controller 100 may be implemented as a set of sub-components or objects including computer executable instructions stored in the electronic memory 104 for operation using computer readable data executing on one or more hardware platforms such as one or more computers including one or more processors, data stores, memory, etc. The components of the controller 100 may be executed o the n the same computer processor or in distributed fashion in two or more processing components that are operatively coupled with one another to provide the functionality and operation described herein.


Referring also to FIGS. 2-4, FIG. 2 illustrates filter transfer functions, motor control and motor speed estimation components of the motor controller 100 in the motor drive 40 of FIG. 1. Disclosed examples include power conversion systems, methods and computer readable mediums to operate an inverter 46 to drive a motor load 20 through an output filter 30, in which a control output value COd,q is computed according to a current reference value Id,q.ref and a current feedback value Id,qfbk using a proportional-integral PI current regulator 106. The control output value COd,q is filtered using a lag compensator filter 108 to compute an inverter output command value Vd,q.com, and the inverter 46 is controlled according to the inverter output command value Vd,q.com. FIG. 3 illustrates a process or method 300 of operating the motor drive inverter 46 to drive a motor load 20 through an intervening filter 30, which can be implemented in the motor controller 100. The controller 100 implements a closed loop control algorithm including one or more proportional-integral (PI) control components or regulators 106 and filter component(s) 108 of a current controller 101 in order to control the driven load 20. The controller 100 in certain embodiments is configured by execution in the processor 102 of instructions in the memory 104 to implement the control configuration illustrated in FIG. 2, as described hereinafter in conjunction with the process 300 of FIG. 3.


The controller 100 is configured to implement the method 300, wherein the processor 102 of FIG. 1 computes a speed error value 201 at 302 according to a speed reference value Speed.ref and a speed feedback value Speed.fbk, and at 304 computes a torque reference value Torque.ref according to the speed error value 201. At 302 in one possible implementation, the controller 100 computes 302 a speed error value 201 according to a speed reference value Speed.ref and a speed feedback value Speed.fbk, for example, by subtracting the feedback value from the reference value. The feedback value can be obtained from any suitable source, including actual speed sensors (not shown) or from a speed observer 210 as shown in FIG. 2. As seen in FIG. 2, the controller 100 implements a speed proportional-integral (PI) control component 200 which receives the resulting speed error signal 201 and operates according to known proportional-integral control operation to compute a torque reference value Torque.ref according to the speed error value 201 at 304 in FIG. 3.


At 306, the processor 102 computes a current reference value Id,q.ref according to the torque reference value Torque.ref. At 306, the controller 100 uses one or more lookup tables 202 or solves one or more parametric equations (not shown) to compute one or more motor current reference values. In the example of FIG. 2, the controller 100 computes d and q axis motor current reference values Id.motor.ref and Iq.motor.ref according to the torque reference value Torque.ref, where this computation in certain examples includes indexing a lookup table 202. In this example, moreover, the controller 100 scales the d and q axis motor current reference values Id.motor.ref and Iq.motor.ref according to a turns ratio 203 of any included output transformer 50 via multiplier components 204 and 206, respectively. Other implementations are possible that do not involve speed and/or torque control, in which case the computations at 302, 304 and 306 can be omitted.


At 308, the control processor 102 computes a control output value COd,q according to a current reference value Id,q.ref and a current feedback value Id,qfbk using a proportional-integral PI current regulator 106 implemented by the controller 100. At 309 the processor 102 filters the control output value COd,q to compute an inverter output command value Vd,q.com using the lag compensator filter 108 implemented by the controller 100. In certain examples, the PI regulator(s) 106 and the lag compensator filter(s) are implemented as programmable instructions stored in the memory 104 to be executed by the processor 102.


At 310 in FIG. 3, the processor 102 provides the inverter switching control signals 101 to control 310 the inverter 46 according to the inverter output command value Vd,q.com to control the inverter 46 according to the inverter output current reference value(s) Id,q.inverter.ref. The controller 100 computes or estimates the speed feedback value Speed.fbk according to any suitable measured or inferred value, such as inverter currents and voltages in one example. In another example, the controller uses sensor information for the speed feedback. Moreover, the controller 100 in certain embodiments implements sensorless speed control according to the estimated speed feedback value Speed.fbk without requiring speed feedback. For instance, the controller 100 can implement sensorless speed and/or position control including computing a speed feedback value at 320 in FIG. 3 according to the motor torque, and the process 300 repeats at 302 as described above.


As shown in FIG. 4, in certain examples the current controller 101 includes one or more of current PI regulators 106 followed by one or more filters 108. The filters 108 include one or more first order lag compensators as described further below to filter the control output provided by the current PI regulator(s) 106 in order to provide one or more voltage command values for use in operating the inverter 60. In other examples, as shown in dashed line in FIG. 4, the filter or filters 108a, including one or more first-order lag filters, can be implemented in a current feedback loop to filter a current feedback value or values in order to provide a filtered current feedback value or values to the PI regulator(s) 106. In certain embodiments, the controller 100 implements voltage control. In the example of FIG. 2, the controller 100 controls the inverter 46 according to the inverter output current reference value id,q.inverter.ref. In one example, the controller 100 computes an inverter output voltage control value Vin.d,q, for example, d and q values Vin.d and Vin.q computed using voltage control PI components 212 and 214, respectively, according to the inverter output current reference value(s) Id,q.inverter.ref and an inverter output current value(s) Id,q.in. In certain examples, the inverter output current value or values Id,q.in (e.g., Id.in and Iq.in) can be obtained from feedback sensors (e.g., as shown in FIG. 1 above), or these can be computed by the controller 100. The controller 100 provides the inverter switching control signals 101 at 310 in this example to control the inverter 46 according to the inverter output voltage control value(s) Vin.d,q.


In other possible implementations, the controller 100 operates to control the inverter 46 according to the inverter output current reference value(s) Id,q.inverter.ref. In this case, the controller 100 computes the inverter output current value(s) Id,q.in according to the inverter output current reference value Id,q.inverter.ref and the inverter output current value Id,q.in, and provides the inverter switching control signals 101 to control the inverter 46 (e.g., at 310 in FIG. 3) according to the inverter output current value Id,q.in. In this example, the PI controllers 212 and 214 provide the computed inverter output current value(s) Id,q.in


The lag compensator filter 108 in certain examples includes one or more lag compensators designed according to a current control loop resonance frequency ωd,q.res of a current control loop, an inverter operating fundamental frequency ωfund, a peak resonance frequency ωpk of the output filter 30, a PI regulator corner frequency ωld of the PI current regulator 106, a desired amplitude margin 1010, 1110 below unity at the resonance frequency ωd,q.res of the current control loop, a desired current control loop crossover frequency ωco of the current control loop, and a plant corner frequency ωΣ. Moreover, the drive 40 and the controller 100 are programmable to adapt to different filter and/or driven motor combinations.


Referring now to FIGS. 4-11, non-limiting example lag compensation concepts are described hereinafter, which can be employed as the post-PI regulator filters 108 in FIGS. 1-4 and/or as alternative feedback filters 108a as shown in FIG. 4. FIG. 4 shows the general system block diagram with a sinewave filter 30, a transformer 50, a potentially lengthy cable 60 and a motor 20, which can be used in deep well oil pump applications, for example.



FIG. 5 shows a system equivalent electrical circuit including fundamental inverter output voltages 502, a power circuit of a simple LC sinewave filter 504, and an equivalent power circuit of a three-phase transformer, cable and motor referred to the primary side of the transformer shown at 506. In this system, a system resistance Rsys.k is given as Rsys.k=Rtr.prime.k+Rcbl.prime.k+Rmot.prime.k. A summation resistance RΣ.k is given as RΣ.k=Rsys.k+Rr.k. In addition, system and summation inductances are given as Lsys.k=Lir.prime.k+Lcbl.prime.k+Lmot.prime.k; and LΣ.k=Lsys.k+Lr.k where k=1, 2, 3.


The following presents an analysis of a current control loop implemented in the controller 100 for operation of the inverter 46 in combination with an output sinewave filter 30. The output filter 30, as previously mentioned, does not include any damping resistors, and thus has a low damping factor and relatively low resonance frequency ωpk (e.g., the resonance frequency ωpk is not far from required current loop frequency crossover).



FIG. 6 illustrates a general closed loop with the current PI regulator 106 providing a command signal to a filter object 601 with an inverter object 602, a summation resistance component 604, and a normalized object 608 including a first order filter component 610 and a second order filter component 612. The use of a low damping second order unit in the object 612 allows the object transfer function to be represented as follows (see also FIGS. 4, 5):











H
object



(
p
)


=




i

m
·
fbk




(
p
)




V
inv



(
p
)



=


1

R



·

1

1
+


1

ω



·
p



·

1

1
+

2

ξ






T
pk


p

+


T
pk
2



p
2










(
1
)







where “ωΣ” is a plant corner frequency given according to the following formulas, where Tpk is the time constant of the output filter 30, C is the filter capacitance, Lr is the inductance of the filter inductors, and Rr is the resistance of the filter inductors:










ω


=


R



L
sys






(
2
)







2

ξ






T
pk


=

CR
r





(
3
)







T
pk
2

=

CL
r





(
4
)







From equations 3 and 4, the following equations can be derived for the time constant Tpk and a damping factor ξ:










T
pk

=


1

ω
pk


=


CL
r







(
5
)






ξ
=



R
r

2

·


C

L
r








(
6
)







where “ξ” and “ωpk” are filter damping factor and filter resonance frequency, respectively. A typical range of the damping factor “ξ” for a standard sinewave filter is 0.01-0.0005, and a typical range of a resonance frequency “ωpk” for a standard filter is 800-1,100 Hz. The amplitude of the resonance peak “Apk” at the point of the resonance frequency “ωpk” can be calculated as follows:











A
pk



(

ω
pk

)


=

1

2
·
ξ






(
7
)







ω
pk

=

1

T
pk






(
8
)







According to the damping factor range, the amplitude of the resonance peak “Apk” is given in one example by the following:










A
pk

=


1

2
·
ξ


=


1

2


(

0.01
-
0.0005

)



=

50
-
1000







(
9
)







Or in a decibel units:





20·log(Apk)=20·log(50-500)=(34−60) db   (10)



FIGS. 6 and 7 show typical Bode log-log amplitude plots for the object. The control algorithm in one example of FIG. 4 works with “d, q” variables, and the controller 100 implements corresponding coordinate transformation blocks shown in FIG. 4. Generally, these blocks make a variables transformation from “a, b, c” or “u, v, w” to “α, β” and then from “α, β” to “d, q”. The resonance frequency “ωpk” of the sinewave filter 30 is shown inside the rotational frames “a, b, c”, “u, v, w”, or “α, β”, but any Bode plot is created inside a synchronous frame “d, q”. Therefore resonance frequency of sinewave filter “ωpk” is equal to the value of equations 5, 8 above. The “d, q” resonance frequency ωd,q.res inside the Bode plot will move according to the fundamental frequency ωfund (i.e., the electrical operating frequency of the inverter 46) since the synchronous frame is rotating with the fundamental frequency. Therefore, the “d, q” resonance frequency ωd,q.res can be calculated as follows:





ωd,q.respk−ωfund   (11)



FIG. 7 is a graph 700 showing a log-log Bode plot curve 702 of the magnitude log-log transfer function of the system of FIG. 6 for the object transfer function of an inverter operating fundamental frequency of zero. FIG. 8 provides a graph showing a log-log Bode plot curve 802 for a non-zero inverter operating fundamental frequency for the object transfer function, as well as a curve 804 showing the magnitude log-log transfer function performance of the second order part of output filter 30. FIG. 9 provides a graph 900 showing a magnitude log-log Bode plot curves 902 for the system object of FIG. 6 and the entire current control loop with PI 904. FIG. 10 includes a graph 1000 showing magnitude log-log Bode plot curve 1002 for the system object of FIG. 6 and a curve 1004 the entire current control loop with PI of FIG. 4 including a single lag filter. FIG. 11 shows a graph 110 including a magnitude log-log Bode plot curve 1102 for the system object of FIG. 6 and a magnitude log-log curve 1104 for the entire current control loop with PI of FIG. 4 including two lag filters.


As seen in FIG. 7, the PI regulator 106 implements a regulation function according to a proportional constant Kp and an integral constant Ki, and has the following transfer function:










H

PI
·
ordinary


=



R


·


1
+

T
ld




T
int


p



=


R


·

[



K

i
·
norm



p

+

K

p
·
norm



]







(
12
)







K

i
·
norm


=


1

T
int


=

ω
int






(
13
)







K

p
·
norm


=



T
ld


T
int


=


ω
int


ω
ld







(
14
)







Stabilizing the current control loop using an ordinary PI regulator is difficult with appropriate current loop frequency crossover at the crossover frequency ωco of the current control loop, due to very large resonance peak of the output filter 30. In one possible embodiment, the controller 100 uses PI regulators 106 in combination with one, two or more lag compensator units, either following the PI regulators 106 in a current control or 101, or using an alternate filter position in the current feedback loop 108k as shown in FIG. 4. In the first embodiment, with the lag compensator filter or filters 108 following the PI regulator 106, the PI controller transfer function with one lag or two lag units and can be represented as follows:










H


PI
·
1







lag
·
unit



=




1
+

T
ld




T
int


p


·

1

1
+


T

lag





1



p




=


[



K

i
·
norm



p

+

K

p
·
norm



]

·


ω

lag





1




ω

lag





1


+
p








(
15
)







H


PI
·
2



lag
·
units



=




1
+

T
ld




T
int


p


·

1

1
+


T

lag





1



p



·

1

1
+


T

lag





2



p




=


[



K

i
·
norm



p

+

K

p
·
norm



]

·


ω

lag





1




ω

lag





1


+
p


·


ω

lag





2




ω

lag





2


+
p








(
16
)







The graph 700 in FIG. 7 shows a Bode magnitude log-log plot of the typical object (plant) for fundamental frequency (e.g., inverter operating frequency) equal to zero. The graph 800 in FIG. 8 shows a Bode magnitude log-log plot of the typical object (plant) for some fundamental frequency not equal to zero. The graph 900 in FIG. 9 shows a Bode magnitude log-log plot of current loop together with ordinary PI controller with some fundamental frequency. Below is an analysis of the system with the PI regulator 106 in combination with one or two first-order lag units to express the relationship between PI controller parameters and system parameters. Example embodiments provide appropriate stability margin with respect to the amplitude margin at or near the control loop resonance frequency ωd,q.res as well as appropriate phase margin at the current control loop crossover frequency ωco.


In one example, the lag compensator filter 108 includes a first lag compensator filter having a first lag filter corner frequency ωlag 1 between the current loop crossover frequency ωco and the current control loop resonance frequency ωd,q.res. In other examples, as discussed further with reference to FIG. 11 below, the lag compensator filter 108 includes a second lag compensator filter having a second lag filter corner frequency ωlag 2 between the first lag filter corner frequency ωlag 1 and the current control loop resonance frequency ωd,q.res. The first and/or second lag compensators are designed to provide a non-zero amplitude margin 1010, 1110 in FIGS. 10 and 11) below unity at the resonance frequency ωd,q.res. In certain embodiments, the lag compensators are designed to provide a non-zero phase margin at the current control loop crossover frequency ωco of the current control loop.



FIG. 10 illustrates a single lag compensator example to implement the following transfer function:










H


PI
·
1







lag
·
unit



=



R


·


1
+

p






T
ld




p






T
int



·

1

1
+

p






T
lag





=



R


·

[



K

i
·
norm



p

+

K

p
·
norm



]

·


ω
lag



ω
lag

+
p



=


[



K
i


p

+

K
p


]

·


ω

lag








ω
lag

+
p









(
17
)







where the integral and proportional constants are given by the following per equations 13 and 14:










K
i

=



R


·

K

i
·
norm



=



R


·

1

T
int



=


R


·

ω
int








(
18
)







K
p

=



R


·

K

p
·
norm



=



R


·


T
ld


T
int



=


R


·


ω
int


ω
ld









(
19
)








FIG. 10 represents the Bode magnitude log-log plot for the above current loop with the current controller 101 that includes a first or single lag compensator unit and the fundamental frequency ωfund is equal to a maximum value. As seen in FIG. 10 it is desired to add an additional parameter that can be called amplitude “margin” 1010. Typically, this margin 1010 should be not less than 1.5 (3.5 db) (arbitrary number) or more due to a filter resistor variation (see equations 6, 7, and 9). In certain examples, the relationship between the filter resonance frequency “ωpk”, the current loop frequency crossover “ωco” and the rest of PI controller's parameters are designed according to the condition is shown in FIG. 10 (a single lag compensator unit approach).


For the triangle “FGM” in FIG. 10, the following holds:










20






log


(
MG
)



=


20






log


(
FM
)



=



20






log


(

ω
lag

)



-

20






log


(

ω

co
·
1


)




=

20






log


(


ω
lag


ω

co
·
1



)









(
20
)







Or:









MG
=



ω
lag


ω

co

.1



.





(

20

a

)







For the triangle “DGM”, the following holds:










20






log


(
MG
)



=


40






log


(
DM
)



=



40






log


(

ω
lag

)



-

40






log


(

ω
D

)




=

20






log


(


ω
lag
2


ω
D
2


)









(
21
)







Or:









MG
=


ω
lag
2


ω
D
2






(
22
)







From equations 20a and 22, the following can be derived:













ω
lag


ω

co
·
1



=


ω
lag
2


ω
D
2



,





or


:











ω
D

=



ω

co
·
1


·

ω
lag




,





(
23
)







where “ωco.1” is a current loop frequency crossover for the single lag unit approach.


For the triangle “DKN”, using equation 16, the following holds:










20






log


(
NK
)



=



40






log


(


ω
pk

-

ω
fund


)



-

40


log


(

ω
D

)




=



40






log


(


ω
pk

-

ω
fund


)



-

40






log


(



ω

co
·
1


·

ω
lag



)




=

20







log


(



(


ω
pk

-

ω
fund


)

2



ω

co
·
1


·

ω
lag



)


.








(
24
)







where “ωfund” is the fundamental frequency (maximum fundamental frequency determined by a specific application. The lag compensator filter 108 in one example includes a first lag compensator filter having a first lag filter corner frequency (ωlag 1) between the current loop frequency crossover (ωco) and the current control loop resonance frequency (ωd,q.res):





ωlag.1=α·ωco.1   (25)


A minimum value for the coefficient “α” can be selected based on an appropriate additional phase shift that “lag unit” brings into an overall phase shift at the current loop frequency crossover point. In certain examples, the first lag compensator (and any included second lag compensator) is designed to provide a non-zero phase margin (1010, 1110 in FIGS. 10 and 11) at the current control loop crossover frequency (ωco) of the current control loop. For example, this additional phase shift should not be more than 25 degrees (arbitrary number). Therefore “αmin” can be calculated as follows:











25
0

>

a






tan


[


ω

co
·
1



ω

lag
·
min



]




=

a






tan


[

1

a
min


]







(
26
)







Or, from (26):





αmin=2.144   (26a)


In a future calculation we will use round “amin“” as follows:





αmin=2   (27),


Then:










atan


[

1
2

]


=

26.56
0





(

27

a

)







Digital implementation brings a limit for maximum value of this coefficient. Practically, good performance for a first order filter can be achieved if the maximum corner frequency (ωlag.max) is no larger than 10% from firmware scan frequency (ωscan) (where 10% is practical arbitrary number). Usually the firmware scan frequency (ωscan) can be determined as follows:





ωscan=2·(2·π·fcarrier)   (28)


And therefore:










ω


lag
.
ma






x


=



4
·
π
·

f
carrier


10

=


π
·

f
carrier


2.5






(

28

a

)







Therefore for “αmax” the following can be written:










a

ma





x


=



ω


lag
.
ma






x



ω


co


.1
.
real









=


π
·

f
carrier



2.5
·

ω

co


.1
.
real










(
29
)







Finally:





αmin<α<αmax   (30


Or:









2
<
a
<


π
·

f
carrier



2.5
·

ω

co

.1








(
31
)







From (24) and (25) we can derive:









NK
=




(


ω

p





k


-

ω
fund


)

2



ω

co

.1


·

ω
lag



=



(


ω

p





k


-

ω
fund


)


2







a
·

ω


co

.1






2








(
32
)







In addition, (see FIG. 10):











20


log


(
NK
)



=



20


log


(

1

2
·
ξ


)



+

20


log


(
margin
)




=

20


log


(

margin

2
·
ξ


)










and






NK
=

margin

2
·
ξ







(
33
)







where the stability margin limit can be determine as follows (3.5 db is a practical arbitrary number):





3.5 db≤20 log(margin). Or: 1.5≤margin and marginmin=1.5    (34)


Appropriate values can be calculated for current loop frequency crossover using equations 32 and 33:










ω
co

=


(


ω

p





k


-

ω
fund


)

·



2
·
ξ


a
·
margin








(
35
)







Or, with the help of equations 27 and 34:










ω


co
.
ma






x


=



(


ω

p





k


-

ω


fund
.
ma






x



)

·



2
·
ξ



a

m





i





n


·

margin

m





i





n






=



(


ω

p





k


-

ω


fund
.
ma






x



)

·



ξ
1.5








=



(


ω

p





k


-

ω


fund
.




m






ax



)

1.2247

·

ξ








(
36
)







According to equation 36, a current loop frequency crossover can be selected as follows:











ω
Σ



ω

co


.1
.
real







(


ω

p





k


-

ω


fund
.
ma






x



)

1.2247

·

ξ



,




(
37
)







Where “ωΣ” is the plant corner frequency (see equation 2).


According to (27, and 29) the following can be written:










2
·

ω

co


.1
.
real






ω

lag
.
real





π
·

f
carrier



2.5
·

ω

co

.1








(
38
)







And real margin can be calculated from (25, 32 and 33) as follows:










margin
real

=



2
·
ξ
·


(


ω

p





k


-

ω

fund
.
real



)

2




a
real

·

ω

co


.1
.
real


2



=


2
·
ξ
·


(


ω

p





k


-

ω

fund
.
real



)

2




ω

co


.1
.
real



·

ω

lag
.
real









(
39
)







Now we need to determine appropriate “Ki,Kp” values.


From triangle “ZYF” the following can be written:










20


log


(
ZY
)



=


20


log


(
ZF
)



=



20


log


(

ω

co

.1


)



-

20


log


(

ω
ld

)




=

20


log


(


ω

co

.1



ω
ld


)









(
40
)







Or:









ZY
=


ω

co

.1



ω
ld






(
41
)







From triangle “ZYE” the following can be written:










20


log


(
ZY
)



=


40


log


(
ZE
)



=



40


log


(

ω
E

)



-

40


log


(

ω
ld

)




=


40


log


(


ω
E


ω
ld


)



=

20


log


(


ω
E
2


ω
ld
2


)










(
42
)







Or:









ZY
=


ω
E
2


ω
ld
2






(
43
)







From (41) and (43):





ωE2co.1·ωld   (44)


From triangle “XPE” the following can be written:










20


log


(
PX
)



=


40


log


(
XE
)



=



40


log


(

ω
E

)



-

40


log


(

ω
Σ

)




=

20


log


(


ω
E
2


ω
Σ
2


)









(
45
)







Or with the help of (44):









PX
=



ω
E
2


ω
Σ
2


=



ω

co
·
1


·

ω
ld



ω
Σ
2







(
46
)







Now, from triangle “XPB” the following can be written:










20






log


(
PX
)



=


20






log


(
BX
)



=



20






log


(

ω
int

)



-

20






log


(

ω
Σ

)




=

20






log


(


ω
int


ω
Σ


)









(
47
)







Or:










(
PX
)

=


ω
int


ω
Σ






(
48
)







From (46) and (48):










ω
int

=



ω

co
·
1


·

ω
ld



ω
Σ






(
49
)







Let's take into account equation (2), then:










ω
int

=



L
sys

·

ω

co
·
1


·

ω
ld



R
Σ






(
50
)







Let's determine the limitation for “ωld” as follows:





ωΣ≤ωld.real≤ωco.1.real   (51)


Let's represent “ωld” using the following equality:





ωld=b·ωΣ  (52)


Or









b
=


ω
ld


ω
Σ






(

52

a

)







According to (51) limitation for “b” can be written as follows:









1


b
real




ω

co
·
1
·
real



ω
Σ






(
53
)







Finally “Ki” and “Kp” can be determined according to equations (18, 50) and (19, 50) as follows:






K
i
=R
Σ·ωint=Lsysωco.1.realωld=Lsys·ωco.1.real·breal·ωΣ   (54)










K
p

=



R
Σ

·


ω
int


ω
ld



=


L
sys

·

ω

co
·
1
·
real








(
55
)







Or:






K
i
=K
pωld=Kp·breal·ωΣ  (56)


Equations (39, 51-56) determines all PI controller parameters.


To determine PI controller's parameters more precisely let's analyze phase margin at the current loop frequency crossover point.


According to FIG. 6 the open current loop transfer function can be written as follows:











H


i
·
open

-
loop




(
p
)


=




H
PI



(
p
)


·


H
inv



(
p
)


·


H
object



(
p
)



=




[


R
Σ

·


(

1
+

pT
ld


)


pT
int


·

1

1
+

pT
lag




]

·




[

e

ω
·
τ


]

·

[


1

R
Σ


·

1

1
+

pT
Σ



·

1

1
+

2

ξ






T
pk


p

+


T
pk
2



p
2





]










(
57
)







Finally:











H


i
·
open

-
loop




(
p
)


=




H
PI



(
p
)


·


H
inv



(
p
)


·


H
object



(
p
)



=


1

pT
int


·

e

ω
·
τ


·

(

1
+

pT
ld


)

·

1

1
+

pT
lag



·

1

1
+

pT
Σ



·

1

1
+

2

ξ






T
pk


p

+


T
pk
2



p
2










(
58
)







Where “τ” is inverter time delay and can be represented as follows:









τ
=

1

f

carrier
·
inverter







(
59
)







Appropriate phase margin at the point of current loop frequency crossover can be determine based on the follows equation:





Δφ0co.1.real)=1800φtotal-phase-shift-open-current-loop≥300    (60)


Where “300” is a practical arbitrary phase margin.


According to (58, 60) the following can be written:











Δϕ
0



(

ω

co
·
1
·
real


)


=



180
0

-

90
0

-



180
0

π

·

[


τ
·

ω

co
·
1
·
real



+

a






tan


(


ω

co
·
1
·
real



ω
lag


)



+

a






tan


(


ω

co
·
1
·
real



ω
Σ


)



-

a






tan


(


ω

co
·
1
·
real



ω
ld


)



+

a






tan
(


2
·
ξ
·

ω

co
·
1
·
real





ω
pk

-


ω

co
·
1
·
real

2


ω
pk




)



]





30
0






(
61
)







Practically, term










180
0

π

·

[

a






tan
(


2
·
ξ
·

ω

co
·
1
·
real





ω
pk

-


ω

co
·
1
·
real

2


ω
pk




)


]







is very small (less than 1 degree) and can be omitted.


Finally, phase margin can be rewritten as follows:











Δϕ
0



(

ω

co
·
1
·
real


)


=



90
0

-



180
0

π

·

{


τ
·

ω

co
·
1
·
real



+

a






tan


(


ω

co
·
1
·
real



ω

lag
·
real



)



+

[


a






tan


(


ω

co
·
1
·
real



ω
Σ


)



-

a






tan
(


ω

co
·
1
·
real



ω

ld
·
real



)



]


}





30
0






(
62
)







Or, after some manipulation:











Δϕ
0



(

ω

co
·
1
·
real


)


=



90
0

-



180
0

π

·

{


τ
·

ω

co
·
1
·
real



+

a






tan
(


ω

co
·
1
·
real



ω

lag
·
real



)


+

a






tan
(



ω

co
·
1
·
real


·

(


ω

ld
·
real


-

ω
Σ


)





ω

ld
·
real


·

ω
Σ


+

ω

co
·
1
·

real
2





)



}





30
0






(

62

a

)







Or:










Δ







ϕ
0



(

ω

co


.1
.
real



)



=



90
°

-


(


180


π

)

·

{


(


ω

co


.1
.
real



·
τ

)

+

[

a






tan


(


x
+
y


1
-

x
·
y



)



]


}



>

30
°






(
63







Where:









y
=




ω

co
·
1
·
real


·

(


ω

ld
·
real


-

ω
Σ


)





ω

ld
·
real


·

ω
Σ


+


ω

co
·
1
·
real


2



=



ω

co
·
1
·
real


·

ω
Σ

·

(


b
real

-
1

)





b
real

·

ω
Σ
2


+


ω

co
·
1
·
real


2








(
65
)







Manipulate with “ωld”, “ωlag”, sometimes “ωco.1.real” and take into account (37, 38, and 51) finally we can establish all necessary PI controller's parameters with appropriate phase margin.



FIG. 11 shows another example using first and second lag units, where the transfer function can be represented as follows:










H

PI
-

2

lag



=



R


·


1
+

pT
ld



pT
int


·

1

1
+

pT

lag





1




·

1

1
+

pT

lag





2





=


[



K
i


p

+

K
p


]

·


ω

lag





1




ω

lag





1


+
p


·


ω

lag





2




ω

lag





2


+
p








(
66
)







Where “Ki” and “Kp” can be determined by according to equations (18-19).



FIG. 11 represents general Bode log-log plot for the above current loop with a controller that includes two lag units. As you can see with two lag units approach current loop frequency crossover can be reached well larger value with the same stability margin. The following demonstrates a relationship between the filter resonance frequency “ωpk”, the current loop frequency crossover “ωco” and the rest of controller's parameters according to the condition is shown on FIG. 11.


For triangle “SRT” the following can be written:










20


log


(
TR
)



=


60


log


(
TS
)



=



60


log


(

ω

lag
·
2


)



-

60


log


(

ω
S

)




=

60


log


(


ω

lag
·
2

3


ω
S
3


)









(
67
)







Or:









TR
=



ω

lag

.2

3


ω
S
3


.





(
68
)







For triangle “DTR” the following can be written:










20


log


(
TR
)



=


40


log


(
TD
)



=



40


log


(

ω

lag
·
2


)



-

40


log


(

ω
D

)




=

40


log


(


ω

lag
·
2

2


ω
D
2


)









(
69
)







Or:









TR
=



ω

lag

.2

2


ω
D
2


.





(
70
)







From (68) and (70) we can derive:











ω

lag
·
2

3


ω
S
3


=


ω

lag
·
2

2


ω
D
2






(
71
)






Or


:













ω
S
3

=




ω

lag
·
2

3

·

ω
D
2



ω

lag
·
2

2


=


ω

lag
·
2


·

ω
D
2







(
72
)







For triangle “FGM” the following can be written:











20


log


(
MG
)



=


20


log


(
FM
)



=



20


log


(

ω

lag
·
1


)



-

20


log


(

ω

co
·
2


)




=

20


log


(


ω

lag
·
1



ω

co
·
2



)






,





where








ω

co
·
2















is





a





current











loop











frequency





crossover





for





2





lag





units





(
73
)







approach.


Or:






MG=ω
lag.1co.2   (74)


For triangle “DGM” the following can be written:










20


log


(
MG
)



=



40


log


(

ω

lag
·
1


)



-

40


log


(

ω
D

)




=

20


log


(


ω

lag
·
1

2


ω
D
2


)








(
75
)







Or:









MG
=


ω

lag

.1

2


ω
D
2






(
76
)







From (74) and (76) we can derive:











ω

lag
·
1



ω

co
·
2



=


ω

lag
·
1

2


ω
D
2






(
77
)







Or:





ωD=√{square root over (ωco.2·ωlag.1)}  (78)


From (72) and (78) we can derive:





ωS3lag.2·ωD2co.2·ωlag.1·ωlag.2   (79)


For triangle “SNK” the following can be written:










20


log


(
NK
)



=


60


log


(
NS
)



=



60


log


(


ω
pk

-

ω
fund


)



-

60


log


(

ω
S

)




=

20


log


(



(


ω
pk

-

ω
fund


)

3


ω
S
3


)









(
80
)







Or:









NK
=



(


ω
pk

-

ω
fund


)

3


ω
S
3






(
81
)







From (79) and (81) we can derive:














NK
=



(


ω
pk

-

ω
fund


)

3



ω

co
·
2


·

ω

lag
·
1


·

ω

lag
·
2









(
82
)







20


log


(
NK
)



=



20


log


(
KW
)



+

20


log


(
NW
)




=



20


log


(

1

2
·
ξ


)



+

20


log


(
margin
)




=

20


log


(

margin

2
·
ξ


)









(
83
)







A stability margin limit can be determine as follows (3.5 db is a practical arbitrary number):





3.5 db≤20 log(margin)   (84)


Or:





1.5≤margin   (85)


From (85):





marginmin=1.5   (86)


Therefore from equation (83):









NK
=

margin

2
·
ξ






(
87
)







Finally, we can calculate a limit value for current loop frequency crossover using equations (82, 86, and 87):










ω

co
·
2
·
max


=


2
·
ξ
·


(


ω
pk

-

ω

fund
·
max



)

3




margin
min

·

ω

lag
·
1
·
real


·

ω

lag
·
2
·
real








(
88
)







According to equations (25, 27)





ωlag.1.min=2·ωco2   (89)


According to equation (27a) maximum phase shift at a current loop frequency crossover for “ωlag.1.min” equals:





Δφ0lag.1.min(@ωco.2))=26.560   (89a)


“ωlag.2” can be represented as follows:





ωlag.2=d·ωco.2   (90)


Practically (just for example) this additional phase shift should not be more than 15 degrees (arbitrary number). Therefore “dmin” can be calculated as follows:











15
0

>

atan


[


ω

co
·
2



ω

lag
·
2
·
min



]



=

atan


[

1

d
min


]






(

90

a

)







Or, from (26):





dmin=3.73   (90b)


In a future calculation we will use round “dmin” as follows:





dmin=3.5   (90c),


Then:










atan


[

1
3.5

]


=

15.94
0





(

90

d

)







Therefore combined additional phase shift from 2 lag units equals (see equations 89a and 90d):





Δφ2.lag.units0=Δφ0lag.1.min(@ωco.2))+Δφ0lag.2.min(@ωco.2))=26.560+15.940=42.50   (90e).





ωlag.2.min=3.5·ωco.2   (91)


Now we can recalculate current loop frequency crossover limit (88) with the help of equations (86, 89, and 91) as follows:










ω

co
·
2
·
max


=



(


ω
pk

-

ω

fund
·
max



)

·



2
·
ξ



a
min

·

d
min

·

margin
min



3


=



(


ω
pk

-

ω

fund
·
max



)

·


ξ
5.25

3


=



(


ω
pk

-

ω

fund
·
max



)

1.738

·

ξ
3








(
92
)







According to (92) with some additional margin we can choose any current loop frequency crossover as follows:










ω




ω

co
·
2
·
real






(


ω
pk

-

ω

fund
·
max



)

1.738

·

ξ
3






(
93
)







Minimum corner frequency of a lag1 unit can be calculated as follows:





ωlag.1.min=2·ωco.2.real   (94)


Minimum corner frequency of a lag2 unit can be calculated as follows:





ωlag.2.min=3.5·ωco.2.real   (95)


According to (94, 95) and practical digital implementation (29) of lag units the following can be written:










2
·

ω

co
·
2
·
real





ω

la
·
1
·
real





π
·

f
carrier



2.5
·

ω

co
·
2
·
real








(
96
)







3.5
·

ω

co
·
2
·
real





ω

lag
·
2
·
real





π
·

f
carrier



2.5
·

w

co
·
2
·
real








(
97
)







And real margin can be calculated as follows:










margin
real

=


2
·
ξ
·


(


ω
pk

-

ω

fund
·
max



)

3




ω

co
·
2
·
real


·

ω

lag
·
1
·
real


·

ω

lag
·
2
·
real








(
98
)







Now we need to determine appropriate “Ki, Kp” values.


From triangle “ZYF” the following can be written:










20






log


(
ZY
)



=


20






log


(
ZF
)



=



20






log


(

ω

co
·
2


)



-

20






log


(

ω
ld

)




=

20






log


(


ω

co
·
2



ω
ld


)









(
99
)







Or:









ZY
=


ω

co
·
2



ω
ld






(
100
)







From triangle “ZYE” the following can be written:










20






log


(
ZY
)



=


40






log


(
ZE
)



=



40






log


(

ω
E

)



-

40






log


(

ω
ld

)




=


40






log


(


ω
E


ω
ld


)



=

20






log


(


ω
E
2


ω
ld
2


)










(
101
)







Or:









ZY
=


ω
E
2


ω
ld
2






(
102
)







From (100) and (102):





ωE2co.2·ωld   (103)


From triangle “XPE” the following can be written:










20






log


(
PX
)



=


40






log


(
XE
)



=



40






log


(

ω
E

)



-

40






log


(

ω
Σ

)




=

20






log


(


ω
E
2


ω
Σ
2


)









(
104
)







Or with the help of (103):









PX
=



ω
E
2


ω
Σ
2


=



ω

co
·
2


·

ω
ld



ω
Σ
2







(
105
)







Now, from triangle “XPB” the following can be written:










20






log


(
PX
)



=


20






log


(
BX
)



=



20






log


(

ω
int

)



-

20






log


(

ω
Σ

)




=

20






log


(


ω
int


ω
Σ


)









(
106
)







Or:










(
PX
)

=


ω
int


ω
Σ






(
107
)







From (105) and (107):










ω
int

=



ω

co
·
2


·

ω
ld



ω
Σ






(
108
)







Let's take into account equation (2), then:










ω
int

=



L
sys

·

ω

co
·
2


·

ω
ld



R
Σ






(
109
)







Let's determine the limitation for “ωld” as follows:





ωΣ≤ωld≤ωco.2.real   (110)


Finally “Ki” and “Kp” can be determined according to equations (18, 109) and (19, 110) as follows:










K
p

=



R
Σ

·


ω
int


ω
ld



=


L
sys

·

ω

co
·
2
·
real








(
111
)









K
i
=R
Σ·ωint=Lsys·ωco.2.real·ωld=Kpωld   (112)


Equations (96-97, 111-112) determines all controller's parameters.


It is possible to determine controller's parameters more precisely if we will analyze phase margin at the current loop frequency crossover point. According to FIG. 6, the following can be written the open current loop transfer function as follows:











H


i
·
open

-


loop
·
2


lag





(
p
)


=




H


PI
·
2


lag




(
p
)


·


H
inv



(
p
)


·


H
object



(
p
)



=


[


R
Σ

·


(

1
+

pT
ld


)


pT
int


·

1

1
+

pT

lag





1




·

1

1
+

pT

lag





2





]

·

[

e

ω
·
τ


]

·

[


1

R
Σ


·

1

1
+

pT
Σ



·

1

1
+

2

ξ






T
pk


p

+


T
pk
2



p
2





]







(
113
)







Finally:











H


i
·
open

-


loop
·
2


lag





(
p
)


=




H


PI
·
2


lag




(
p
)


·


H
inv



(
p
)


·


H
object



(
p
)



=


1

pT
int


·

e

ω
·
τ


·

(

1
+

pT
ld


)

·

1

1
+

pT

lag





1




·

1

1
+

pT

lag





2




·

1

1
+

pT
Σ



·

1

1
+

2

ξ






T
pk


p

+


T
pk
2



p
2










(
114
)







Where “τ” is inverter time delay and can be represent as follows:









τ
=

1

f

carrier
·
inverter







(
115
)







Appropriate phase margin at the point of current loop frequency crossover can be determine based on follows equation:





Δφ0co.2.real)=1800−φtotal-phase-shift-open-current-loop-2lag≥300   (116)


According to (105, 107) the following can be written:







Δ







ϕ
0



(

ω

co

.2


)



=



180
°

-

90
°

-



180
°

π

·

{


τ
·

ω

co

.2



-

a






tan


(


ω

co

.2



ω

ld
.
real



)



+

a






tan


(


ω

co

.2



ω

lag





1.

real



)



+

a






tan


(


ω

co

.2



ω

lag





2.

real



)



+

a






tan


(


ω

co

.2



ω
Σ


)



+

a






tan
(


2
·
ξ
·

ω

co

.2





ω
pk

-


ω

co

.2

2


ω
pk




)



}





30
°






Practically, term








a






tan
(


2
·
ξ
·

ω

co


.2
.
real






ω
pk

-


ω

co


.2
.
real


2


ω
pk




)







is very small (less than 1 degree) and can be omitted.


Finally, phase margin can be write as follows:










Δ







ϕ
0



(

ω

co


.2
.
real



)



=


90
°

-



180
°

π

·

{



τ
·

ω

co


.2
.
real




+

[


a






tan


(


ω

co


.2
.
real




ω
ld


)



-

a






tan


(


ω

co


.2
.
real




ω
Σ


)




]

+



[


a






tan


(


ω

co


.2
.
real




ω

lag





1



)



+

a






tan


(


ω

co


.2
.
real




ω

lag





2



)




]

}




30










(
117
)







After some manipulation we can derive:










Δ







ϕ
0



(

ω

co


.2
.
real



)



=



90
°

-


(


180
°

π

)

·

{


(

τ
·

ω

co


.2
.
real




)

+

[

a






tan


(


x
+
y


1
-

x
·
y



)



]


}



>

30







(
118
)







Where:









x
=



ω

co


.2
.
real



·

(


ω

ld
.
real


-

ω
Σ


)





ω

ld
.
real


·

ω
Σ


+

ω

co


.2
.
real


2







(
119
)






y
=



ω

co


.2
.
real



·

(


ω

lag


.1
.
real



+

ω

lag


.2
.
real




)





ω

lag


.1
.
real



·

ω

lag


.2
.
real




-

ω

co


.2
.
real


2







(
120
)







Manipulate with “ωld”, “ωlag1”, “ωlag2”, sometimes “ωco.2.real” and take into account (93, 96, 97, and 110) finally we can establish all necessary PI controller's parameters. Disclosed examples include power conversion systems 40, methods 300 and computer readable mediums 104 to operate an inverter 46 to drive a motor load 20 through an output filter 30, in which a control output value COd,q is computed according to a current reference value Id,q.ref and a current feedback value Id,qfbk using a proportional-integral PI current regulator 106, the control output value COd,q is filtered using a lag compensator filter 108 to compute an inverter output command value Vd,q.com, and the inverter 46 is controlled according to the inverter output command value Vd,q.com. The examples of FIGS. 10 and 11 use a single lag compensator 108 with a corner frequency profile 1006, 1106 to provide a −20 db/dc slope in combination with the leading characteristic of the PI regulator to shift the profile of the closed current loop curve 1004, 1104 to ensure a desired amplitude margin 1010, 1110 below unity (below the X axis in FIGS. 10 and 11), in consideration of the peak amplitude amount 1012, 1112 associated with the weakly damped output filter 30. In addition, disclosed examples of the lag compensator filter (108) are designed to provide a non-zero phase margin (1010, 1110) at the current control loop crossover frequency (ωco) of the closed current control loop.


In the preceding specification, various embodiments have been described with reference to the accompanying drawings. It will be evident that various modifications and changes may be made thereto, and additional embodiments may be implemented, without departing from the broader scope of the invention as set forth in the claims that follow. The specification and drawings are accordingly to be regarded in an illustrative rather than restrictive sense.

Claims
  • 1. A power conversion system, comprising: an inverter comprising a DC input, an AC output, and a plurality of switching devices coupled between the DC input and the AC output and operative according to inverter switching control signals to convert DC electrical power received at the DC input to provide AC electrical output power at the AC output to drive a motor load through an intervening output filter; anda controller configured to: compute a control output value according to a current reference value and a current feedback value using a proportional-integral (PI) current regulator implemented by the controller,filter the control output value to compute an inverter output command value using a lag compensator filter implemented by the controller, wherein the lag compensator filter is designed to provide a non-zero amplitude margin below unity at a resonance frequency of a current control loop, and provide the inverter switching control signals to control the inverter according to the inverter output command value.
  • 2. The power conversion system of claim 1, wherein the lag compensator filter includes one or more lag compensators designed according to a current control loop resonance frequency of a current control loop, an inverter operating fundamental frequency, a peak resonance frequency of the output filter, a desired lead corner frequency of the current control loop, a desired amplitude margin below unity at the resonance frequency of the current control loop, a desired current control loop crossover frequency of the current control loop, and a plant corner frequency, wherein the current control loop resonance frequency is equal to a difference between the peak resonance frequency of the output filter and the inverter operating fundamental frequency.
  • 3. The power conversion system of claim 2, wherein the lag compensator filter includes a first lag compensator filter having a first lag filter corner frequency between the current control loop crossover frequency and the current control loop resonance frequency.
  • 4. The power conversion system of claim 3, wherein the lag compensator filter includes a second lag compensator filter having a second lag filter corner frequency between the first lag filter corner frequency and the current control loop resonance frequency.
  • 5. (canceled)
  • 6. (canceled)
  • 7. The power conversion system of claim 4, wherein the first and second lag compensators are designed to provide a non-zero phase margin at the current control loop crossover frequency.
  • 8. The power conversion system of claim 4, wherein the controller is further configured to: compute a speed error value according to a speed reference value and a speed feedback value;compute a torque reference value according to the speed error value; andcompute the current reference value according to the torque reference value.
  • 9. (canceled)
  • 10. The power conversion system of claim 3, wherein the first lag compensator is designed to provide a non-zero phase margin at the current control loop crossover frequency.
  • 11. The power conversion system of claim 3, wherein the controller is further configured to: compute a speed error value according to a speed reference value and a speed feedback value;compute a torque reference value according to the speed error value; andcompute the current reference value according to the torque reference value.
  • 12. (canceled)
  • 13. The power conversion system of claim 2, wherein the lag compensator filter is designed to provide a non-zero phase margin at the current control loop crossover frequency.
  • 14. The power conversion system of claim 2, wherein the controller is further configured to: compute a speed error value according to a speed reference value and a speed feedback value;compute a torque reference value according to the speed error value; andcompute the current reference value according to the torque reference value.
  • 15. (canceled)
  • 16. The power conversion system of claim 1, wherein the lag compensator filter is designed to provide a non-zero phase margin at a current control loop crossover frequency.
  • 17. The power conversion system of claim 1, wherein the controller is further configured to: compute a speed error value according to a speed reference value and a speed feedback value;compute a torque reference value according to the speed error value; andcompute the current reference value according to the torque reference value.
  • 18. A method of operating an inverter to drive a motor load through an output filter, the method comprising: using a proportional-integral (PI) current regulator implemented by a processor, computing a control output value according to a current reference value and a current feedback value;using the processor, filtering the control output value to compute an inverter output command value using a lag compensator filter implemented by the controller, wherein the lag compensator filter is designed to provide a non-zero amplitude margin below unity at a resonance frequency of a current control loop; andcontrolling the inverter according to the inverter output command value.
  • 19. The method of claim 18, comprising: using the processor, computing a speed error value according to a speed reference value and a speed feedback value;using the processor, computing a torque reference value according to the speed error value; andusing the processor, computing the current reference value according to the torque reference value.
  • 20. A power conversion system, comprising: an inverter comprising a DC input, an AC output, and a plurality of switching devices coupled between the DC input and the AC output and operative according to inverter switching control signals to convert DC electrical power received at the DC input to provide AC electrical output power at the AC output to drive a motor load through an intervening output filter; anda controller configured to: filter a current feedback value to compute a filtered current feedback value using a lag compensator filter implemented by the controller, wherein the lag compensator filter is designed to provide a non-zero amplitude margin below unity at a resonance frequency of a current control loop,compute an inverter output command value according to a current reference value and the filtered current feedback value using a proportional-integral (PI) current regulator implemented by the controller, andprovide the inverter switching control signals to control the inverter according to the inverter output command value.
INCORPORATION BY REFERENCE

The following U.S. patents, patent applications and published patent applications are hereby incorporated by reference in their entireties: U.S. Pat. No. 9,124,209 issued Sep. 1, 2015 to Liu et al., entitled METHOD AND APPARATUS FOR CONTROLLING POWER CONVERTER WITH INVERTER OUTPUT FILTER; U.S. Patent Application Publication No. 2015/0123579 A1 to Liu et al., entitled METHOD AND APPARATUS FOR CONTROLLING POWER CONVERTER WITH INVERTER OUTPUT FILTER, and filed as U.S. patent application Ser. No. 14/555,769 on Nov. 28, 2014; U.S. Pat. No. 9,054,621 issued Jun. 9, 2015 to Liu et al., entitled POSITION SENSORLESS OPEN LOOP CONTROL FOR MOTOR DRIVES WITH OUTPUT FILTER AND TRANSFORMER; U.S. Patent Application Publication No. 2015/0194901 Al to Liu et al., entitled POSITION SENSORLESS OPEN LOOP CONTROL FOR MOTOR DRIVES WITH OUTPUT FILTER AND TRANSFORMER, and filed as U.S. patent application Ser. No. 14/666,894 on Mar. 24, 2015; U.S. Pat. No. 9,054,611 issued Jun. 9, 2015 to Liu et al., entitled METHOD AND APPARATUS FOR STABILITY CONTROL OF OPEN LOOP MOTOR DRIVE OPERATION; U.S. Patent Application Publication No. 2015/0002067 A1 to Nondahl et al., entitled METHOD AND APPARATUS FOR STABILITY CONTROL OF OPEN LOOP MOTOR DRIVE OPERATION, and filed as U.S. patent application Ser. No. 14/193,329 on Feb. 28, 2014; U.S. patent application Ser. No. 14/565,781 filed Dec. 10, 2014 to Nondahl et al., entitled TRANSITION SCHEME FOR POSITION SENSORLESS CONTROL OF AC MOTOR DRIVES; U.S. patent application Ser. No. 15/014,360 filed Feb. 3, 2015 to Royak et al., entitled CONTROL OF MOTOR DRIVES WITH OUTPUT SINEWAVE FILTER CAPACITOR CURRENT COMPENSATION USING SINEWAVE FILTER TRANSFER FUNCTION; U.S. patent application Ser. No. 15/053,135 filed Feb. 25, 2016 to Nondahl et al., entitled SENSORLESS MOTOR DRIVE VECTOR CONTROL WITH FEEDBACK COMPENSATION FOR FILTER CAPACITOR CURRENT; and U.S. patent application Ser. No. 15/053,273 filed Feb. 25, 2016 to Nondahl et al., entitled SENSORLESS MOTOR DRIVE VECTOR CONTROL.