Patent Application
20250147531
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2023-190903, filed on Nov. 8, 2023, the entire contents of which are incorporated herein by reference.
The present disclosure relates to a current detection circuit that detects a large or small current using a comparator and a power supply semiconductor integrated circuit (power supply IC) incorporating the current detection circuit, and relates to a technique that is effective for use in a power supply semiconductor integrated circuit having a plurality of output terminals to which a load is connected and using a current detection circuit to detect an open error or short error of the plurality of output terminals or load, for example.
In automobiles equipped with terrestrial digital (terrestrial digital TV broadcasting) tuners, an in-vehicle regulator supplies power to on-board electronic devices such as antennas for terrestrial digital broadcasting. In in-vehicle terrestrial digital tuners that support full-segment broadcasting, diversity antennas, which are equivalent antennas for four channels, are generally used as antennas for terrestrial digital broadcasting to optimize reception situations by adjusting reception sensitivity and switching between full-segment and one-segment broadcasting at the tuner.
On the other hand, since in-vehicle tuners and antennas are connected to the in-vehicle regulator via connectors, vibration of the vehicle body can cause the connectors to disconnect and open the output terminals of the power supply, or cause a wire break or a short-circuit (short) inside the load. For this reason, some in-vehicle regulators are equipped with a function to detect such error states.
Conventionally, inventions related to semiconductor integrated circuits for regulators (IC for regulators) configured to detect an open or short state of an output terminal, generate an error detection signal, generate an error detection signal and output the signal from the output terminal are described in JP-A-2017-45096 and No. JP-A-2023-43049.
Both the JP-A-2017-45096 and JP-A-2023-43049 inventions are configured as regulators that can supply power for two channels (2ch). Among these, the invention in JP-A-2017-45096 allows the threshold for error detection to be set separately from the two external terminals corresponding to the two channels. The invention in JP-A-2023-43049 uses a common threshold for error detection for two channels to reduce the number of external terminals for setting the threshold.
In both the JP-A-2017-45096 and JP-A-2023-43049 inventions, the open or short state of the output terminal is detected by using a comparator that compares a voltage proportional to the output current with an externally set threshold voltage and makes determination. Therefore, when the output current increases or decreases near the threshold value due to noise, the comparator output repeatedly changes high or low. To prevent such malfunctions due to noise, it is necessary to provide hysteresis in the comparison operation of the comparator.
Although JP-A-2023-43049 states that a comparator with hysteresis characteristics should be used, it does not disclose the specific configuration for providing hysteresis. Also, in JP-A-2017-45096 and JP-A-2023-43049, examples of regulators composed of MOS transistors are disclosed, and specific examples of regulators composed of bipolar transistors are not disclosed.
An object of the present disclosure is to provide a current detection circuit capable of providing hysteresis to the comparison operation of a comparator whose detection target is a current, and a power supply semiconductor integrated circuit incorporating the current detection circuit.
Another object of the present disclosure is, in a power supply semiconductor integrated circuit having a current detection circuit that detects an open state or a short state of an output terminal using a comparator and composed of a bipolar transistor, to prevent a transistor constituting a hysteresis circuit in the current detection circuit from operating in the saturation region.
In order to achieve the above objects, according to an aspect of the present disclosure, there is provided
The accompanying drawings are not intended as a definition of the limits of the invention but illustrate embodiments of the invention, and together with the general description given above and the detailed description of the embodiments given below, serve to explain the principles of the invention, wherein:
Hereinafter, one or more embodiments of the present disclosure will be described with reference to the drawings. However, the scope of the present disclosure is not limited to the disclosed embodiments.
In the regulator IC10 of this embodiment, as shown in
Between the output terminals OUT1 and OUT2 and the ground line to which the ground potential GND is applied, resistors R11 and R12 and resistors R21 and R22 are connected in series to divide the output voltage Vout1 and Vout2, respectively. R11, R12, R21 and R22 can be provided outside the regulator IC10 if a separate external terminal connected to the midpoint between resistors R11 and R12 or R21 and R22 is provided.
The voltage VFB1 divided by the resistors R11 and R12 for the above output voltage dividing is fed back to the non-inverting input terminal of an error amplifier 11A as an error amplifier circuit controlling the base terminal of the above transistor Qp1, and the voltage VFB2 divided by the above resistors R21 and R22 is fed back to the non-inverting input terminal of the error amplifier 11B that controls the base terminal of the above transistor Qp2. The error amplifiers 11A and 11B control the transistors Qp1 and Qp2 according to the potential difference between the output feedback voltages VFB1 and VFB2 and a predetermined reference voltage Vref, so that the output voltages Vout1 and Vout2 become the desired potential by flowing current according to the load. As a result, transistors Qp1 and Qp2 function as current control elements and voltage control elements.
Furthermore, the regulator IC 10 of this embodiment has a reference voltage circuit 12 for generating a reference voltage Vref applied to the inverting input terminals of the above error amplifiers 11A and 11B, and a bias circuit 13 for flowing an operating current in the error amplifiers 11A and 11B and the reference voltage circuit 12.
The above reference voltage circuit 12 can be composed of a band gap reference circuit, a series of resistors and Zener diodes.
Furthermore, in the regulator IC 10 of this embodiment, transistors Qs1 and Qs2, which constitute current mirror circuits with the above transistors Qp1 and Qp2 for current control respectively, are provided in parallel with the transistors Qp1 and Qp2, and the same voltages as those applied to the base terminals of the transistors Qp1 and Qp2, that is, the output voltages of the above error amplifiers 11A and 11B, are applied to the base terminals as control terminals of these transistors Qs1 and Qs2. This allows currents proportional to the collector currents of Qp1 and Qp2 (1/N current) to flow in Qs1 and Qs2, depending on the size ratio N of the elements.
Furthermore, the regulator IC10 of this embodiment is provided with resistors R31 and R32 as current-to-voltage converters, which are connected in series with the above current mirror transistors Qs1 and Qs2, respectively, and convert the current flowing in Qs1 and Qs2 into voltages. The voltages converted by the resistors R31 and R32 are input to one input terminals of comparators CMP1 and CMP2 and compared with a threshold voltage Vth applied to the other input terminals. Therefore, the resistor R31 and the comparator CMP1 constitute a current detection circuit 14A, and the resistor R32 and the comparator CMP2 constitute a current detection circuit 14B.
Hysteresis circuits 17A and 17B are provided corresponding to the above current detection circuits 14A and 14B to provide hysteresis to the comparison operation of the comparators CMP1 and CMP2 by increasing or decreasing the current flowing in the transistors Qs1 and Qs2 according to the output state of the comparators CMP1 and CMP2. The specific configuration and operation of the hysteresis circuits 17A and 17B will be described in detail later.
There are provided an external terminal P1 for connecting a voltage-current converting resistor Rdet outside the chip, and a voltage converter 15 that generates a voltage Vth in accordance with the voltage Vdet generated at the external terminal P1, and the comparators CMP1 and CMP2 compare the voltage Vth generated by the voltage converter 15 and the voltages converted by the resistors R31 and R32 to detect either an open or short error in the output terminals OUT1 and OUT2. Therefore, the voltage Vth is the threshold for determining an open or short error.
When the comparators CMP1 and CMP2 are used as open error detection means, to one input terminals (+ or −) of the comparators CMP1 and CMP2, the currents Iout1′ and Iout2′ of Qs1 and Qs2 are applied through the resistors R31 and R32 to generate voltages, and a threshold voltage Vtho is generated at the other input terminals (− or +).
On the other hand, when the comparators CMP1 and CMP2 are made to function as short error detection means, one input terminals (− or +) of the comparators CMP1 and CMP2 are used to generate voltage by flowing the currents Iout1′ and Iout2′ of Qs1 and Qs2 in the resistors R31 and R32 to generate voltages, and the threshold voltage Vths is generated at the other input terminals (+ or −).
The inverting/non-inverting input terminals (− or +) of the comparators CMP1 and CMP2, to which Vtho or Vths is input, can be either by the logic of a logic circuit 16 in the subsequent stage. Therefore, in
Here, there is a possibility that Vth and Vtho or Vths are limited by the input dynamic range of the comparators CMP1 and CMP2 if they are too high or too low, and if they are too low, the voltage generated across the resistors R4, R31, and R32 will be small, which raises an accuracy issue. Therefore, when the comparators CMP1 and CMP2 are used as open error detection means, since the current flowing through the transistors Qp1 or Qp2 is small, it is desirable that the current mirror ratio m of the transistors Qp1 and Qs1 or the transistors Qp2 and Qs2 are set to be small to make the current flowing through the transistors Qs1 or Qs2 relatively large, so that Vtho does not become too small.
On the other hand, when the comparators CMP1 and CMP2 are used as short error detection means, since the current flowing through the transistors Qp1 or Qp2 is large, it is desirable to set the current mirror ratio m of the transistors Qp1 and Qs1 or the transistors Qp2 and Qs2 to be large and make the current flowing through the transistors Qs1 or Qs2 relatively small, so that Vths does not become too large.
Furthermore, the regulator IC 10 of this embodiment has a logic circuit 16 that takes the outputs of the above comparators CMP1 and CMP2 for error detection as inputs and an external terminal P2 that outputs a signal ERR indicating that the comparators CMP1 and CMP2 detected an error.
In the example shown in
The above logic circuit 16 is configured as a circuit with an OR logic function if an error state is indicated when the outputs of the above comparators CMP1 and CMP2 for error detection are high level, and it is output as a low level error detection signal ERR. The above logic circuit 16 is configured as a circuit with a NAND logic function if an error state is indicated when the outputs of the above comparators CMP1 and CMP2 for error detection are low level, and it is output as a low level error detection signal ERR. The above logic circuit 16 is configured as a circuit with a NOR logic function if an error state is indicated when the outputs of the above comparators CMP1 and CMP2 for error detection are low level, and it is output as a high level error detection signal ERR.
Furthermore, two external terminals for outputting an error detection signal may be provided to output two-bit error detection signals corresponding to the outputs of the comparators CMP1 and CMP2, respectively, to the outside, in which case the logic circuit 16 can be configured as a delay circuit, for example.
As explained above, in the regulator IC10 of this embodiment, when equivalent loads are connected to the output terminals OUT1 and OUT2, an open or short error can be detected by simply providing one external terminal to which an external resistor Rdet is connected. It also thereby reduces chip size. Furthermore, the reduced number of terminals and components allows the use of smaller and less expensive packages, which saves space and reduces the cost of power supply devices.
In addition, the threshold value for detecting an open or short error can be easily changed by changing the resistance value of the external resistor Rdet, thereby expanding the applications of the IC. Furthermore, the hysteresis circuits 17A and 17B are provided so that the comparators CMP1 and CMP2 can operate in hysteresis, preventing the current detection circuits 14A and 14B from malfunctioning due to noise. Moreover, hysteresis can be set separately for current detection circuits 14A and 14B.
Next, the specific circuits of the voltage converter 15 and hysteresis circuits 17A and 17B in the IC are described. First, as shown in
The current buffer 15a of the above voltage converter 15 has the output terminal of the above amplifier AMP connected to the base terminal of the NPN bipolar transistor Q0, and the emitter terminal of the transistor Q0 is connected to the inverting input terminal of the amplifier AMP. This allows the amplifier AMP to function as a voltage follower and operate the transistor Q0 so that the emitter voltage of the transistor Q0 (potential of external terminal P1) is equal to the input voltage of the non-inverting input terminal (reference voltage Vref).
The above amplifier AMP can be configured by a general differential amplifier circuit consisting of a constant current source (or resistor), a pair of load transistors, and a pair of differential input transistors with the above reference voltage Vref and the voltage Vdet of the external terminal P1 input to the base terminal, and it operates as a current buffer that flows a predetermined collector current in the transistor Q0.
On the other hand, the current mirror circuit 15b consists of a PNP bipolar transistor Q1 connected in series with Q0 at the collector terminal of the above transistor Q0, a PNP bipolar transistor Q2 connected in current mirror with the transistor Q1, and a resistor R4 connected at the collector terminal of the transistor Q2. The voltage obtained by the current-to-voltage conversion by the resistor R4 is supplied to the comparators CMP1 and CMP2 as the threshold voltage Vth. Therefore, the current buffer 15a and the transistors Q1 and Q2 that constitute the current mirror circuit 15b constitute a reference current generation circuit that generates a current that serves as a reference for comparison in the aforementioned current detection circuits 14a and 14b.
The characteristics of the above voltage converter 15 is described here.
In the voltage converter 15 of this embodiment, the voltage Vdet at the external terminal P1 is equal to the reference voltage Vref, or Vdet=Vref, due to the function of the current buffer 15a. Therefore, the current I1 that is flowed in the external resistor R4 by the current buffer 15a is as follows.
Therefore, the comparison reference voltage Vth, which is converted and generated by the resistor R4 through which the current I2, with I1 folded back by the current mirror circuit 15b, flows, is expressed by the following equation (1) when the current mirror ratio is m.
On the other hand, the output current Iout1 at the output terminal OUT1 is converted to the voltage Vout1′ by flowing the current Iout1′ generated by the current mirror (n) of the transistors Qp1 and Qs1 in the resistor R31. Therefore, when the ratio of Qp1 to Qs1 is n, it is expressed by the following equation (2).
The comparator CMP1 detects the error by comparing the voltage given by the above equation (1) and the voltage given by equation (2). When the comparator CMP1 is used as a means of detecting open errors, the threshold voltage can be set by connecting the external resistor Rdet with a resistance value such that Vth=Vtho to the external terminal P1, and a regulator IC that detects an open state in the case of Vout1′ Vtho can be realized. When the comparator CMP1 is used as a means of detecting short errors, the threshold voltage can be set by connecting an external resistor Rdet with a resistance value such that Vth=Vths to the external terminal P1, and a regulator IC that detects a short-circuit in the case of Vout1′≥Vths can be realized.
Here, since both internal resistors R31 and R4 of the IC are on-chip elements, the relative ratio is good (about ±0.5%), and the variation in temperature characteristics due to manufacturing variation is canceled.
On the other hand, the reference voltage Vref of the voltage converter 15 can generate a highly accurate reference voltage by band gap, or the like, and the external resistor Rdet is a discrete component with good accuracy and temperature characteristics (resistance accuracy of about ±1% and temperature characteristics of about ±100 ppm/° C.) that can be manufactured or obtained. Therefore, a highly accurate comparison reference voltage Vth can be set, and the accuracy of open or short error detection can be improved.
The output current Iout2 of the output terminal OUT2 is similar to the above, and the voltage converter 15 and the comparator CMP2 can detect open or short errors with high accuracy. If the loads connected to the output terminals OUT1 and OUT2 have the same characteristics and flow the same current, the same comparison reference voltage Vth can be used for the comparators CMP1 and CMP2. Thus, the voltage converter 15 can be shared like the regulator IC10 in this embodiment, and the comparison reference voltage Vth can be set by providing one external terminal P1 and one external resistor Rdet.
Next, the configuration and operation of the aforementioned hysteresis circuits 17A and 17B will be described.
The present inventors, in developing a regulator composed of bipolar transistors, examined hysteresis circuits suitable for bipolar circuits. However, although the method of switching the threshold voltage is relatively easy to implement to give hysteresis to the comparator, the method of switching the threshold voltage cannot be applied when a common error detection threshold is used for two channels, as in the invention of JP 2023-43049. Therefore, the present inventors considered a method of switching the input voltage or current on the other detection target side of the comparator.
Of these, the circuit in
On the other hand, the circuit in
In both circuits of
In the circuit of
On the other hand, in the circuit of
As shown in
In the hysteresis circuit 17A having the above configuration, when the transistor Qsw1 for switching is in an on state, the current Isns1 flowing in the resistor R31 is Isns1=Iout1′+Ihys11 when the current flowing in the transistor Qh11 is 10′Ihys11. The output of comparator CMP1 is input to the base terminal of transistor Qsw1, which switches Qsw1 to the off state when a detection operation is performed. And if the current flowing in the transistor Qh21 is Ihys21, the current flowing in the resistor R31 is Isns1=Iout1′+Ihys11−Ihys21 when Qsw1 is in an off state.
Therefore, when the current detection circuit is used as an open error detection circuit, the open state is detected when Vth≤R31×(Iout1′+Ihys11−Ihys21) and the open state detection is released when Vth≥R31×(Iout1′+Ihys11). On the other hand, when the current detection circuit is used as short-circuit detection, the short state is detected when Vth≥R31×(Iout1′+Ihys11), and the short state detection is released when Vth≤R31×(Iout1′+Ihys11−Ihys21).
By operating as described above, the detection current value when performing the detection and release operations of the comparator CMP1 is different, which is the same as relatively switching the threshold voltage Vth, thus providing hysteresis to current detection circuit 14A. The width of hysteresis can be changed by adjusting the mirror ratio of transistors Qh31 and Qh41, which constitute the current mirror.
The aforementioned hysteresis circuit 17B, which is provided corresponding to the other current detection circuit 14B composed of the transistor Qs2, resistor R32 and comparator CMP2, has the same configuration as the hysteresis circuit 17A and performs the same operation as above.
As noted above, in the circuit of
In contrast, according to the hysteresis circuit 17A in this example, which is configured as described above, by the action of the transistors Qh31 and Qh41, which transfer the current of transistors Qh21 and Qh21 as a current source with a current mirror, and the transistor Qsw, which is responsible for stopping the current flowing in Qh31 and Qh41, Qh11 and Qh21 do not operate in the saturation region, Thus, the desired current hysteresis can be given. This is also true for the hysteresis circuit 17B. When the regulator IC10 of
In the example regulator IC 10 shown in
In the second example regulator IC10′ shown in
In the second example regulator IC 10′, the diode-connected transistors Q31 and Q32 do not allow the input voltages of comparators CMP1 and CMP2 (detection voltage converted by resistors R31 and R32) to fall below the threshold voltage of the NPN transistors. This ensures that the collector-emitter voltage of transistors Qh41 and Qh42 is sufficient and that Qh41 and Qh42 do not operate in the saturation region.
The diode-connected transistor Q4 in the voltage converter 15 prevents the potential difference between the input voltages of comparators CMP1 and CMP2 and the threshold voltage Vth generated by the voltage converter 15 from changing before and after the transistors Q31 and Q32 are installed. Along with this, even if the base-emitter voltages of transistors Q31 and Q32 differ from IC to IC due to manufacturing variations, the same variation in the base-emitter voltage of transistor Q4 can avoid reduction of the detection accuracy.
However, since the circuit in
An example regulator IC with the above countermeasures against variation is shown in
In the third example regulator IC 10″ shown in
In the third example of regulator IC10″, the diode-connected transistor for preventing saturation is shared by the resistors R4, R31, and R32, so that a difference in base-emitter voltage as in the second example cannot inevitably occur. The thresholds for the detection and release operations of comparator CMP1 are determined by comparing the voltage of resistor R4×current I2 and resistor R31×Isns1, and the thresholds for the operation and release operations of comparator CMP2 are determined by comparing the voltage of resistor R4×current I2 and resistor R32×Isns2. Therefore, it is possible to realize a current detection circuit that is not dependent on the variation of diode-connected transistors. However, because current detection circuits 14A and 14B share diode-connected transistors, crosstalk may occur as a result of the operation of one current detection circuit, which affects the other.
Next, the second embodiment of the application of the present disclosure to a series regulator is described.
In the first embodiment above, hysteresis is applied to the current side to be detected of the current detection circuits 14A and 14B, whereas the regulator in the second embodiment example shown in
The regulator IC shown in
In the regulator IC10 shown in
Among these, the hysteresis circuit 17A′ consists of a transistor Q21, which constitutes a current mirror with a transistor Q1 on the primary side of the current mirror circuit 15b, transistors Qh11 and Qh21, which are also connected to Q1 in a current mirror, current mirror transistors Qh41 and Qh31 connected in series with Qh11 and Qh21, and a switching transistor Qsw1 connected between the common base terminal of Qh41 and Qh31 and the ground point, so that Qsw1 is turned on and off by the output of comparator CMP1.
In the regulator IC10 shown in
Also, when the threshold voltages Vth1 and Vth2 are set to low values, the transistors Qh41 and Qh42 constituting the hysteresis circuits 17A′ and 17B′ may operate in the saturation region, which is the same concern as the hysteresis circuits 17A and 17B in the regulator IC 10 shown in
In the regulator IC 10′ of
In addition, an example regulator IC with countermeasures against the variation of the transistor of the diode connection in the regulator IC 10′ of
In the regulator IC10″ shown in
Again, in this example, as in the example shown in
Also, since the regulator IC of the second embodiment shown in
The above is specific explanation of some aspects of the present disclosure based on embodiments, but the present disclosure is not limited to the aforementioned embodiments. For example, in the above embodiments, a bipolar transistor is used as a transistor that constitutes the internal circuit of the regulator IC 10, but as for the first example of the first embodiment (
In the above-mentioned embodiments, the case of a regulator IC with a two-channel configuration having two output terminals is described, but the number of channels is not limited to two and can be three or more. Especially in the case of three or more channels, the signal indicating that an error has been detected output from the logic circuit 16 may be configured to be output as a signal of two or more bits.
Furthermore, in the regulator IC of the above embodiments, the explanation assumes the case where it is configured as a power supply device for in-vehicle terrestrial digital broadcasting with an antenna connected to the output terminal OUT as a load, but the load is not limited to an antenna and can be applied to a power supply device to which two or more loads with the same current consumption are connected.
In the above embodiments, the case where the present disclosure is applied to a regulator IC that constitutes a linear regulator such as an LDO is described. However, the present disclosure is not limited to regulator ICs, but can also be applied to ICs that constitute switching regulator type DC-DC converters and high-side switch ICs.
According to an aspect of the present disclosure, there is provided a current detection circuit including: a current-to-voltage converter that converts a current to be detected or a reference current into a voltage; a comparator including one input terminal to which a voltage that is current-to-voltage converted by the current-to-voltage converter is input and the other input terminal to which a voltage as a reference for comparison or a voltage converted from the current to be detected is input; and a hysteresis circuit for providing hysteresis to a comparison operation of the comparator, wherein the hysteresis circuit includes: a current source circuit that generates a current of a predetermined magnitude; and a switch connected in series with the current source circuit, and the switch is switched to an on state or an off state by an output of the comparator, thereby a current flowed in the current-to-voltage converter is increased or decreased by an amount of the current of the current source circuit, and the voltage converted from the current to be detected or the voltage converted from the reference current changes and thereby the hysteresis circuit provides hysteresis to the comparison operation of the comparator.
According to the current detection circuit having the above configuration, hysteresis can be provided to the comparison operation of the comparator whose detection target is a current.
According to an aspect of the present disclosure, it is possible to provide a current detection circuit and a power supply semiconductor integrated circuit incorporating the same, which can provide hysteresis to the comparison operation of the comparator whose detection target is a current. There is also an effect that, in a power supply semiconductor integrated circuit having a current detection circuit that detects an open state or a short state of an output terminal using a comparator and composed of bipolar transistors, it is possible to prevent the transistor that constitutes the hysteresis circuit in the current detection circuit from operating in the saturation region.
Although embodiments of the present invention have been described and illustrated in detail, the disclosed embodiments are made for purposes of illustration and example only and not limitation. The scope of the present invention should be interpreted by terms of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-190903 | Nov 2023 | JP | national |
