Patent Application
20230393599
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-092295, filed on Jun. 7, 2022, the entire contents of which are incorporated herein by reference.
The present disclosure relates to a current detection circuit, an overcurrent protection circuit using the same, and a linear power supply.
A current detection circuit that detects a monitoring target current is used for various purposes (e.g., an overcurrent protection circuit that limits an output current flowing through an output transistor to a predetermined upper limit value or less).
However, conventional current detection circuits have room for improvement in terms of detection accuracy thereof.
Some embodiments of the present disclosure provide a current detection circuit with high detection accuracy, an overcurrent protection circuit using the current detection circuit, and a linear power supply.
According to one embodiment of the present disclosure, a current detection circuit includes: a first transistor configured to pass a sense current corresponding to a monitoring target current; a second transistor provided on a path through which the sense current flows, and configured such that a voltage across the second transistor is extracted as a current detection signal; and a third transistor having a control terminal connected to a control terminal of the second transistor, having a higher on-threshold voltage than the second transistor, and configured to drive the second transistor in a linear region.
Other features, elements, steps, advantages, and characteristics will become more apparent from the following detailed description and the accompanying drawings related thereto.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure.
Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, systems, and components have not been described in detail so as not to unnecessarily obscure aspects of the various embodiments.
Referring to
The output transistor M0 is connected between an application terminal of the input voltage Vin and an application terminal of the output voltage Vout. Referring to
The overcurrent protection circuit 10 is connected between the application terminal of the input voltage Vin and the application terminal of the output voltage Vout, and generates an overcurrent protection signal OCP using an output current Tout flowing through the output transistor M0 as a monitoring target current (details will be described later).
The driver 20 controls the driving of the output transistor M0. Referring to
The feedback voltage generation circuit 30 includes resistors 31 and 32 connected in series between an output terminal OUT and a ground terminal, and divides the output voltage Vout to generate a feedback voltage Vfb. The feedback voltage generation circuit 30 may be omitted and the output voltage Vout may be directly inputted to the driver 20.
The reference voltage generation circuit 40 generates a reference voltage Vref that is less affected by the input voltage Vin and the ambient temperature, and outputs the reference voltage Vref to the inverting input terminal (−) of the driver 20.
Next, the overcurrent protection circuit 10 will be described in detail with reference to
The current detection circuit 11 includes a transistor M1 and a sense resistor Rs, and generates a current detection signal Vs according to the output current Tout.
A source of the transistor M1 (e.g., PMOSFET) is connected to the source of the output transistor M0 via the sense resistor Rs. A drain of the transistor M1 is connected to the drain of the output transistor M0. A gate of the transistor M1 is connected to a gate of the output transistor M0 (application terminal of the gate signal G0).
The on-resistance (conductivity) of the transistor M1 connected in this manner is controlled in the same manner as the on-resistance (conductivity) of the output transistor M0. Therefore, a sense current Is (Iout/m where m>1) proportional to the output current Tout flows through the transistor M1. The sense current Is flows from the application terminal of the input voltage Vin to the application terminal of the output voltage Vout via the sense resistor Rs and the transistor M1.
The sense resistor Rs is provided on the path through which the sense current Is flows, and the voltage across the sense resistor Rs is extracted as a current detection signal Vs (=Is×Rs).
The protection signal generation circuit 12 generates an overcurrent protection signal OCP for limiting the output current Tout to an overcurrent upper limit value Iocp or less based on the current detection signal Vs. The overcurrent protection circuit 10 may control the driver 20 according to the overcurrent protection signal OCP, or may directly adjust the gate signal G0.
With such a configuration including the overcurrent protection circuit 10, it is possible to limit the output current Tout even when an abnormality occurs in the load 2 and an excessive output current Tout may flow. Accordingly, it is possible to protect the linear power supply 1 and its peripheral circuits.
Factors that may affect the detection accuracy of the current detection circuit 11 include a variation in pair ratio between the output transistor M0 and the transistor M1, a variation in absolute value of the sense resistor Rs, and a variation in input offset of the protection signal generation circuit 12.
In particular, in view of integration into a semiconductor device, it is general that the absolute value variation is larger than the mismatch variation. That is, it is considered that among the factors described above, the variation in absolute value of the sense resistor Rs greatly affects the detection accuracy of the current detection circuit 11.
In view of the above considerations, various embodiments that can improve the detection accuracy of the current detection circuit 11 are proposed below.
A source of the transistor M2 is connected to the source of the output transistor M0 (the application terminal of the input voltage Vin). A drain of the transistor M2 is connected to the source of the transistor M1. The drain of the transistor M1 is connected to the drain of the output transistor M0 (the application terminal of the output voltage Vout).
A source of the transistor M3 is connected to the source of the output transistor M0. Gates of the transistors M2 and M3 are both connected to a drain of the transistor M3. The drain of the transistor M3 is connected to a first terminal of the current source CS1. A second terminal of the current source CS1 is connected to the ground terminal.
The transistor M1 corresponds to a first transistor configured to pass a sense current Is corresponding to the output current Iout.
The transistor M2 corresponds to a second transistor provided on a path through which the sense current Is flows, and is configured such that the voltage across the transistor (drain-source voltage Vds) is extracted as a current detection signal Vs.
The transistor M3 corresponds to a third transistor having a higher on-threshold voltage Vth [M3] than the transistor M2 and is configured to drive the transistor M2 in a linear region.
Thus, the second transistor and the third transistor constituting the current detection circuit 11 may be provided on the source side of the first transistor. For example, when the second transistor and the third transistor are provided on the source side of the P-channel transistor M1, P-channel transistors M2 and M3 may be used as the second transistor and the third transistor, respectively.
However, the transistor M2 is a PMOSFET having a gate electrode formed of high-concentration P-type polysilicon. In the following description, the transistor M2 may be referred to as “P-gate PMOSFET” to distinguish it from a typical PMOSFET. On the other hand, the transistor M3 is a typical PMOSFET having a gate electrode made of high-concentration N-type polysilicon. That is, the transistors M2 and M3 are both PMOSFETs having the same structure, and the polarities of the gate electrodes thereof are different.
The P-gate PMOSFET is a PMOSFET whose on-threshold voltage Vth is changed by changing the polarity of the gate electrode. A typical PMOSFET has an on-threshold voltage Vth of about 0.7 V. On the other hand, in the P-gate PMOSFET, the on-threshold voltage Vth is about −0.15 V.
The P-gate PMOSFET and the typical PMOSFET have exactly the same device structure, except that the polarities of the gate electrodes are different. Therefore, as long as they are formed on a common silicon substrate, their element characteristics (on-threshold voltage Vth, on-resistance Ron, etc.) vary in the same way.
Further, as described above, the gates of the transistors M2 and M3 are both connected to the drain of the transistor M3. The reference current Tref generated by the current source CS1 flows through the drain of the transistor M3. Therefore, a potential difference corresponding to the on-threshold voltage Vth [M3] (≈0.7 V) of the transistor M3 is generated between the gate and source of the transistor M3.
The on-threshold voltage Vth [M3] of the transistor M3 is much higher than the on-threshold voltage Vth [M2] (≈0.15 V) of the transistor M2. Therefore, the transistor M2 is sufficiently driven in a linear region. In the linear region, the characteristic between the drain and source of the transistor M2 is equivalent to that of a resistor. That is, the current detection signal Vs extracted from between the drain and source of the transistor M2 is proportional to the sense current Is flowing through the transistor M1.
In the linear power supply 1 of the first embodiment, unlike the comparative example (
As shown in
As shown in
As described above, in the linear power supply 1 of the first embodiment, the transistor M2 (P gate PMOSFET) and the transistor M3 (typical PMOSFET) are different only in the polarity of the gate electrode, and the device structures thereof are exactly the same. Therefore, as long as they are formed on a common silicon substrate, the variations in their characteristics (the on-threshold voltages Vth [M2] and Vth [M3], the on-resistances Ron [M2] and Ron [M3], etc.) are the same.
For example, when the on-resistance Ron [M2] of the transistor M2 varies in an increasing direction, the on-threshold voltage Vth [M2], which has a positive correlation with the on-resistance Ron [M2], varies in an increasing direction (see
As described above, according to the linear power supply 1 of the first embodiment, the variation in on-resistance Ron [M2] of the transistor M2 is corrected. Therefore, the variation in the current detection signal Vs is reduced.
Referring to
On the other hand, according to the linear power supply 1 of the first embodiment, due to the correction action of the on-resistance Ron [M2] described above, the drain-source voltage Vds (current detection signal Vs) with respect to the drain current Id (sense current Is) is suppressed to d2 (<d1).
An inverting input terminal (−) of the amplifier A1 is connected to the source of the transistor M2. A non-inverting input terminal (+) of the amplifier A1 is connected to a positive terminal of the voltage source E1. A negative terminal of the voltage source E1 is connected to the drain of the transistor M2. An output terminal of the amplifier A1 is connected to a gate of the transistor M4. A source of the transistor M4 is connected to the application terminal of the input voltage Vin. A drain of the transistor M4 is connected to the output terminal of the driver 20.
The amplifier A1 uses the negative terminal of the voltage source E1 as a reference potential terminal, and generates a gate signal G1 so as to control an on-resistance (conductivity) of the transistor M4 according to a difference (Vofs−Vs) between the offset voltage Vofs (corresponding to the detection threshold value) inputted to the non-inverting input terminal (+) and the current detection signal Vs inputted to the inverting input terminal (−).
When the current detection signal Vs (=Is×Rs) is lower than the offset voltage Vofs, the gate signal G1 outputted from the amplifier A1 stays at a high level. Therefore, the transistor M4 is fully turned off so that the gate and source of the output transistor M0 are open. As a result, the on-resistance of the output transistor M0 is not increased, and the output current Tout flowing through the output transistor M0 is not limited (that is, the overcurrent protection operation is canceled).
On the other hand, when the output current Tout increases due to an output abnormality or the like and the current detection signal Vs becomes higher than the offset voltage Vofs, the gate signal G1 outputted from the amplifier A1 decreases from the high level according to the difference value between the two voltages. Therefore, the transistor M4 is turned on and the drive current Idry (corresponding to the overcurrent protection signal OCP) flows between the gate and source of the output transistor M0, so that the gate signal G0 rises and the gate and source of the output transistor M0 voltage is pulled down. As a result, the on-resistance of the output transistor M0 increases, resulting in a state in which the output current Tout is limited (i.e., a state in which the overcurrent protection operation is activated). Consequently, the gate control of the transistor M4 is balanced in a state in which the current detection signal Vs and the offset voltage Vofs are imaginary-shorted.
Specifically, referring to
Further, the protection signal generation circuit 12 includes an amplifier A2, a voltage source E2, a transistor M5 (e.g., NMOSFET), and transistors M6 and M7 (e.g., PMOSFETs) instead of the amplifier A1, the voltage source E1, and the transistor M4 described above.
The source of the transistor M1 is connected to the source of the output transistor M0 (i.e., the application terminal of the input voltage Vin). The drain of the transistor M1 is connected to a drain of the transistor MT. A source of the transistor MT is connected to the drain of the output transistor M0 (i.e., the application terminal of the output voltage Vout).
A source of the transistor M3′ is connected to the drain of the output transistor M0. Gates of the transistors MT and M3′ are both connected to a drain of the transistor M3′. The drain of the transistor M3′ is connected to a first terminal of the current source CS2. A second end of the current source CS2 is connected to the application terminal of the input voltage Vin.
The transistor M1 corresponds to a first transistor configured to pass a sense current Is corresponding to the output current Tout.
The transistor MT corresponds to a second transistor provided on a path through which the sense current Is flows, and is configured such that the voltage across the transistor (drain-source voltage Vds) is extracted as a current detection signal Vs.
The transistor M3′ has a higher on-threshold voltage Vth [M3′] than the transistor M2′, and corresponds to a third transistor configured to drive the transistor MT in a linear region.
As described above, the second transistor and the third transistor constituting the current detection circuit 11 may be provided on the drain side of the first transistor. For example, when the second transistor and the third transistor are provided on the drain side of the P-channel transistor M1, the N-channel transistors M2′ and M3′ may be used as the second transistor and the third transistor, respectively.
An inverting input terminal (−) of the amplifier A2 is connected to the source of the transistor MT. A non-inverting input terminal (+) of the amplifier A2 is connected to a negative terminal of the voltage source E2. A positive terminal of the voltage source E2 is connected to the drain of the transistor MT. An output terminal of the amplifier A2 is connected to a gate of the transistor M5. A source of the transistor M5 is connected to the application terminal of the output voltage Vout. A drain of the transistor M5 is connected to a drain of the transistor M7.
Sources of the transistors M6 and M7 are both connected to the application terminal of the input voltage Vin. Gates of the transistors M6 and M7 are both connected to the drain of the transistor M7. A drain of the transistor M6 is connected to the output terminal of the driver 20. The transistors M6 and M7 connected in this manner function as a current mirror that mirrors the drain current of the transistor M5 and generates a drive current Idry flowing between the gate and source of the output transistor M0.
The amplifier A2 uses the positive terminal of the voltage source E2 as a reference potential terminal, and generates a gate signal G2 so as to control an on-resistance (conductivity) of the transistor M5 according to a difference (Vs−Vofs) between the offset voltage Vofs (corresponding to the detection threshold value) inputted to the non-inverting input terminal (+) and the current detection signal Vs inputted to the inverting input terminal (−).
When the current detection signal Vs (=Is×Rs) is lower than the offset voltage Vofs, the gate signal G2 outputted from the amplifier A2 stays at a low level. Therefore, the transistor M5 is fully turned off so that the current mirror consisting of the transistors M6 and M7 does not operate and the gate and source of the output transistor M0 are open. As a result, the on-resistance of the output transistor M0 is not increased, and the output current Tout flowing through the output transistor M0 is not limited (that is, the overcurrent protection operation is canceled).
On the other hand, when the output current Tout increases due to an output abnormality or the like and the current detection signal Vs becomes higher than the offset voltage Vofs, the gate signal G2 outputted from the amplifier A2 rises from the low level according to the difference value between the two voltages. Therefore, the transistor M5 is turned on and the drive current Idry (corresponding to the overcurrent protection signal OCP) flows between the gate and source of the output transistor M0, so that the gate signal G0 rises and the gate-source voltage of the output transistor M0 is pulled down. As a result, the on-resistance of the output transistor M0 increases, resulting in a state in which the output current Tout is limited (i.e., a state in which the overcurrent protection operation is activated). Consequently, the gate control of the transistor M5 is balanced in a state in which the current detection signal Vs and the offset voltage Vofs are imaginary-shorted.
However, the transistor MT is an NMOSFET having a gate electrode formed of high-concentration N-type polysilicon. In the following description, the transistor MT may be referred to as an “N-gate NMOSFET” to distinguish it from a typical NMOSFET. On the other hand, the transistor M3′ is a typical NMOSFET having a gate electrode made of high-concentration P-type polysilicon. That is, the transistors MT and M3′ are both NMOSFETs having the same structure, and the polarities of the gate electrodes thereof are different.
The N-gate NMOSFET is an NMOSFET whose on-threshold voltage Vth is changed by changing the polarity of the gate electrode. The typical NMOSFET has an on-threshold voltage Vth of about 0.7 V. On the other hand, in the N-gate NMOSFET, the on-threshold voltage Vth is about −0.15 V.
The N-gate NMOSFET and the typical NMOSFET have exactly the same device structure, except that the polarities of the gate electrodes are different. Therefore, as long as the N-gate NMOSFET and the typical NMOSFET are formed on a common silicon substrate, their element characteristics (on-threshold voltage Vth, on-resistance Ron, etc.) vary in the same way.
Further, as described above, the gates of the transistors MT and M3′ are both connected to the drain of the transistor M3′. The reference current Iref generated by the current source CS2 flows through the drain of the transistor M3′. Therefore, a potential difference corresponding to the on-threshold voltage Vth [M3′] (≈0.7 V) of the transistor M3′ is generated between the gate and source of the transistor M3′.
The on-threshold voltage Vth [M3′] of the transistor M3′ is much higher than the on-threshold voltage Vth [M2′] of the transistor MT (≈0.15V). Therefore, the transistor MT is sufficiently driven in a linear region. In the linear region, the characteristic between the drain and source of the transistor MT is equivalent to that of a resistor. That is, the current detection signal Vs extracted from between the drain and source of the transistor MT is proportional to the sense current Is flowing through the transistor M1.
According to the linear power supply 1 of the third embodiment, there is no need to consider the variations in absolute value of the sense resistor Rs, as in the first embodiment (
However, in the linear power supply 1 of the third embodiment, the overcurrent protection circuit 10 is connected between the application terminal of the input voltage Vin and the application terminal of the output voltage Vout. Therefore, the input/output voltage difference (Vin−Vout) needs to be higher than the on-threshold voltage Vth [M7] of the transistor M7 in order not to interfere with the overcurrent protection operation.
In the linear power supply 1 of the third embodiment, the transistor MT is formed of an N-gate NMOSFET, and the transistor M3′ is formed of a typical NMOSFET. However, the combination of the second transistor and the third transistor is not limited to the above. For example, the transistor MT may be formed of a depletion-mode NMOSFET, and the transistor M3′ may be formed of an enhancement-mode NMOSFET.
Referring to
According to the linear power supply 1 of the fourth embodiment, the circuit size can be reduced as compared with the third embodiment (
However, in the linear power supply 1 of the fourth embodiment, the overcurrent protection circuit 10 is connected between the application terminal of the input voltage Vin and the application terminal of the output voltage Vout, as in the third embodiment (
In addition, the linear power supply 1 of the fourth embodiment is susceptible to the variation in on-threshold voltage and the temperature characteristics of the transistor M5. Therefore, it should be noted that the effect of suppressing the variation in the overcurrent upper limit value Iocp may be smaller than in the third embodiment (
That is, in the linear power supply 1 of the fifth embodiment, the overcurrent protection circuit 10 is connected between the application terminal of the input voltage Vin and the ground terminal. Therefore, unlike the third embodiment (
According to the linear power supply 1 of the sixth embodiment, unlike the fourth embodiment (
Referring to
The transistor M1′ corresponds to a first transistor configured to pass a sense current Is corresponding to the output current Iout.
The transistor M2′ corresponds to a second transistor provided on a path through which the sense current Is flows, and is configured such that the voltage across the transistor (the drain-source voltage Vds) is extracted as a current detection signal Vs.
The transistor M3′ has a higher on-threshold voltage Vth [M3′] than the transistor M2′, and corresponds to a third transistor configured to drive the transistor M2′ in a linear region.
As described above, the second transistor and the third transistor constituting the current detection circuit 11 may be provided on the source side of the first transistor. For example, when the second transistor and the third transistor are provided on the source side of the N-channel transistor M1′, the N-channel transistors M2′ and M3′ may be used as the second transistor and the third transistor, respectively.
Further, in the linear power supply 1 of the seventh embodiment, the input polarity of the driver 20 is reversed due to the above change. Referring to
Furthermore, in the linear power supply 1 of the seventh embodiment, the transistors M6 and M7 are omitted from the constituent elements of the protection signal generation circuit 12. Referring to
When the current detection signal Vs (=Is×Rs) is lower than the offset voltage Vofs, the gate signal G2 outputted from the amplifier A2 stays at a low level. Therefore, the transistor M5 is fully turned off, so that the gate and source of the output transistor M0′ are open. As a result, an on-resistance of the output transistor M0′ is not increased, and the output current Iout flowing through the output transistor M0′ is not limited (that is, the overcurrent protection operation is released).
On the other hand, when the output current Iout increases due to an output abnormality or the like and the current detection signal Vs becomes higher than the offset voltage Vofs, the gate signal G2 outputted from the amplifier A2 rises from the low level according to a difference value between the two voltages. Therefore, the transistor M5 is turned on and the drive current Idrv (corresponding to the overcurrent protection signal OCP) flows between the gate and source of the output transistor M0′, so that the gate signal G0 decreases and the gate-source voltage of the output transistor M0′ is pulled down. As a result, the on-resistance of the output transistor M0′ increases, and the output current Iout is limited (that is, the overcurrent protection operation is activated). Consequently, the gate control of the transistor M5 is balanced in a state in which the current detection signal Vs and the offset voltage Vofs are imaginary-shorted.
Thus, even when the output transistor M0′ and the transistor M1′ are NMOSFETs, it is possible to apply the current detection circuit 11 that does not use the sense resistor Rs. Therefore, it is possible to enhance the detection accuracy of the current detection circuit 11, and hence, it is possible to suppress the variation in the overcurrent upper limit value Iocp.
Specifically, referring to
Further, the protection signal generation circuit 12 includes an amplifier A1, a voltage source E1 and a transistor M4 (e.g., see
The source of the transistor M1′ is connected to the source of the output transistor M0′ (i.e., the application terminal of the output voltage Vout). The drain of the transistor M1′ is connected to the drain of the transistor M2. The source of the transistor M2 is connected to the drain of the output transistor M0′ (i.e., the application terminal of the input voltage Vin). Since the connection relationship between the transistors M2 and M3 and the current source CS1 is the same as that of the second embodiment (
The transistor M1′ corresponds to a first transistor configured to pass a sense current Is corresponding to the output current Iout.
The transistor M2 corresponds to a second transistor provided on a path through which the sense current Is flows, and is configured such that the voltage across the transistor (i.e., the drain-source voltage Vds) is extracted as a current detection signal Vs.
The transistor M3 corresponds to a third transistor having a higher on-threshold voltage Vth [M3] than the transistor M2 and is configured to drive the transistor M2 in a linear region.
As described above, the second transistor and the third transistor constituting the current detection circuit 11 may be provided on the drain side of the first transistor. For example, when the second and third transistors are provided on the drain side of the N-channel transistor Mr, P-channel transistors M2 and M3 may be used as the second and third transistors, respectively.
Since the connection relationship between the amplifier A1, the voltage source E1, and the transistor M4 is the same as that of the second embodiment (
Sources of the transistors M8 and M9 are both connected to the application terminal of the output voltage Vout. Gates of the transistors M8 and M9 are both connected to the drain of the transistor M9. A drain of the transistor M8 is connected to the output terminal of the driver 20. The transistors M8 and M9 connected in this manner function as a current mirror that mirrors the drain current of the transistor M4 to generate a drive current Idry flowing between the gate and source of the output transistor M0′.
When the current detection signal Vs (=Is×Rs) is lower than the offset voltage Vofs, the gate signal G1 outputted from the amplifier A1 stays at a high level. Therefore, the transistor M4 is fully turned off, so that the current mirror consisting of the transistors M8 and M9 does not operate and the gate and source of the output transistor M0′ are open. As a result, the on-resistance of the output transistor M0′ is not increased, and the output current Tout flowing through the output transistor M0′ is not limited (that is, the overcurrent protection operation is released).
On the other hand, when the output current Tout increases due to an output abnormality or the like and the current detection signal Vs becomes higher than the offset voltage Vofs, the gate signal G1 outputted from the amplifier A1 decreases from the high level according to a difference value between the two voltages. Therefore, the transistor M4 is turned on and the drive current Idry (corresponding to the overcurrent protection signal OCP) flows between the gate and source of the output transistor M0′, so that the gate signal G0 is lowered and the gate-source voltage of the output transistor M0′ is pulled down. As a result, the on-resistance of the output transistor M0′ increases, and the output current Tout is limited (that is, the overcurrent protection operation is activated). Consequently, the gate control of the transistor M4 is balanced in a state in which the current detection signal Vs and the offset voltage Vofs are imaginary-shorted.
According to the linear power supply 1 of the eighth embodiment, as in the seventh embodiment (
However, in the linear power supply 1 of the eighth embodiment, the overcurrent protection circuit 10 is connected between the application terminal of the input voltage Vin and the application terminal of the output voltage Vout. Therefore, it should be noted that the input/output voltage difference (Vin−Vout) needs to be higher than the on-threshold voltage Vth [M9] of the transistor M9 in order not to interfere with the overcurrent protection operation.
That is, in the linear power supply 1 of the ninth embodiment, the overcurrent protection circuit 10 is connected between the application terminal of the input voltage Vin and the ground terminal. Therefore, unlike the eighth embodiment (
Referring to
According to the linear power supply 1 of the tenth embodiment, the circuit size can be reduced as compared with the eighth embodiment (
It should be noted that the first to tenth embodiments described so far may be combined as appropriate as long as there is no contradiction. For example, although not described again, by combining the ninth embodiment (
In the following, the various embodiments described above will be comprehensively described.
For example, the current detection circuit disclosed herein includes: a first transistor configured to pass a sense current corresponding to a monitoring target current; a second transistor provided on a path through which the sense current flows, and configured such that a voltage across the second transistor is extracted as a current detection signal; and a third transistor having a control terminal connected to a control terminal of the second transistor, having a higher on-threshold voltage than the second transistor, and configured to drive the second transistor in a linear region (first configuration).
In the current detection circuit of the first configuration, the second transistor and the third transistor may be MOSFETs of the same structure, and may have gate electrodes with different polarities (second configuration).
In the current detection circuit of the second configuration, the second transistor may be a PMOSFET having a gate electrode made of P-type polysilicon, and the third transistor may be a PMOSFET having a gate electrode made of N-type polysilicon (third configuration).
In the current detection circuit of the second configuration, the second transistor may be an NMOSFET having a gate electrode made of N-type polysilicon, and the third transistor may be an NMOSFET having a gate electrode made of P-type polysilicon (fourth configuration).
In the current detection circuit of the first configuration, the second transistor may be a depletion type NMOSFET, and the third transistor may be an enhancement type NMOSFET (fifth configuration).
Further, for example, the overcurrent protection circuit disclosed herein includes: the current detection circuit of any one of the first to fifth configurations; and a protection signal generation circuit configured to generate an overcurrent protection signal for limiting the monitoring target current to an upper limit value or less based on the current detection signal (sixth configuration).
In the overcurrent protection circuit of the sixth configuration, the protection signal generation circuit may include an amplifier configured to generate the overcurrent protection signal according to a difference between the current detection signal and a detection threshold value (seventh configuration).
In the overcurrent protection circuit of the sixth configuration, the protection signal generation circuit may include a transistor configured to generate the overcurrent protection signal in response to the current detection signal applied between a gate and a source (eighth configuration).
Further, for example, the linear power supply disclosed herein includes: an output transistor configured to be connected between an application terminal of an input voltage and an application terminal of an output voltage; a driver configured to drive the output transistor such that the output voltage or a feedback voltage corresponding to the output voltage matches a reference voltage; and the overcurrent protection circuit of any one of the sixth to eighth configurations configured to use an output current flowing through the output transistor as the monitoring target current (ninth configuration).
In the linear power supply of the ninth configuration, the overcurrent protection circuit may be connected between the application terminal of the input voltage and the application terminal of the output voltage (tenth configuration).
In the linear power supply of the ninth configuration, the overcurrent protection circuit may be connected between the application terminal of the input voltage and a ground terminal (eleventh configuration).
It should be noted that the various technical features disclosed herein may be modified in various ways in addition to the above-described embodiments without departing from the gist of the technical concept. That is, the above-described embodiments should be considered as examples and not limitative in all respects. It should be understood that the technical scope of the present disclosure is defined by the claims and all changes falling within the meaning and range of equivalents of the claims are included in the technical scope of the present disclosure.
According to the present disclosure in some embodiments, it is possible to provide a current detection circuit with high detection accuracy, an overcurrent protection circuit using the current detection circuit, and a linear power supply.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-092295 | Jun 2022 | JP | national |
