Patent Application
20120113087
1. Technical Field
This disclosure relates to the field of semiconductor devices and fabrication.
2. Description of the Related Art
Active matrix backplanes that are used to control light emitting diode (LED) pixels of display devices, for example, oftentimes involve driving and/or sensing currents. Since these backplanes typically incorporate thin film transistors (TFTs), routing of the driving and/or sensing currents usually requires electrical connections between the sources and drains of some TFTs with the gates of others. Notably, since the sources and drains are often located on different metal layers than the metal layer on which the gates are located, vias (electrical connections formed through the layers) are conventionally used to facilitate the routing of the currents. Unfortunately, vias tend to increase production costs as their formation typically involves dedicated processing steps requiring relatively high precision.
Many aspects of the disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.
Pixel circuits and related methods are provided, several exemplary embodiments of which will be described in detail. In some embodiments, a pixel circuit is provided that uses capacitive coupling to provide a persistent current for driving an emissive load in contrast to using a via. The use of capacitive coupling allows the pixel circuit to avoid the need for a via and, as such, efficiencies in fabrication may be achieved. Since the pixel circuit does not require a via, fabrication can be accomplished using, for example, a Self-Aligned Imprint Lithography (SAIL) process that can utilize roll-to-roll (R2R) manufacturing. For more information on SAIL processes, please refer to U.S. Pat. No. 7,202,719, for example, which is incorporated by reference herein. Notably, as used herein, the term “persistent current” refers to a substantially constant current (such as can be used for driving and/or sensing) provided between data updates to a pixel.
In this regard, reference is made to
TFT T1 is conductively coupled to a data line 104 and to a select line 106. Specifically, data line 104 is conductively coupled to drain electrode (D) of TFT T1, and select line 106 is conductively coupled to gate electrode (G) of TFT T1. The source electrode (S) of TFT T1 is conductively coupled to electrodes 107, 108 of capacitors C1 and C2, respectively.
TFT T2 is capacitively coupled to TFT T1. In this embodiment, the capacitive coupling is facilitated by electrode 109 of capacitor C1 being conductively coupled to gate electrode (G) of TFT T2, and electrode 110 of capacitor C2 being conductively coupled to source electrode (S) of TFT T2. Capacitor C2 of this embodiment includes an electrically floating electrode 112. Notably, use of a floating electrode configuration positions both terminals (i.e., electrodes 108 and 110) at the top metal layer, which constitutes source/drain material. In contrast, for a typical non-floating electrode configuration, a via would likely be used to conductively couple a terminal of the capacitor to the bottom metal layer. This is because such a non-floating electrode configuration would conventionally use the gate dielectric as the capacitor dielectric.
Additionally, drain electrode (D) of TFT T2 is conductively coupled to Vdd, and source electrode (S) of TFT T2 is conductively coupled to emissive load 102. Notably, circuit 100 lacks a via for electrically connecting a data signal, which is provided by data line 104, to TFT T2.
In operation, emissive load 102 is driven responsive to the data signal and the select signal provided by the data and select lines, respectively. Specifically, at each frame cycle, data is transferred to the circuit by the data line to TFT T1 as enabled by a select signal provided during an active mode of the select line. Notably, the select line selectively exhibits either an active or inactive mode, with the active mode for this embodiment for the frame cycle time divided by the number of gate lines.
Responsive to the select signal, the transferred data is stored by capacitor C2, which functions as a hold capacitor. The hold capacitor C2 drives TFT T2, which provides a persistent current to the emissive load. Notably, this is accomplished without a conductive coupling for controlling TFT T2, i.e., TFT T2 is controlled through capacitive coupling.
As shown in
In addition to the gate layer, portion 211 of capacitor C2 includes a gate dielectric layer 216A, an amorphous silicon layer 218A, a doped (N+) microcrystalline silicon layer 220A and a metal layer 222A, which functions as an electrode (e.g., electrode 108 of
It should be noted that, in some embodiments, as the voltage at the bottom of the capacitor (e.g., gate layer 214) is increased relative to the top (e.g., metal layer 222), charge accumulates at the semiconductor dielectric interface (i.e., the interface between layers 218 and 220) resulting in increased capacitance, which should not have a significant effect on operation. Additionally, a leaky or shorted dielectric on the driven side of the device (i.e., between electrode 107 of capacitor C1 and gate (G) of TFT T2) could improve device performance by functioning as a conductive coupling.
Although particular families of materials may have been set forth above for forming the layers, various materials may be used. In this regard, conductive layers can be metals. Commonly used metals, include, but are not limited to, Al, Mo, Cr, Cu, Ti, Ni. Additionally, since conductors are often required to be transparent in display applications, conductive oxides such as ITO (Indium Tin Oxide) and doped zinc oxide, for example, can be used. Alternatively, pixel electrodes are sometimes made from organic materials such as PEDOT (Polyethylenedioxythiophene), for example.
Semiconductors can be inorganic (e.g., amorphous silicon or polysilicon) or can be transition metal oxides (e.g., zinc indium oxide, zinc tin oxide, indium gallium zinc oxide). Organic semiconductors can be either small molecules (e.g., pentacene) or polymers (e.g., polyacetylene).
Dielectrics can also be organic or inorganic. Examples of the latter are silicon nitride and silicon dioxide as well as other oxides and nitrides such as hafnium oxide. Organic dielectrics are often very particular to the organic semiconductor they are paired with. For instance, benzocyclobutane is often used with pentacene.
Equations for predicting the voltages, charges and capacitances for the electrodes of capacitor C2 are presented below, in which it is assumed that ideal dielectrics (i.e., dielectrics exhibiting no leakage and no charge trapping) are used under DC conditions. In the equations:
Vm/V=(A1/A2)/((A1/A2)+(d1/d2));
CΔ=q/V=ε(A1A2)/((d1A2)+(d2A1));
Therefore, for constant total area A=A1+A2 and d1=d2,
dC/dA
1=(ε/Ad)(A−2A1), and
C is maximum at A1=A/2. That is, for a fixed area, the maximum capacitance is predicted when the area of the dielectric is the same on both sides of the floating electrode 112 of capacitor C2. Additionally, maximum voltage transfer to the gate (G) of TFT T2 occurs when the area of the dielectric on the opposite side of the floating electrode from TFT T2 is much larger than the area of the gate dielectric.
In addition to the gate layer, gate (G) of TFT T2 includes a gate dielectric layer 216C, an amorphous silicon layer 218C, a doped (N+) microcrystalline silicon layer 220C and a metal layer 222C. Metal layer 222C functions as the gate electrode of TFT T2.
Source (S) and drain (D) share gate dielectric layer 216D and amorphous silicon layer 218D, above which the source and drain are separated by a gap 227. Above amorphous silicon layer 218D, the source includes a doped (N+) microcrystalline silicon layer 220D and a metal layer 222D, which functions as the source electrode, whereas the drain includes a doped (N+) microcrystalline silicon layer 220E and a metal layer 222E. Metal layer 222E functions as the drain electrode of TFT T2.
It should be noted that the vertical symmetry exhibited by the material layers of the capacitor and TFT lends itself well to fabrication by a SAIL process, a representative example of which will be described in more detail with respect to
In this regard,
In
In block 254 (
By way of example,
As depicted in block 258 of
It should be noted that in a SAIL process, a stack of thin films is typically deposited before any patterning is performed. This results in each layer being substantially planar and parallel with other layers of the stack. In contrast, with conventional thin film processing (e.g., photolithography), the layers are deposited on top of previously patterned layers, which can lead to step coverage problems and non-uniform film thicknesses and electrical stress concentrations. Notably, by providing a SAIL fabrication without using vias, at least one masking step and one etching step are eliminated compared to conventional photolithographic fabrication techniques.
Additionally, by utilizing a SAIL process, such as the embodiment described above, for example, the problem of multiple alignments on flexible (mechanically unstable) substrates can be addresses. Notably, plastic substrates are known to exhibit process induced distortions on the order of 1000 ppm. These distortions can lead to significant alignments on large area backplanes. SAIL addresses this issue by performing potentially all of the masking steps in a single imprint. In some embodiments, the 3D imprinted mask distorts with the substrate to maintain alignment regardless of process induced distortion.
TFT T1A is conductively coupled to a data line 304 and to a select line 306. Specifically, data line 304 is conductively coupled to drain electrode (D) of TFT T1A, and select line 106 is conductively coupled to gate electrode (G) of TFT T1A. The source electrode (S) of TFT T1A is conductively coupled to electrodes 307, 308 of capacitors C1A and C2A, respectively.
TFT T2A is capacitively coupled to TFT T1A. In this embodiment, the capacitive coupling is facilitated by electrode 309 of capacitor C1A being conductively coupled to gate electrode (G) of TFT T2A, and electrode 310 of capacitor C2A being conductively coupled to a capacitor communication line 312. Notably, circuit 300 lacks a via for electrically connecting a data signal, which is provided by data line 304, to TFT T2.
In operation, emissive load 302 is driven responsive to the data signal and the select signal provided by the data and select lines, respectively. Specifically, during the programming phase of each frame cycle, data is transferred to the circuit by the data line as enabled by the select signal to TFT T1. The transferred data is stored by capacitor C2, which functions as a hold capacitor.
By connecting the bottom electrode 310 of the C2 capacitor directly to a separate bus line (312), the capacitance of C2 can be made 4 times larger for the same plan area (thickness divided by two, area increased by a factor of two). Also, capacitor communication line 312 can be toggled negative immediately prior to programming to mitigate bias induced threshold shift.
It should be emphasized that the above-described embodiments are merely possible examples of implementations set forth for a clear understanding of the principles of this disclosure. Many variations and modifications may be made to the above-described embodiments without departing substantially from the spirit and principles of the disclosure. Notably, various circuit configurations other than those depicted can be used in other embodiments, such as by varying component connectivity. By way of example, the power (Vdd) and emissive loads could be either cathode- or anode-connected, for example. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the accompanying claims.
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/US09/47775 | 6/18/2009 | WO | 00 | 12/12/2011 |
