BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to providing frequency compensation, and more particularly, to a feedback-controlled system (e.g., an LDO voltage regulator) using a current generating apparatus capable of minimizing the DC offset of an output current used for frequency compensation.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a first conventional LDO (low dropout) voltage regulator 10. The LDO voltage regulator 10 comprises a pass transistor MP, a feedback voltage divider 11, and an error amplifier 12. The connections between the pass transistor MP, the feedback voltage divider 11, and the error amplifier 12 are shown in FIG. 1. The input terminal Nin of the LDO voltage regulator 10 is coupled to a supply voltage VDD. The output terminal Nout of the LDO voltage regulator 10 is coupled to a loading stage, which is equivalent to a resistor RL connected with a capacitor CL in parallel. Please note that the terminal Ng has a parasitic resistor RPAR and a parasitic capacitor CPAR, where the capacitor CL has an equivalent series resistance of RESR connected to the capacitor CL. Accordingly, it is well-known that there are two low-frequency poles that need to be taken into account when determining the closed-loop transfer function of the frequency response of the LDO voltage regulator 10. In order to guarantee the phase margin of the LDO voltage regulator 10 will be greater than 45 degrees, a zero is introduced to compensate the phase contribution of the two low-frequency poles. Normally, the series combination of the capacitor CL and the equivalent series resistance RESR generates a zero ωESR that provides the LDO voltage regulator 10 with proper phase margin. However, in some conditions, the equivalent series resistance RESR fails to provide proper phase margin for the LDO voltage regulator 10. Please refer to FIG. 2. FIG. 2 is a frequency response diagram of the LDO voltage regulator 10 with various load currents IL at fixed ωESR. For brevity, three Bode plots 21, 22, and 23 are shown in FIG. 2, which correspond, respectively, to light load current, proper load current, and heavy load current of the LDO voltage regulator 10. Furthermore, there are three poles and one zero for each of the Bode plots 21, 22, and 23, in which the first pole ωp1 is mainly concentrated at the output terminal Nout, the second pole ωp2 is mainly concentrated at the terminal Ng of the transistor MP, and the zero is ωESR. When the load current IL varies from the heavy load status to the light load status, the first pole ωp1 decreases roughly and the second pole ωp2 decreases as well, as shown in the Bode plots 21, 22, and 23 of FIG. 2. Furthermore, three of the Bode plots 21, 22, and 23 have poor phase margin in this case. There are at least three drawbacks by utilizing the zero ωESR to compensate the pole of the LDO voltage regulator 10. Firstly, the high-frequency bypass capacitor Cgdpass placed in parallel with the capacitor CL provides another pole with the zero ωESR of the capacitor CL, in which the new pole will further decrease the phase margin of the LDO voltage regulator 10. Secondly, the equivalent series resistance of RESR of the capacitor CL is not properly specified in many cases and varies with temperature. As a result, the zero ωESR cannot be predicted easily. Thirdly, owing to some advantages of ceramic capacitors, such as low RESR, less expense, and compact printed circuit boards, using the ceramic capacitor is becoming more popular. However, it is hard to generate a proper zero ωESR with the low RESR.
Besides utilizing the zero ωESR to compensate the pole of the LDO voltage regulator 10, there are various other frequency compensation means taught in the prior art. Please refer to FIG. 3. FIG. 3 is a diagram illustrating a second conventional LDO voltage regulator 30 having a prior art frequency compensation implemented therein. The LDO voltage regulator 30 shown in FIG. 3 is equivalent to applying the prior art frequency compensation to the LDO voltage regulator 10. The frequency compensation method of FIG. 3 is to provide a feedback path for the output voltage Vout through an additional capacitor CF, and the connection is shown in FIG. 3. The capacitor CF provides a high-frequency bypass path for the loop gain of the LDO voltage regulator 10. Then a pole-zero pair (ωp, ωz) is generated, which is represented by the following equation (1) and equation (2),
ωz=1/(RF1*CF), (1)
ωp=(1+(RF1/RF2))/(RF1*CF) (2)
According to this prior art circuit configuration, due to the fact that the resistance magnitudes of feedback resistors RF1 and RF2 have the same order, the pole ωp and the zero ωz are not far from each other as shown in FIG. 4. FIG. 4 is a diagram illustrating the frequency response of capacitive feedback frequency compensation of FIG. 3. The curve 41 represents the transferring characteristic of the frequency compensation of FIG. 3, and the curve 42 represents the phase variation of the frequency compensation of FIG. 3. Accordingly, the zero ωz contributes less phase margin for the frequency compensation of FIG. 3.
According to the reference of Chaitanya K. Chaya, and Jose Silva-Martinez, “A Frequency Compensation Scheme for LDO Voltage Regulators”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I. REGULAR PAPERS, VOL. 51, NO. 6, Jun. 2004, an improved prior art frequency compensation developed from the frequency compensation of FIG. 3 is proposed. Please refer to FIG. 5. FIG. 5 is a diagram illustrating a third conventional LDO voltage regulator 50 having another prior art frequency compensation implemented therein. The LDO voltage regulator 50 shown in FIG. 5 is equivalent to applying the improved prior art frequency compensation to the LDO voltage regulator 10. The frequency compensation of FIG. 5 is implemented using a frequency-dependent voltage-controlled current source (VCCS) 52 connected at the feedback terminal NFB of the LDO voltage regulator 50. The frequency-dependent VCCS 52 is capable of eliminating the pole ωp of FIG. 3 and generate a new zero ωz0. The new zero ωz0 is determined by the following equation:
ωz0=1/(N*RF1*CF). (3)
Therefore, the location of the new zero ωz0 can be easily adjusted by modifying the current mirror ratio N set to the current mirrors 54a, 54b or modifying the capacitance of the ground capacitor C1 of the FIG. 6. FIG. 6 is a diagram illustrating the frequency-dependent voltage-controlled current source 52 shown in FIG. 5. However, the mismatch of the current mirror 54a and the current mirror 54b, both having the same current mirror ratio N, induces a DC current ΔIB flowing into the feedback resistors RF1, RF2, and equivalently forms a mismatch resistor Rmismatch parallel with the feedback resistors RF1, RF2 as shown in FIG. 6. Hence, the output voltage Vout varies due to the mismatch resistor Rmismatch from the imbalanced current mirrors 54a, 54b. Furthermore, the mismatch of current mirrors 54a, 54b contributes considerable yield loss for chip mass production. In addition, the mismatch current ΔIB is in proportion to the current mirror ratio N of current mirrors 54a, 54b. Furthermore, as the output voltage Vout changes, the mismatch current ΔIB changes accordingly. In order to decrease the effect of the mismatch current ΔIB, the current mirror ratio N of the current mirrors 54a, 54b should preferably be lower, and the capacitance of the grounded capacitor C1 should preferably be larger. However, the larger the capacitance, the higher the production cost and chip area becomes.
SUMMARY OF THE INVENTION
Therefore, one of the objectives of the present invention is to provide a feedback-controlled system (e.g. an LDO voltage regulator) using a current generating apparatus capable of minimizing the DC offset of an output current used for frequency compensation.
According to an embodiment of the present invention, a current generating apparatus is disclosed for generating an output current. The current generating apparatus comprises: a first current mirror, a first bias current generator, a second current mirror, a second bias current generator, a third current source, a feedback circuit, and a fourth current source. The first current mirror generates a first mirror current according to a first bias current and a current mirror ratio. The first bias current generator is coupled to the first current mirror for providing the first bias current according to a first current and a reference current, and the first bias current generator comprises: a first current source biased by a first bias voltage for providing the first current; and a capacitive device coupled to the first current source in parallel for conducting the reference current. The second current mirror generates a second mirror current according to a second bias current and the current mirror ratio. The second bias current generator is coupled to the second current mirror, and the second bias current generator has a second current source biased by the first bias voltage for generating a second current serving as the second bias current. The third current source is coupled to an output node of the second current mirror, and is biased by a second bias voltage to provide a third current, wherein the second mirror current is equal to the third current. The feedback circuit is coupled to the output node of the second current mirror and the third current source for tuning the second bias voltage according to a voltage level at the output node of the second current mirror and a target voltage level. The fourth current source is coupled to an output node of the first current mirror, and is biased by the second bias voltage to provide a fourth current, wherein the output current is outputted at the output node of the first current mirror.
According to an embodiment of the present invention, a feedback-controlled system is disclosed. The feedback-controlled system comprises: a plurality of operational stages cascaded in a closed loop; and a current generating apparatus. The current generating apparatus generates an output current to an output of a first operational stage in the operational stages. The current generating apparatus comprises: a first current mirror, a first bias current generator, a second current mirror, a second bias current generator, a third current source, a feedback circuit, and a fourth current source. The first current mirror generates a first mirror current according to a first bias current and a current mirror ratio. The first bias current generator is coupled to the first current mirror for receiving an output of a second operational stage in the operational stages and providing the first bias current according to a first current and a reference current. The first bias current generator comprises: a first current source for providing the first current according to a first bias voltage and the output of the second operational stage; and a capacitive device coupled to the first current source in parallel for conducting the reference current. The second current mirror generates a second mirror current according to a second bias current and the current mirror ratio. The second bias current generator is coupled to the second current mirror, and the second bias current generator has a second current source for generating a second current serving as the second bias current according to the first bias voltage and the output of the second operational stage. The third current source is coupled to an output node of the second current mirror, and is biased by a second bias voltage to provide a third current, wherein the second mirror current is equal to the third mirror current. The feedback circuit is coupled to the output node of the second current mirror and the third current source for tuning the second bias voltage according to a voltage level at the output node of the second current mirror and a target voltage level. The fourth current source is coupled to an output node of the first current mirror, and is biased by the second bias voltage to provide a fourth current, wherein the output current is outputted from the output node of the first current mirror.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram illustrating a prior art LDO voltage regulator.
FIG. 2 is a frequency response diagram of the LDO voltage regulator.
FIG. 3 is a diagram illustrating a frequency compensation according to the prior art utilized in the LDO voltage regulator of FIG. 1.
FIG. 4 is a diagram illustrating the frequency response of the capacitive feedback frequency compensation of FIG. 3.
FIG. 5 is a diagram illustrating the prior art frequency compensation that improves on the frequency compensation of FIG. 3.
FIG. 6 is a diagram illustrating the prior art frequency-dependent voltage-controlled current source of FIG. 5.
FIG. 7 is a diagram illustrating a voltage regulator according to an embodiment of the present invention.
FIG. 8 is a diagram illustrating the voltage-controlled current source in the voltage regulator of FIG. 7.
FIG. 9 is a diagram illustrating an equivalent schematic of the voltage-controlled current source in the voltage regulator of FIG. 7.
FIG. 10 is a diagram illustrating the frequency response of the voltage regulator of FIG. 7.
FIG. 11 is a diagram of a feedback-controlled system according to a second embodiment of the present invention.
DETAILED DESCRIPTION
Please refer to FIG. 7. FIG. 7 is a diagram illustrating a voltage regulator 100 according to an embodiment of the present invention. The voltage regulator 100 is a low dropout (LDO) voltage regulator that can track the loading current of the voltage regulator 100 to adjust the zero of the voltage regulator 100. The voltage regulator 100 comprises a pass transistor Mp, a voltage divider 101, an error amplifier 102, a loading sensing circuit 103, and a voltage-controlled current source (VCCS) 104. The pass transistor Mp, which is a PMOS transistor, has a source terminal Nin coupled to a supply voltage Vdd and a drain terminal Nout for outputting an output voltage Vout. The voltage divider 101 comprises two feedback resistors RF1 and RF2, connected in series, where the feedback resistor RF1 has a terminal coupled to the drain terminal Nout and another terminal coupled to the feedback resistor RF2. The voltage divider 101 is utilized for providing a feedback voltage level VFB according to the output voltage Vout passed by the pass transistor Mp. The error amplifier 102 has a first input node (i.e. a non-inverting node) N+ coupled to the voltage divider 101 for receiving the feedback voltage level VFB, a second input node (i.e. an inverting node) N− coupled to the target voltage level Vref, and an output node Ng coupled to a gate terminal of the pass transistor Mp. The voltage-controlled current source 104 is coupled to the voltage divider 101 (i.e. the first input node N+) for generating an output current Iac at the first input node N+ of the error amplifier 102, in which the output current Iac is a voltage-controlled AC current. The loading sensing circuit 103 is coupled to the voltage-controlled current source 104 and the gate terminal Ng (i.e. the output node) of the pass transistor MP, for sensing the loading current ILoad variation of the voltage regulator 100 to adjust the output current Iac of the voltage-controlled current source 104. Furthermore, the drain terminal Nout is coupled to a loading circuit, which is equivalent to a loading resistor RL connected with a loading capacitor CL in parallel. Please note that the loading capacitor CL has an equivalent series resistance of RESR connected with the loading capacitor CL. The output node Ng is connected to a parasitic resistor RPAR and a parasitic capacitor CPAR in parallel.
Please refer to FIG. 8. FIG. 8 is a diagram illustrating the voltage-controlled current source 104 in the voltage regulator 100 of FIG. 7. The voltage-controlled current source 104 comprises a first current mirror 1041, a first bias current generator 1042, a second current mirror 1043, a second bias current generator 1044, a third current source 1045, a feedback circuit 1046, and a fourth current source 1047. The first current mirror 1041 generates a first mirror current IM1 according to a first bias current IB1 and a current mirror ratio N. The first bias current generator 1042 is coupled to the first current mirror 1041 for providing the first bias current IB1 according to a first current IB and a reference current Iac1. In this embodiment, the first bias current IB1 is a sum of the first current IB and the reference current Iac1. The first bias current generator 1042 comprises a first current source, which is implemented using a transistor M1, having a gate terminal Ng1 biased by a first bias voltage VB1 for generating the first bias current IB1; and a capacitive device C1 coupled to the drain terminal Nd1 of the transistor M1 in parallel for conducting the reference current Iac1. Therefore, the reference current Iac1 is equal to s*C1*Vout, where the symbol s represents jω. The second current mirror 1043 generates a second mirror current IM2 according to a second bias current IB2 and the current mirror ratio N. The second bias current generator 1044 is coupled to the second current mirror 1043 and has a second current source, which is implemented using a transistor M2 having a gate terminal Ng2 biased by the first bias voltage VB1 for generating a second current IB2 serving as the second bias current. In this embodiment, the transistors M1 and M2 have the same configuration and are biased by the same bias voltage VB1, thus the first current IB1 is equal to the second current IB2. The third current source 1045, which is implemented using a transistor M3, has a drain terminal Nd3 coupled to an output node of the second current mirror 1043 and the gate terminal Ng3 biased by a second bias voltage VB2 for providing a third current ID3, wherein the second mirror current 1043 is equal to the third current ID3. The feedback circuit 1046 is coupled to the output node Nd3 of the second current mirror 1043 and the third current source 1045, for tuning the second bias voltage VB2 according to the target voltage level Vref of the voltage regulator 100 and the voltage Vd3 at the output node Nd3 of the second current mirror 1043. The fourth current source 1047, which is implemented using a transistor M4 has a drain terminal coupled to the output node Nd4 of the first current mirror 1041 and the gate terminal Ng4 biased by the second bias voltage VB2 for providing a fourth current ID4. Furthermore, the output current Iac is outputted at the output node of the first current mirror 1041, which is the first input node N+ of the error amplifier 102.
The first bias current generator 1042 further comprises a transistor M5 having a drain terminal Nd5 coupled to the first current mirror 1041, a source terminal coupled to the drain terminal Nd1 of the transistor M1 and a gate terminal Ng5; and a first error amplifier OP1 having a first input node NOP1+ coupled to the output voltage Vout of the voltage regulator 100, a second input node NOP1− coupled to the source terminal of the transistor M5, and an output node coupled to the gate terminal Ng5 of the transistor M5. In addition, the second bias current generator 1044 further comprises a transistor M6 having a drain terminal Nd6 coupled to the second current mirror 1043, a source terminal coupled to a drain terminal Nd2 of the transistor M2, and a gate terminal Ng6; and a second error amplifier OP2 having a first input node NOP2+ coupled to the output voltage Vout of the voltage regulator 100, a second input node NOP2− coupled to the source terminal of the transistor M6, and an output node coupled to the gate terminal Nd6 of the transistor M6. Please note that, in this embodiment, the circuit configuration of the transistor M5 and the first error amplifier OP1 is symmetric to that of the transistor M6 and the second error amplifier OP2. As shown in FIG. 8, the feedback circuit 1046 comprises a third error amplifier OP3 having a first input node NOP3+ coupled to the drain terminal Nd3 of the transistor M3, a second input node NOP3− coupled to the target voltage level Vref, and an output node coupled to the gate terminal Ng3 of the transistor M3. The detailed operation of the voltage-controlled current source 104 is illustrated as below.
Please refer to FIG. 7 in conjunction with FIG. 8. Due to the mirroring imperfection between the first bias current IB1 and the first mirror current IM1 of the first current mirror 1041, the first current mirror 1041 mirrors the first bias current IB1 according to the current mirror ratio N to introduce the mismatch current to the first mirror current IM1, i.e. IM1=N*IB1=N*IB+N*Iac1+ΔIB1, where ΔIB1 is the mismatch current induced by the first current mirror 1041. Similarly, due to the mirroring imperfection between the second bias current IB2 and the second mirror current IM2 of the second current mirror 1043, the second current mirror 1043 mirrors the second bias current IB2 according to the current mirror ratio N to introduce the mismatch current to the second mirror current IM2, i.e. IM2=N*IB2+ΔIB2, where ΔIB2 is the mismatch current induced by the second current mirror 1043. Please note that, since the second current mirror 1043 is a replica of the first current mirror 1041 in this embodiment (i.e. both have the same current mirror ratio N), the mismatch current ΔIB1 is substantially equal to the mismatch current ΔIB2, i.e. ΔIB1=ΔIB2. Additionally, the first error amplifier OP1 is operative to lock the voltage level at the drain terminal Nd2 to the output voltage Vout, and the first error amplifier OP1 is also operative to lock the voltage level at the drain terminal Nd2 to the output voltage Vout. As shown in FIG. 8, the transistors M1 and M2 are both biased by the same bias voltage VB1. As a result, the first current IB1 is substantially the same as the second current IB2 because of the same bias condition applied to the transistors M1 and M2.
On the other hand, the feedback circuit 1046, acting as a common mode feedback circuit of the transistors M3, is utilized to make the voltage Vd3 approach to the target voltage level Vref of the voltage regulator 100 by controlling the transistor M3. Furthermore, the feedback voltage level VFB at the output node Nd4 also approaches to the target voltage level Vref of the voltage regulator 100 because of the error amplifier 102. Therefore, both of the transistors M3 and M4 are operated under substantially identical bias condition. In this way, as the feedback voltage VFB and the drain voltage Vd3 are both equal to the target voltage Vref with the help of the error amplifier 102 and the third error amplifier OP3, the third current ID3 of the transistor M3 is sure to coincide with the fourth current ID4 of the transistor M4, i.e. ID3=ID4=N*IB2+ΔIB2. Accordingly, referring to Kirchhoff's Laws, the output current Iac can be obtained by subtracting the fourth current ID4 from the first mirror current IM1 (i.e. IM1=N*IB+N*Iac1+ΔIB1), which is the AC current of N*Iac1 (i.e. N*s*C1*Vout). Compared with the prior art, the voltage-controlled current source (i.e. the output current Iac) of N*s*C1*Vout with no mismatch current ΔIB can be obtained, ideally. In a real application, the induced mismatch current ΔIB is very small, and can be neglected.
Please refer to FIG. 9. FIG. 9 is a diagram illustrating an equivalent schematic of the voltage-controlled current source 104 in the voltage regulator 100 of FIG. 7. Therefore, as one can see, the voltage-controlled current source 104 provides an ideal frequency-dependent voltage-controlled current source, where Rmismatch approaches to ∞.
Please refer to FIG. 7 again. In order to obtain a good phase margin for all loading current ILoad of the voltage regulator 100 of FIG. 7, a location of zero ωESR of the voltage regulator 100 should be adjustable with the loading current ILoad. In other words, the zero ωESR is higher for heavy loading current ILoad (i.e. small load impedance) and lower for light loading current ILoad (i.e. high load impedance) as shown in FIG. 10. FIG. 10 is a diagram illustrating the frequency response of the voltage regulator 100 of FIG. 7. By applying the voltage-controlled current source 104 to compensate the pole of the voltage regulator 100, the zero ωESR is directly tuned by modifying the current mirror ratio N of the first current mirror 1041 and the second current mirror 1043 according to the loading current ILoad monitored by the loading sensing circuit 103. According to the aforementioned equation (3), the zero ωESR of the voltage regulator 100 can be modified as below:
ωESR=1/(N*RF1*CF). (4)
In this embodiment, the loading sensing circuit 103 of the present invention is configured to sense the voltage level at the gate terminal Ng (i.e. the output node) of the pass transistor MP to detect the loading current variation. Then the loading sensing circuit 103 changes the current mirror ratio N of the first current mirror 1041 and the second current mirror 1043 to modify the zero ωESR according to the above equation (4). Therefore, as shown in FIG. 10, a good phase margin can be obtained as compared with the prior art. Please note that, the loading sensing circuit 103 of the present invention is not limited to sensing the voltage level at the gate terminal Ng of the pass transistor MP to detect the loading current variation. That is, any other terminal voltage of the voltage regulator 100 that can be referred to for tracking the loading current ILoad also can be adopted. These alternative designs all fall in the scope of the present invention. In addition, any conventional means of changing the current mirror ratio N of the first current mirror 1041 and the second current mirror 1043 can be utilized in the present invention. Since the technique of tuning the current mirror ratio is well known to those skilled in this art, further description is omitted here for brevity.
Please refer to FIG. 11. FIG. 11 is a diagram a feedback-controlled system 200 according an embodiment of the present invention. The feedback-controlled system 200 comprises a plurality of operational stages 2011, . . . , 201x cascaded in a closed loop. In addition, a current generating apparatus 202 is implemented and coupled to the operational stages 201n+m. Each of the operational stages 2011, . . . , 201x has a transfer function of A1, . . . , Ax, respectively. The current generating apparatus 202 has a control terminal Nc coupled to an output of an nth operational stage 201n and an output terminal No coupled to an output of a (n+m)th operational stage 201n+m in the operational stages. The current generating apparatus 202 generates an output current Vn*N*s*C1 to an output of the (n+m)th operational stage 201n+m in the operational stages. Please note that, in this embodiment the current generating apparatus 202 is implemented using the above-mentioned voltage-controlled current source 104 shown in FIG. 8, therefore the detailed description is omitted here for brevity. Through the current generating apparatus 202, a zero can be induced to the feedback-controlled system 200. According to FIG. 11, the voltage Vn+m at the output of the (n+m)th operational stage 201n+m is represented using the following equation (5):
Vn+m=Vn*(An+1*An+2 . . . An+m)+Vn*N*s*C1*RIN. (5)
Then,
Vn+m/Vn=(An+1*An+2 . . . An+m+N*s*C1*RIN). (6)
Thus, a zero ωz can be obtained from the equation (6),
ωz=(An+1*An+2 . . . An+m)/(N*C1*RIN),
wherein C1 is the capacitive device of the voltage-controlled current source 104 of FIG. 8, RIN is the input resistor at the output of the (n+m)th operational stage 201n+m, and N is the current mirror ratio of the first current mirror 1041 and the second current mirror 1043. Therefore, by utilizing the current generating apparatus 202 zero ωz can be added to the feedback-controlled system 200 and without introducing any pole.
It should be note that a person skilled in this art can readily appreciate that the voltage regulator is a kind of the feedback-controlled system. Referring to FIG. 7 in conjunction with FIG. 11, it is clear that the voltage regulator 100 includes three operational stages connected in a closed loop, where the pass transistor MP serves as one operational stage, the voltage divider 101 serves as another operation stage, and the error amplifier 102 serves as yet another operational stage.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Patent Grant
7504814
