Current-integrating successive-approximation analog-to-digital converter

Abstract

The current-integrating analog-to-digital converter includes a first charge storage device C.sub.1 ; a second charge storage device C.sub.2 ; an input current I.sub.in coupled to the first charge storage device C.sub.1 for a first time period; a variable reference current I.sub.dac coupled to the second charge storage device C.sub.2 for a second time period; and a comparator 20 for comparing the voltage on the first charge storage device C.sub.1 with the voltage on the second charge storage device C.sub.2.

Description

FIELD OF THE INVENTION

This invention generally relates to electronic systems and in particular it relates to analog-to-digital converters.

BACKGROUND OF THE INVENTION

One popular type of analog-to-digital (A/D) converter is the successive-approximation A/D converter. The successive-approximation A/D converter compares a digital-to-analog D/A output with the analog signal. The conversion starts with a D/A output corresponding to a most significant bit (MSB) of "1" and all other bits at "0". This D/A output is compared with the analog signal. If the D/A output is larger, the "1" is removed from the MSB. Then the next most significant bit is set to "1" with all the less significant bits remaining at "0". The corresponding D/A output is again compared with the analog signal. If the D/A output is larger, the "1" is removed from the next most significant bit. This process continues until a "1" is tried in each bit. The binary number remaining at the end of the process is the binary equivalent of the analog signal.

SUMMARY OF THE INVENTION

Generally, and in one form of the invention, the current-integrating analog-to-digital converter includes a first charge storage device; a second charge storage device; an input current coupled to the first charge storage device for a first time period; a variable reference current coupled to the second charge storage device for a second time period; and a comparator for comparing the voltage on the first charge storage device with the voltage on the second charge storage device.

DESCRIPTION OF THE DRAWINGS

In the drawings:

FIG. 1 is a schematic diagram of a first preferred embodiment current-integrating analog-to-digital converter;

FIG. 2 is a schematic diagram of the first preferred embodiment current-integrating analog-to-digital converter with MOS source followers at the input of the comparator;

FIG. 3 is a schematic diagram of a second preferred embodiment current-integrating A/D converter used to digitize time/phase difference.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Referring to FIG. 1, a circuit diagram of a preferred embodiment current-integrating analog-to-digital converter is shown. The circuit includes comparator 20, currents I.sub.dac (variable reference current) and I.sub.in (analog input current), capacitors (charge storage devices) C.sub.1 and C.sub.2 and switches S.sub.1 -S.sub.6. The switches S.sub.3 and S.sub.5 steer the current I.sub.in to either capacitor C.sub.1 or ground. When S.sub.3 is on, S.sub.5 is off, and when S.sub.5 is on, S.sub.3 is off. Similarly, the switches S.sub.4 and S.sub.6 steer current I.sub.dac to either capacitor C.sub.2 or ground. Initially, S.sub.1 and S.sub.2 are closed to discharge C.sub.1 and C.sub.2, while S.sub.3 and S.sub.4 are opened, and S.sub.5 and S.sub.6 are closed so that the currents I.sub.in and I.sub.dac flow to ground. Then S.sub.1 is opened and I.sub.in is directed to C.sub.1 for a set period of time such as one clock period T. For a constant I.sub.in, a charge of (I.sub.in .times.T) will be integrated on C.sub.1, giving a voltage of (I.sub.in .times.T/C.sub.1). The current I.sub.dac is set to I.sub.ref /2. With S.sub.2 opened, the current I.sub.dac is directed to C.sub.2 for one clock period, generating a voltage of (0.5.times.I.sub.ref .times.T/C.sub.2). With C.sub.1 and C.sub.2 equal, the voltage comparator 20 basically compares I.sub.in to I.sub.ref /2. If I.sub.in is greater, a "1" will be stored as the most significant bit (MSB). A "0" is registered otherwise. C.sub.2 is then discharged and I.sub.dac is set to (3.times.I.sub.ref /4) if the MSB is a "1". I.sub.dac is set to I.sub.ref /4 otherwise. I.sub.dac is then used to charge C.sub.2 for one clock period and the resulting voltage is compared with (I.sub.in .times.T/C.sub.1) to determine the second MSB. In a similar manner, the remaining bits are determined by this successive approximation method.

In the above scheme, one clock period can be used to discharge the capacitor and one clock period can be given to the comparator to resolve the voltage difference. Thus, each bit would require a total of three clock periods. For instance, an 8-bit converter would need only 24 clock periods to determine all 8 bits. The switches S.sub.1, S.sub.2, S.sub.3, S.sub.4, S.sub.5, and S.sub.6 can be implemented with p-channel MOS transistors. The input current I.sub.in can be integrated over multiple clock periods and is not limited to a constant current. If the current is varying, a voltage proportional to the "average" value of I.sub.in will appear on C.sub.1 as a result of the current integration. The reference current I.sub.ref or capacitors C.sub.1 and C.sub.2 can be scaled to adjust the gain to cover the range of the integrated input current. The current I.sub.dac can be generated by a current-output digital-to-analog converter. If C.sub.1 is made equal to C.sub.2, the conversion scheme will be relatively insensitive to the voltage coefficients of C.sub.1 and C.sub.2.

For the conversions to be accurate, the comparator needs to have high input impedance and any capacitor coupling of the comparator's output to its input needs to be minimized. To accomplish this, MOS source followers can be used at the input of the comparator 40, as shown in FIG. 2. The circuit of FIG. 2 is the same as the circuit of FIG. 1 with the addition of the MOS source followers which consist of current sources I.sub.1 and I.sub.2, and transistors M.sub.1 and M.sub.2.

With slight modification, the current-integration A/D converter can be used to digitize time/phase difference. The second preferred embodiment, shown in FIG. 3, can be used to digitize time/phase difference. The circuit in FIG. 3 includes comparator 20, current I.sub.dac, capacitors C.sub.1 and C.sub.2, and switches S.sub.1 -S.sub.4 and S.sub.6. In this circuit, I.sub.dac is used to charge both C.sub.1 and C.sub.2. If the current I.sub.dac is set to I.sub.ref and the current is integrated on C.sub.1 over a period corresponding to a time difference T.sub.d, a voltage of (I.sub.ref .times.T.sub.d /C.sub.1) will be created on C.sub.1. This voltage can then be digitized by the successive approximation method described above. The full-scale of the time difference is basically determined by the clock period T. If necessary, the conversion gain can be varied by adjusting C.sub.1 and C.sub.2, or integrating a current scaled from I.sub.ref on C.sub.1.

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Claims

1. A process comprising:

charging a first capacitor with a first current for a first time period;

charging a second capacitor with a second current for a second time period;

comparing a voltage on the first capacitor with a voltage on the second capacitor;

discharging the second capacitor; and

repeating the steps of charging a second capacitor, comparing a voltage, and discharging the second capacitor at least one time, the second current is at a different current level each time the steps are repeated.

2. The process of claim 1 further comprising, after the step of comparing a voltage, providing a logic one if the voltage on the first capacitor is greater than the voltage on the second capacitor and providing a logic zero otherwise.

3. The process of claim 1 wherein the different current levels are selected such that a digital equivalent of the first current is derived.

4. The process of claim 1 wherein the first time period and the second time period are equal.

5. A current-integrating analog-to-digital converter comprising:

a first charge storage device;

a second charge storage device;

an input current coupled to the first charge storage device for a first time period;

a first switch coupled between the input current and the first charge storage device;

a variable reference current coupled to the second charge storage device for a second time period;

a second switch coupled between the variable reference current and the second charge storage device;

a comparator for comparing the voltage on the first charge storage device with the voltage on the second charge storage device.

6. The circuit of claim 5 wherein the first charge storage device and the second charge storage device are capacitors.

7. A current-integrating analog-to-digital converter comprising:

a comparator;

a first capacitor coupled to a first input of the comparator;

a second capacitor coupled to a second input of the comparator;

an analog current input coupled to the first capacitor for a first time period;

a first switch coupled between the analog current input and the first capacitor;

a variable reference current input coupled to the second capacitor for a second time period; and

a second switch coupled between the variable reference current input and the second capacitor.

8. The circuit of claim 7 further comprising:

a third switch for discharging the first capacitor; and

a fourth switch for discharging the second capacitor.

9. The circuit of claim 7 further comprising:

a third switch for coupling the analog current input to ground; and

a fourth switch for coupling the variable reference current input to ground.

10. The circuit of claim 7 wherein the comparator provides a logic one if the analog current input is greater than the variable reference current input, and a logic zero otherwise.

11. The circuit of claim 7 wherein the first and second inputs of the comparator include MOS source followers.

12. The circuit of claim 7 wherein the first capacitor and the second capacitor are the same size.

13. A circuit for digitizing time/phase difference comprising:

a variable reference current;

a first capacitor coupled to the variable reference current for a first time period;

a second capacitor coupled to the variable reference current for a second time period;

a comparator coupled to the first capacitor and coupled to the second capacitor for comparing the voltage on the first capacitor with the voltage on the second capacitor.

14. The circuit of claim 13 further comprising:

a first switch for coupling the variable reference current to the first capacitor;

a second switch for coupling the variable reference current to the second capacitor.

15. The circuit of claim 13 further comprising:

a first switch for discharging the first capacitor; and

a second switch for discharging the second capacitor.

16. The circuit of claim 13 wherein the comparator provides a logic one if the voltage on the first capacitor is greater than the voltage on the second capacitor, and a logic zero otherwise.

17. The circuit of claim 13 wherein the first capacitor and the second capacitor are the same size.