Patent Grant
9092041
A current mirror is a circuit designed to emulate a current through one active device by controlling the current in another active device of a circuit, keeping the output current constant regardless of loading. The current being emulated can be a varying signal current. Current mirrors can be used in analog circuits as biasing, reference, and simple current-operator circuit elements. Common usages for current mirrors are in output amplifiers and linear regulators. Line regulation is the capability to maintain a constant output voltage level on an output channel despite changes to the input voltage level.
Current mirrors can be characterized by a transfer ratio, in the case of a current amplifier, or the output current magnitude, in the case of a constant current source. Current mirrors can also be characterized by an alternating current (AC) output resistance and by a minimum voltage drop, referred to as dropout voltage. The output resistance determines how much the output current varies with the output voltage applied to the current mirror. The dropout voltage is the smallest possible difference between the input voltage and output voltage to remain within the intended operating range of the device. This minimum voltage is dictated by the need to keep the output transistor of the current mirror in active mode.
Two important characteristics of output amplifiers and linear regulators are minimum supply voltage at maximum rated output current and output voltage variation from minimum to maximum supply voltage. There is usually a tradeoff between these two characteristics; minimum gate length of common source output metal-oxide-semiconductor (MOS) device minimizes dropout voltage while increasing supply sensitivity at low output current. Supply sensitivity is increased at low output current due to reduced amplifier open loop gain and lower effective “Early” voltage of output device operating in moderate or weak inversion. Increasing open loop amplifier or regulator direct current (DC) gain reduces DC supply sensitivity, but stable feedback requires gain to “roll-off” as frequency increases. This results in increased supply sensitivity with increasing frequency.
A current mirror circuit that is configured to adjust a body to source voltage of an input device in response to a drain to source voltage of an output device is disclosed. In an implementation, the current mirror circuit comprises a current mirror including an input device and an output device coupled together. The current mirror circuit also includes a feedback circuit component coupled between the output of the current mirror and the input device. The feedback circuit component is configured to adjust a body to source voltage of the input device in response to a drain to source voltage of the output device.
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The Detailed Description is described with reference to the accompanying figures. The use of the same reference numbers in different instances in the description and the figures may indicate similar or identical items.
A number of current mirror circuit designs have been implemented to provide accurate transfer gain, within a high frequency band, while exhibiting low input and high output resistance.
The schematic current mirror circuit is shown in
The current mirror includes a transistor P0, a transistor P1, a transistor P2, and a level shifter. The transistor P0 functions as an input device for the current mirror, and the transistor P1 functions as an output device for the current mirror. The gate of the transistor P0 is coupled to the gate of the transistor P1. The source and the body of the transistor P0 are coupled to the supply voltage VIN, and the source and the body of the transistor P1 are also coupled to the supply voltage VIN. As such, the sources of the transistors P0 and P1 are coupled together, and the bodies of the transistors P0 and P1 are coupled together. The drain of the transistor P0 is coupled to the source of the transistor P2. The gate of the transistor P0 and the gate of the transistor P1 are coupled to the drain of the transistor P2. The output of the current mirror is coupled to the drain of the transistor P1. The level shifter is coupled between the drain of the transistor P1 and the gate of the transistor P2. The body of the transistor P2 is coupled to the supply voltage VIN. The drain of the transistor P2 is coupled to a bottom half (not shown) of the output stage of the amplifier 2. In operation, the drain voltage of the transistor P0 is adjusted to track the drain voltage of the transistor P1. As such, the gate shared by the transistor P0 and the transistor P1 is adjusted automatically by the transistor P0 to whatever voltage is needed to result in a constant output current. The current mirror of
In an effort to reduce the minimum supply voltage at maximum rated output current for the current mirror, the gate length of the output transistor P1 can be shortened and the gate width widened, which effectively lowers the channel resistance RDSON=1/gm=[μCoxW/L(VGS−VT)]−1. However, the shorter transistor gate length negatively affects the line regulation of the current mirror because the output resistance of the device ro=1/(λId) is lowered with reduced gate length. As such, there is a trade-off between improving the on-resistance of the current mirror and concurrently lowering the output resistance. Line regulation=δVOUT/δVIN=δVGSP1/[(Av)(δVIN)], where Av is amplifier open loop gain from input to gate of output PMOS device P1. The output resistance of P1, Ro=δVDS/δVD=WIN/[δ(VGS)gm] for constant VOUT. Substituting δVIN/δVGS into line regulation equation gives line regulation=1/gmRoAv.
The current mirror of
Other current mirror configurations use the transistor body as an input terminal while keeping the gate voltage constant to turn the transistor on. This is referred to as a body-driven technique.
The present disclosure is directed to a current mirror circuit that is configured to adjust a body to source voltage of an input device in response to a drain to source voltage of an output device is disclosed. In an implementation, the current mirror circuit comprises a current mirror including an input device and an output device coupled together. The current mirror circuit also includes a feedback circuit component coupled between the output of the current mirror and the input device. The feedback circuit component is configured to adjust a body to source voltage of the input device in response to a drain to source voltage of the output device.
Reference is now made in detail to implementations of the current mirror circuit as illustrated in the accompanying drawings. The same reference indicators are used throughout the drawings and the following detailed description to refer to the same or like parts. In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will, of course, be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions may be made in order to achieve the developer's specific goals, such as compliance with application and business related constraints, and that these specific goals will vary from one implementation to another and from one developer to another. Moreover, it should be appreciated that such a development effort may be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.
The schematic current mirror circuit is shown in
The current mirror circuit includes a transistor P0, a transistor P1, a transistor P2, a resistor Rb1, and a resistor Rb2. The transistor P0 functions as an input device for the current mirror, and the transistor P1 functions as an output device for the current mirror. The gate of the transistor P0 is coupled to the gate of the transistor P1, and the gates of the transistors P0 and P1 are coupled to the drain of the transistor P0. The source of the transistor P0 is coupled to the supply voltage VIN, and the source of the transistor P1 is coupled to the supply voltage VIN. As such, the sources of the transistors P0 and P1 are coupled together. The body of the transistor P1 is also coupled to the supply voltage VIN. The output of the current mirror is coupled to the drain of the transistor P1. The resistors Rb1 and Rb2 form a voltage divider coupled to the supply voltage VIN, the body of the transistor P0, and the source of the transistor P2. The transistor P2 is coupled between the drain of the transistor P1 and the resistor Rb2. The body of the transistor P2 is coupled to the source of the transistor P2. The drain of the transistor P2 is coupled to ground. The gate of the transistor is coupled to the drain of the transistor P1. The drain of the transistor P0 is coupled to a bottom half of the output stage of the amplifier 10. In some implementations, the transistors P0, P1, and P2 are p-type MOS field effect transistors (FETs), as shown in
The current mirror circuit is configured to provide a feedback compensation so that as the supply voltage VIN moves up or down, the output voltage VOUT does not change. The gate length of the transistor P1 is minimized to reduce dropout voltage. In some implementations, the gate length of the transistor P0 is the same as the transistor P1 for accurate ratio of P1 to P0 drain current. Minimum gate length devices exhibit reduced output resistance due to reduction of threshold voltage as drain to source voltage increases. This is referred to as the “short channel effect.” Variation in the supply voltage VIN results in variations of the source to drain voltage of the transistor P1 while the source to drain voltage of the transistor P0 is fixed. The buffered voltage divider formed by the transistor P2, the resistor Rb1, and the resistor Rb2 drives the body of the transistor P0 with a fraction of VOUT−VGSP2 (gate to source voltage of the transistor P2) to reduce the threshold voltage of the transistor P0 as the supply voltage VIN increases. Therefore, both P0 and P1 experience reduced threshold voltage as VIN increases resulting in less change in current ratio between the transistor P0 and the transistor P1. At low output current, the transistors P0 and P1 are operating in moderate or weak inversion (VGS−VT<0.2V), a region where drain current is more sensitive to threshold voltage variation. Therefore, this scheme significantly improves line regulation for load current <1% of rated value, as shown in
In operation, the output voltage VOUT is fed back to the body of the transistor P0 so as to compensate for changes in the supply voltage VIN. As the supply voltage VIN increases, the source to body voltage VSB of transistor P0 also increases. However, the body voltage VSB does not increase at the same rate as the increase in the supply voltage VIN. This is due to the voltage divider formed by the resistors Rb1 and Rb2. MOSFET threshold voltage is modeled by Vt=Vto+γ[√(2φf+VSB)−√(2φf)], γ=√(2qεNA)/Cox. Gamma (γ) is the process dependent coefficient of threshold voltage sensitivity to VSB; a typical value is 0.6√N. The signal path from the output VOUT through the transistor P2 and the voltage divider to the body of the transistor P0 provides feedback so that as the drain to source voltage across the transistor P1 increases, the gate to source voltage of both transistors P0 and P1 may decrease. This compensates for the change in the supply voltage VIN. In this manner, the transistor P1 functions as if it has a longer gate channel length than it really does because of the feed back result at the gate to compensate for voltage changes at the drain.
The ratio of the voltage divider is determined according to the body effect coefficient gamma of the transistor P0, which is a parameter of the particular process used to fabricate the transistor. The body effect can be determined empirically, it can be simulated, or it can be calculated. In general, the resistor Rb1 is much smaller than the resistor Rb2. The bigger the resistor Rb1, the more correction is being applied. In an example, if VIN-VOUT increases by 3V, then the body voltage VSB may only increase about 0.1V, which reduces the threshold voltage of the transistor P0 at least approximately 0.03V.
There is no significant current at the body of the transistor P0 because the body to source junction of the transistor P0 is a reverse biased junction. As such, the size of the resistors can be large, such as megaohms. In an exemplary implementation, the resistor Rb2 is on the order of 100 Kohms, and the resistor Rb1 is on the order of 10 Kohms. Different sized resistors can be used.
The combination of the resistors Rb1 and Rb2 with the transistor P2 forms a buffered voltage divider because the transistor P2 isolates the voltage divider from the output. In other words, no current flows from the output through the resistors Rb1 and Rb2 because the gate current of the transistor P2 is about zero. As such, the transistor P2 functions as a buffer between the voltage divider and the output. Additionally, the transistor P2 functions as a level shifter. The voltage supplied to the voltage divider at the source of the transistor P2 is equal to the voltage output VOUT minus the gate to source voltage Vgs of the transistor P2. When the supply voltage VIN drops to the point where the output VOUT is within a gate to source voltage Vgs of the supply voltage VIN, then the amount of feedback at the body of the transistor P0 is zero, as desired. In other words, since the gate and drain of the transistor P0 are shorted together, the gate voltage of the transistor P0 is equal to the drain voltage, which means Vds is equal to Vgs, and in that condition it is desired that the body voltage Vbody equal the supply voltage VIN. The transistor P2 makes this the case for both the transistors P0 and P1.
The exemplary circuit shown in
The gate to source voltage of the transistor P0 is adjusted in response to changes in the drain to source voltage of the transistor P1 in a way that minimizes the change in drain current of the transistor P1 for changes in the drain to source voltage of the transistor P1. This effect is not linear. In some implementations, the feedback supplied to the body of the transistor P0 is derived from a replica mirror with matching bias conditions.
Although the subject matter has been described in language specific to structural features and/or process operations, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
| Number | Name | Date | Kind |
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| 20080072181 | Baumgartner et al. | Mar 2008 | A1 |
| 20130043957 | Shibata | Feb 2013 | A1 |
| 20140084975 | Tang et al. | Mar 2014 | A1 |
