Current mirror circuit with interconnected control electrodies coupled to a bias voltage source

Abstract

A current mirror circuit is described which includes a current input terminal (14A), a current output terminal (14B) and a common terminal (14C). A first controllable semiconductor element (T1) is arranged between the current input terminal (14A) and the common terminal (14C). A second controllable semiconductor element (T2) is arranged between the current output terminal (14B) and the common terminal (14C). The controllable semiconductor elements (T1, T2) have interconnected control electrodes (T1A, T2A) which are also coupled to a bias voltage source (VBIAS), for biasing said control electrodes at a reference voltage. The circuit further includes a transconductance stage (12) with an input (12A) coupled to the current input terminal (14A) and an output (12B) coupled to the common terminal (14C). The control electrodes (T1A, T2A) are coupled to the common terminal (14C) via a third controllable semiconductor element (T3). The bias voltage source (VBIAS) is coupled to the control electrodes of the first and the second controllable semiconductor element (T1, T2) via a control electrode (T3A) of the third controllable semiconductor element (T3). The current mirror circuit has high bandwidth also at low input currents and is very suitable for application in an arrangement for reproducing an optical record carrier.

Description

The invention pertains to a current mirror circuit including a current input terminal, a current output terminal and a common terminal, a first controllable semiconductor element arranged between the current input terminal and the common terminal, a second controllable semiconductor element arranged between the current output terminal and the common terminal, the controllable semiconductor elements having interconnected control electrodes which are also coupled to a bias voltage source, for biasing said control electrodes at a reference voltage, the circuit further including a transconductance stage having an input coupled to the current input terminal and an output coupled to the common terminal.

Such a current mirror circuit is known from WO 00/31604. In the known circuit the transconductance stage generates a current which is divided over the first and the second semiconductor element, so that the input voltage is maintained close to a reference voltage. It is realised therewith that the input impedance is significantly decreased so that a large bandwidth is obtained However, in the known circuit the imput impedance depends relatively strongly on the current amplification factor of the first and second controllable semiconductor elements, which on its turn is dependent on the input current. As the source of the input current generally has a finite impedance, this entails that the bandwidth of the mirror circuit is dependent on the input current.

It is an object of the invention to provide a current mirror circuit according to the opening paragraph in which the dependence of the bandwidth on the input current is reduced. According to the invention the current mirror circuit is characterized in that the control electrodes are coupled to the common terminal via a third controllable semiconductor element, and in that the bias voltage source is coupled to the control electrodes of the first and the second controllable semiconductor element via a control electrode of the third controllable semiconductor element. At a low input current the current amplification factor of the first and the second controllable semiconductor element strongly reduces. This has the effect that a relatively large current flows via the control electrodes of these semiconductor elements. In the current mirror circuit of the invention the current via the control electrodes to the common terminal flows back via the third controllable semiconductor element, so that this effect is compensated. As a result the input impedance, and therewith the bandwidth is less dependent on the input current.

In a preferrable embodiment the interconnected control electrodes are further connected to a current source. This current source may serve at the same time to bias the third semiconductor element and to bias a component of the transconductance stage.

A further preferable embodiment is characterized in that the first and the second semiconductor elements have an area ratio 1:P. In that way the circuit operates as a current amplifier.

A still further preferable embodiment is characterized in that the first and the second semiconductor elements are bridged by a first and a second capacitive impedances having a capacitive value with a ratio of 1 to P. This measure further improves the bandwidth. The high frequency components generated by the transconductance stage are divided over the first and the second capacitive impedances in a ratio determined by the ratios of their capacitive values. As the ratios of the capacitive values corresponds to the area ratios of the controllable semiconductor elements a flat amplification-frequency characteristic is obtained over a large frequency range.

Another preferable embodiment of the invention is characterized in that the interconnected control electrodes are further connected via a third capacitive impedance and via a fourth controllable semiconductor element to a reference voltage, and that a control electrode of the fourth controllable semiconductor element is coupled to the common terminal. In the circuit of the invention the common terminal shows relatively large voltage variations. These may induce losses via stray capacitances. The auxiliary circuit formed by the third capacitive element and the fourth controllable semiconductor element achieves that these losses are compensated for, as a result of which the bandwidth is still further improved.

An integrated circuit according to the invention comprises at least one current mirror circuit according to the invention, and a photodiode having an output coupled to its current input terminal. The integrated photodiodes have a relatively small capacitance as compared to discrete photo diodes, which is also favorable for the bandwidth.

Such an integrated circuit is described in more detail in the ANNEX: “High-Bandwidth Low-Capacitance Integrated Photo Diodes for Optical Storage”.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of photodiodes;

FIG. 2 is a detailed diagram of a current preamplifiers;

FIG. 3 is a current mirror stage according to the invention;

FIG. 4 is a second embodiment of a current mirror according to the invention;

FIG. 5 is a third embodiment of a current mirror according to the invention;

FIG. 6 is an arrangement for an optical record carrier.

FIG. 1 schematically shows an integrated circuit comprising photodiodes A, . . . , F, the photodiodes A, . . . , D are coupled to current pre-amplifiers 1 A, . . . , 1 D and the photodiodes E and F are coupled to transimpedance amplifiers 3 F and 3 G respectively. The current pre-amplifiers 1 A . . . , 1 D each have a first output coupled to a respective transimpedance amplifier 2 A, . . . , 2 D. The current pre-amplifiers 1 A, . . . , 1 D each have a second output. The latter are interconnected as well as connected to the input of a further transimpedance amplifier 2 RF.

One of the current pre-amplifiers is shown in more detail in FIG. 2 . The current amplifier comprises a cascade of current mirrors 14 , 18 , 22 and 26 . to amplify the signal provided by the diode A. The current amplifier comprises a current mirror circuit 14 including a current input terminal 14 A coupled to the photo diode A, a current output terminal 14 B and a common terminal 14 C. A transconductance stage 12 has an input 12 A coupled to the current input terminal 14 A and an output 12 B coupled to the common terminal 14 C. The transconductance stage has a further input 12 C coupled to a reference voltage source 10 . Likewise current mirror circuits 18 and 22 are coupled to a transconductance stage 16 and 20 . Also the current mirror circuit 26 is coupled to a transconductance stage 24 , but in this case the output of the transconductance stage 24 is coupled to the mutually interconnected control electrodes of the controllable semiconductor elements 26 A, 26 B forming part of this current mirror circuit.

FIG. 3 shows an embodiment of a current mirror stage 14 according to the invention. The current mirror circuit includes a current input terminal 14 A, a current output terminal 14 B and a common terminal 14 C. The input terminal 14 A is connected to a photodiode A, which is represented here in the form of a signal current source Sph and a parasitic capacitance Cph. The output terminal 14 B is connected to a load Zi 2 . A first controllable semiconductor element T 1 is arranged between the current input terminal 14 A and the common terminal 14 C. A second controllable semiconductor element T 2 is arranged between the current output terminal 14 B and the common terminal 14 C. In casu the semiconductor elements T 1 , T 2 are connected to the common terminal via degeneration resistors R 2 , R 3 . The controllable semiconductor elements T 1 , T 2 have interconnected control electrodes T 1 A, T 2 A which are also coupled to a bias voltage source V BIAS , for biasing said control electrodes at a reference voltage.

The circuit further includes a transconductance stage 12 having an input 12 A coupled to the current input terminal 14 A and an output 12 B coupled to the common terminal 14 C.

The circuit according to the invention is characterized in that the interconnected control electrodes T 1 A, T 2 A are coupled to the common terminal via a third controllable semiconductor element T 3 , and in that the bias voltage source V BIAS is coupled to these control electrodes T 1 A, T 2 A via a control electrode T 3 A of the third controllable semiconductor element T 3 . The interconnected control electrodes T 1 A, T 2 A are further connected to a current source SI.

In the embodiment shown the transconductance stage 12 comprises a fifth controllable semiconductor element T 5 which is arranged between its output 12 B and ground GND. The fifth controllable semiconductor element T 5 has a control electrode which is coupled to a common node 12 D of a series arrangement of a further controllable semiconductor element MO and a resistive impedance R 1 . The current source SI both biases the third and the fifth controllable semiconductor elements T 3 and T 5 .

The circuit shown in FIG. 3 operates as follows. If the photodiode provides a current Iph to the input terminal 14 A of the current mirror, the transconductance stage 12 will withdraw a current Ic from the common terminal 14 C of the current mirror such that the current Ii 1 via the input terminal 14 A equals the current Iph provided by the photodiode A. The operation of the current mirror formed by T 1 and T 2 has the effect that a current Io 1 is delivered by the second controllable semiconductor element T 2 . The currents have a ratio Io 1 :Ii 1 =P, P being the area ratio of the controllable semiconductor elements T 1 , T 2 . At the same time the control electrodes T 1 A, T 2 A of the controllable semiconductor elements T 1 , T 2 respectively conduct a current Ib 1 , Ib 2 such that Ii 1 =α Ib 1 and Io 1 =αIb 2 . As the third controllable semiconductor element T 3 is biased by a current source, the signal currents Ib 1 +Ib 2 will be conducted substantially from the common terminal 12 B via the main current path of that semiconductor element T 3 . Hence these signal currents Ib 1 , Ib 2 substantially do not contribute to the current Ic withdrawn by the transconductance stage 12 . The current Ic therefore is Ii 1 (1+P). If the transconductange stage has an amplification gm, then the input resistance amounts (1+P/gm which is independent of the current amplification of the controllable semiconductor elements T 1 , T 2 .

In the known circuit which does not include a controllable semiconductor element T 3 as in the invention, the input resistance amounts (1+P)(1+1/α)gm

Hence in the known circuit the input resistance is dependent on the amplification a of the controllable semiconductor elements. This is on its turn dependent on the current conducted by these elements. At low input currents the amplification α decreases, as a result of which the input resistance increases. This causes increasing signal losses at higher frequencies. In the circuit of the invention this phenomenon has been substantially annihilated.

FIG. 4 shows a second embodiment of the current mirror according to the invention. In FIG. 4 elements which have the same references are the same. This embodiment is characterized in that the first and the second semiconductor elements T 1 , T 2 are bridged by a first and a second capacitive impedance C 1 , C 2 having a capacitive value with a ratio of 1 to P. The first and the second capactive impedances C 1 , C 2 will respectively conduct signal currents Ic 1 and Ic 2 , having a ratio Ic 2 /Ic 1 =P. Hence the capacitive impedances C 1 , C 2 contribute to the currents passing via the input and the output terminal 14 A, 14 B in the same ratio as the controllable semiconductor elements. As the frequency of the input signal of the current mirror increases and the amplification factors of the controllable semiconductor elements T 1 , T 2 decreases the capacitive impedances C 1 , C 2 gradually take over the function of the semiconductor elements T 1 , T 2 .

FIG. 5 shows a third embodiment of the current mirror according to the invention. Parts of FIG. 5 having the same reference number as in FIG. 4 are identical. The embodiment shown is characterized in that the interconnected control electrodes T 1 A, T 2 A are further connected via a third capacitive impedance C 3 and via a fourth controllable semiconductor element T 4 to a reference voltage GND. A control electrode T 4 A of the fourth controllable semiconductor element T 4 is coupled to the common terminal 14 C.

As illustrated in FIG. 5 , losses Ip may be caused by parasitic impedance Cp. However, as in this embodiment of the invention the parasitairy capacitor Cp, the bias voltage source, the base emitter transition of T 3 , the capacitive impedance C and the emitter base transition of T 4 form a closed loop the sum of the voltages should be 0. From this it follows that the parasitic current Ip is completely compensated provided that the capacitance C 3 is chosen equal to the parasitic capacitance Cp.

FIG. 6 schematically shows an arrangement for reproducing an optical record carrier 30 . The arrangement comprises a read head 40 including a radiation source 41 for generating a radiation beam 42 . The read head further comprises an optical system 43 for directing the beam after interaction with the record carrier 30 to one or more photodiodes. The read head 40 also comprises a signal processing circuit with respective amplifiers comprising a current mirror circuit according to the invention, for example according to one of the embodiments shown in FIGS. 3 , 4 and 5 . The current mirror circuits each have an input coupled to one of the photodiodes. In the embodiment shown the photodiodes and the amplifiers are together integrated at an IC 45 as shown schematically in FIG. 1. A signal output of the signal processing circuit is coupled to a channel decoding circuit and/or an error correction circuit 50 for reconstructing an information stream Sinfo from the signal Sout provided by the signal processing circuit. The arrangement is provided with means 61 , 62 for providing a relative movement between the read head 40 and the record carrier 30 . In the embodiment shown the means 61 rotate the record carrier and the means 62 provide for a radial movement of the read head. Otherwise the means 61 , 62 may for example be linear motors for moving the read head 40 and the record carrier respectively in mutually orthogonal directions.

It is remarked that the scope of protection of the invention is not restricted to the embodiments described herein. In the embodiments mainly bipolar transistors are shown. However, instead of bipolar transistors unipolar or MOSFET transistors can be used. In that case gate, source and drain of the unipolar transistor substitute respectively the base, emitter and collector, of the bipolar transistor. Multiple outputs are possible by providing copies of the transistor T 2 between the common terminal 14 C and additional output terminals 14 B. Neither is the scope of protection of the invention restricted by the reference numerals in the claims. The word ‘comprising’ does not exclude other parts than those mentioned in a claim. The word ‘a(n)’ preceding an element does not exclude a plurality of those elements. Means forming part of the invention may both be implemented in the form of dedicated hardware or in the form of a programmed general purpose processor. The invention resides in each new feature or combination of features.

Claims

1. Current mirror circuit including a current input terminal, a current output terminal and a common terminal, a first controllable semiconductor element arranged between the current input terminal and the common terminal, comprising:a second controllable semiconductor element arranged between the current output terminal and the common terminal, the controllable semiconductor elements having interconnected control electrodes which are also coupled to a bias voltage source, for biasing said control electrodes at a reference voltage, the circuit further including a transconductance stage having an input coupled to the current input terminal and an output coupled to the common terminal, characterized in that the control electrodes are coupled to the common terminal via a third controllable semiconductor element, and in that the bias voltage source is coupled to the control electrodes of the first and the second controllable semiconductor element via a control electrode of the third controllable semiconductor element.

2. Current mirror circuit according to claim 1, characterized in that the interconnected control electrodes are further connected to a current source.

3. Current mirror circuit according to claim 1, characterized in that the first and the second semiconductor elements have an area ratio 1:P.

4. Current mirror circuit according to claim 3, characterized in that the first and the second semiconductor elements are bridged by a first and a second capacitive impedances having a capacitive value with a ratio of 1 to P.

5. Current mirror circuit according to claim 1, characterized in that the interconnected control electrodes are further connected via a third capacitive impedance and via a fourth controllable semiconductor element to a reference voltage, and that a control electrode of the fourth controllable semiconductor element is coupled to the common terminal.

6. Integrated circuit comprising at least one a current mirror circuit according to claim 1, and a photodiode having an output coupled to the current input terminal of said at least one current mirror circuit.

7. Arrangement for reproducing an optical record carrier, comprising:a read head including a radiation source for generating a radiation beam, an optical system for directing the beam after interaction with the record carrier to one or more photodiodes, respective amplifiers comprising a current mirror circuit according to claim 1, each having an input coupled to one of the photodiodes, a channel decoding circuit and/or an error correction circuit for reconstructing an information stream from the signal provided by an amplifier, means for providing a relative movement between the read head and the record carrier.

8. The arrangement of claim 7, wherein the current mirror circuit further comprises the interconnected control electrodes are further connected to a current source.

9. The arrangement of claim 7, wherein the current mirror circuit further comprises the first and the second semiconductor elements have an area ratio 1:P.

10. The arrangement of claim 9, wherein the current mirror circuit further comprises the first and the second semiconductor elements are bridged by a first and a second capacitive impedances having a capacitive value with a ratio of 1 to P.

11. The arrangement of claim 7, wherein the current mirror circuit further comprises the interconnected control electrodes are further connected via a third capacitive impedance and via a fourth controllable semiconductor element to a reference voltage, and that a control electrode of the fourth controllable semiconductor element is coupled to the common terminal.

12. The arrangement of claim 7, further comprising at least one current mirror circuit, and a photodiode having an output coupled to the current input terminal of said at least one current mirror circuit.