Current mirror circuit

Abstract

Current mirror circuit including a current input terminal (2), a current output terminal (6), a common terminal (8), a first transistor (T1) arranged between the current input terminal (2) and the common terminal (8), a second transistor (T2) arranged between the current output terminal (6) and the common terminal (8), a transconductance stage (TS) having an input terminal coupled to the current input terminal (2), and an output terminal coupled to the common terminal (8), and a bias source (22) for biasing the control electrodes of the first and second transistors (T1, T2). This configuration provides a large bandwidth independently of the input current, accurate current transfer and a single pole system.

Description

[0001] The invention relates to a current mirror comprising:

[0002] a first terminal for receiving an input current;

[0003] a second terminal for supplying an output current;

[0004] a common terminal;

[0005] a first transistor having a control electrode, and having a main current path arranged between the first terminal and the common terminal;

[0006] a second transistor having a control electrode connected to the control electrode of the first transistor, and having a main current path arranged between the second terminal and the common terminal.

[0007] Such a current mirror is known, for example, from U.S. Pat. No. 4,462,005 and is shown in FIG. 1. In this well-known basic current mirror the interconnected control electrodes, in this case the bases, of the first transistor T1 and the second transistor T2 are connected to the first terminal which forms the current input terminal of the current mirror. The common terminal is connected to a reference terminal, in this case the negative supply terminal which serves as signal ground. As will be explained hereinafter, the bandwidth of this known current mirror strongly depends on the input current due to the presence of an input capacitance Ci between the first terminal and the common terminal and of base-emitter capacitances Cbe of the first and the second transistor T1 and T2. By adding degeneration resistors in series with the emitters of the first and the second transistor T1 and T2, as shown in FIG. 2, the dependence on the input current can be avoided to some extent. However, this comes at the cost of a reduced bandwidth, an increased input impedance and a smaller voltage swing in comparison with to the basic current mirror of FIG. 1.

[0008] It is known to obtain an improvement in bandwidth by adding a gain stage GS as shown in FIG. 3. FIG. 4 shows gain stage formed by means of an emitter follower EF between the first terminal and the interconnected control electrodes of the first and the second transistor T1 and T2. This improved current mirror still has a bandwidth which depends on the input current.

[0009] Therefore, it is an object of the invention to provide a current mirror with improved performance. To obtain the above object, according to the present invention, the current mirror of the type defined in the opening paragraph is characterized in that the current mirror further comprises:

[0010] a transconductance stage having an input terminal coupled to the first terminal, and having an output terminal coupled to the common terminal;

[0011] and a bias source for biassing the control electrode of the first transistor and the control electrode of the second transistor.

[0012] The voltage at the first terminal is sensed by the transconductance stage which drives the common terminal. In this way a feedback loop is created which makes the current through the first transistor equal to the input current, thus providing a low input impedance. The first and the second transistor, assuming that they are bipolar transistors are, in common base configuration and provide a large bandwidth. Advantageous embodiments are defined in the dependent claims.

[0013] These and other aspects of the invention will be described and explained with reference to the appended drawings, in which:

[0014] FIG. 1 is a circuit diagram of a known current mirror;

[0015] FIG. 2 is a circuit diagram of a known current mirror;

[0016] FIG. 3 is a circuit diagram of a known current mirror;

[0017] FIG. 4 is a circuit diagram of a known current mirror;

[0018] FIG. 5 is a circuit diagram of a first embodiment of a current mirror in accordance with the invention;

[0019] FIG. 6 is a circuit diagram of a second embodiment of a current mirror in accordance with the invention;

[0020] FIG. 7 is a circuit diagram of a third embodiment of a current mirror in accordance with the invention; and

[0021] FIG. 8 is a circuit diagram of a fourth embodiment of a current mirror in accordance with the invention.

[0022] In these Figures parts having the same function or purpose are denoted by the same references.

[0023] FIG. 1 shows a circuit diagram of the well-known basic current mirror. Bipolar transistors are shown which each have an emitter and a collector which define the main current path of the transistor, and which each have a base which acts as a control electrode for controlling the current through the main current path. The current mirror has a first terminal 2 for receiving an input current I1 from an input current source 4, a second terminal 6 for supplying a mirrored output current I0, and common terminal 8 which is connected to signal ground 10. The main current path of a first transistor T1 is arranged between the first terminal 2 and the common terminal 8, and the main current path of a second transistor T2 is arranged between the second terminal 6 and the common terminal 8. The emitters of the transistors T1 and T2 are connected to the common terminal 8. The bases of the transistor T1 and T2 are interconnected and the interconnected bases are connected to the first terminal 2. The current mirror has an input capacitor 12 between the first terminal 2 and ground 10.

[0024] The DC current transfer characteristic of the current mirror is: 1$\begin{array}{cc}{I}_o=I_{\iota }\left(1-\frac{2}{\beta +2}\right)& \left(1\right)\end{array}$

[0025] where β is the current gain of the transistors T1 and T2. The bandwidth fh of this current mirror strongly depends on the input current I, and can be calculated with the following equation (2): 2$\begin{array}{cc}\mathrm{fh}=\frac{g_m}{2\pi ·\left(C_{\iota }+2C_{\mathrm{be}}\right)}=\frac{I_1}{2\pi ·\left(C_{\iota }+2C_{\mathrm{be}}\right)·V_T}& \left(2\right)\end{array}$

[0026] where gm=I1/VΥ is the small signal transconductance of the transistor T1, C1 the capacitance of input capacitor 12, Cbe the base-emitter capacitance of the transistors T1 and T2 and VΥ the thermal voltage of a bipolar transistor. From equation 2 it is apparent that the bandwidth fh is directly proportional to the input current I1. This dependence can be reduced by applying emitter degeneration as shown in FIG. 2. Degeneration resistors 14 and 16 are arranged in the emitter leads of the transistors T1 and T2, respectively. The bandwidth fh for this configuration can be calculated with the following equation: 3$\begin{array}{cc}\mathrm{fh}=\frac{1}{2\pi ·\left(C_i+2C_{\mathrm{be}}\right)·\left(R_e+r_e\right)}=\frac{1}{2\pi ·\left(C_i+2C_{\mathrm{be}}\right)·\left(R_e+\frac{V_T}{I_i}\right)}& \left(3\right)\end{array}$

[0027] where Γe=1/gm of the transistor T1, and Re the resistance of the degeneration resistor 14. If Re>>Γe, the bandwidth fh is mainly determined by the values of the capacitors and the degeneration resistor. The reduced input current dependence comes at the cost of a smaller bandwidth, an increased input impedance and a smaller voltage swing in comparison with the basic current mirror of FIG. 1.

[0028] FIG. 3 shows a known improved current mirror. The direct connection between the first terminal 2 and the interconnected bases is replaced with a gain stage GS, which has a non-inverting input connected to the first terminal 2, an inverting input connected to a reference voltage source 18 and an output connected to the interconnected bases. The input impedance Γi of this current mirror is given by: 4$\begin{array}{cc}{r}_i=\frac{1}{A·g_{\mathrm{m1}}}=\frac{1}{A}·\frac{V_T}{I_{\iota }}& \left(4\right)\end{array}$

[0029] where A is the gain of the gain stage GS and gml the transconductance of the transistor T1. The input impedance Γi together with the capacitance C1 of the input capacitor 12 form a pole which determines the bandwidth fh of the current mirror, and is given by: 5$\begin{array}{cc}\mathrm{fh}=\frac{1}{2\pi ·C_i·r_{\iota }}=\frac{A·I_i}{2\pi ·C_i·V_T}& \left(5\right)\end{array}$

[0030] Compared with the bandwidth of the basic current mirror in equation 2, the bandwidth fh has increased owing to the gain A and the missing capacitance Cbe, but is still proportional to the input current I1. Again, emitter degeneration can be applied just as in the basic current mirror at the same cost of bandwidth, input impedance and voltage swing.

[0031] FIG. 4 shows a version of the current mirror of FIG. 3 in which the gain stage is an emitter follower transistor EF which has its base connected to the first terminal 2, its emitter connected to the interconnected bases of the transistors T1 and T2 and to a bias current source 20. Owing to the high gain A the DC transfer characteristic of the current mirror of FIG. 3 is:

I0=I1  (5a)

[0032] while the DC current gain of the current mirror of FIG. 4 is given by: 6$\begin{array}{cc}{I}_o=\left(I_i-\frac{I_e}{\beta +1}\right)·\left(1-\frac{2}{{\beta }^2+1}\right)& \left(\text{5b}\right)\end{array}$

[0033] where Ie is the current of bias current source 20.

[0034] FIG. 5 shows a current mirror in accordance with the invention. The interconnected bases of the transistors T1 and T2 are biased by a bias source 22. The current mirror further has a transconductance stage TS which has an inverting input coupled to the first terminal 2, a non-inverting input to a bias source 24 and a current output to the common terminal 8. The voltage at the first terminal 2 is sensed by the transconductance stage TS, which drives the emitter of transistor T1. The feedback loop thus formed adjusts the current through transistor T1 until it is equal to the input current Ii. The current through transistor T1 is copied to the second terminal 6 by the transistor T2. The DC current transfer characteristic of this arrangement therefore is the same as given in equation 5a. The transistors T1 and T2 are operated in common-base configuration and thus have a large bandwidth. Assuming that the transconductance stage TS also has a large bandwidth, which is generally the case, the dominant pole is located at the first input terminal 2 of the current mirror. As a result, this configuration offers the advantageous possibility of a single pole design.

[0035] The input resistance Γ1 of the FIG. 5 current mirror is given by: 7$\begin{array}{cc}{r}_i=\frac{2}{g_m}& \left(6\right)\end{array}$

[0036] where gm is the transconductance of the transconductance stage TS. The factor 2 in the equation 6 is due to the fact that the output current of the transconductance stage TS is halved by the transistors T1 and T2. The input resistance Γ1 and the input capacitance C1 form a pole which dictates the bandwidth fh of the FIG. 5 current mirror. This bandwidth is given by: 8$\begin{array}{cc}\mathrm{fh}=\frac{1}{2\pi ·C_i·r_i}=\frac{g_m/2}{2\pi ·C_i}& \left(7\right)\end{array}$

[0037] If the transconductance gm is independent of the input current I1, the bandwidth fh is also independent of the input current.

[0038] FIG. 6 shows an example of the transconductance stage TS with a transistor T3, which has its base coupled to the first terminal 2, its collector coupled to the common terminal 8 and its emitter coupled to ground 10. A bias current source 26 is also coupled to the common terminal 8 to provide a bias current Ib. The transconductance gm of the transistor T3 is made independent of the input current I1 by adding the bias current Ib to the collector of transistor T3. In that case the transconductance gm of the transistor T3 is given by: 9$\begin{array}{cc}{g}_m=\frac{I_b+2I_{\iota }}{V_T}& \left(8\right)\end{array}$

[0039] By making the bias current Ib much larger than the input current I1 the input impedance will not change significantly with the input current I1. It is to be noted that the extra bias current Ib does not flow through the actual current mirror T1-T2 and does not affect the output current I0. In other words, the current mirror transfer characteristic and the input impedance can be optimized independently of each other. Because the input impedance, together with the input capacitor 12, determines the bandwidth, the bandwidth is also insensitive to the input current variations and can be optimized separately. The DC current transfer characteristic of the FIG. 6 current mirror is given by: 10$\begin{array}{cc}{I}_0=\left(I_i-\frac{I_b}{\beta }\right)·\left(1-\frac{2}{\beta }-\frac{2}{{\beta }^2}\right)& \left(9\right)\end{array}$

[0040] Instead of directly coupling the base of the transistor T3 to the first terminal 2, an emitter follower transistor T4 can be placed between them as shown in FIG. 7. The base of the transistor T4 is coupled to the first terminal 2 and the emitter of the transistor T4 drives the base of the transistor T3. A bias current source 28 supplies bias current to the emitter of transistor T4. This configuration with the emitter follower transistor T4 provides a larger voltage swing at the first terminal 2 within the mirror circuit itself at the cost of a higher DC input voltage level. FIG. 8 shows an alternative configuration in which transistor T4 is a MOSFET, which has the advantage that no current is drawn from the first terminal 2, resulting in a nearly perfect current mirror configuration with a 1 to 1 ratio between input current Ii and output current I0 (assuming equal transistors T1 and T2).

[0041] In the embodiments mainly bipolar transistors are shown. However, instead of bipolar transistors unipolar or MOSFET transistors can be used. In that case the gate, source and drain of the unipolar transistor substitute respectively the base, emitter and collector, of the bipolar transistor. Multiple outputs are possible by providing copies of the transistor T2 between the common terminal 8 and additional second terminals 6.

Claims

1. A current mirror comprising: a first terminal (2) for receiving an input current; a second terminal (6) for supplying an output current; a common terminal (8); a first transistor (T1) having a control electrode, and having a main current path arranged between the first terminal (2) and the common terminal (8); a second transistor (T2) having a control electrode connected to the control electrode of the first transistor (T1), and having a main current path arranged between the second terminal (6) and the common terminal (8), characterized in that the current mirror further comprises: a transconductance stage (TS) having an input terminal coupled to the first terminal (2), and having an output terminal coupled to the common terminal (8); and a bias source (22) for biasing the control electrode of the first transistor (T1) and the control electrode of the second transistor (T2).

2. A current mirror as claimed in claim 1, wherein the transconductance stage comprises a third transistor (T3) having a control electrode coupled to the first terminal (2), and having a main current path coupled between the common terminal (8) and a reference terminal (10).

3. A current mirror as claimed in claim 2, further comprising a buffer stage (T4) arranged between the first terminal (2) and the control terminal of the third transistor (T3).

4. A current mirror as claimed in claim 3, wherein the buffer stage comprises a fourth transistor (T4) operating as a voltage follower, the fourth transistor having a control electrode coupled to the first terminal (2), and having main electrode coupled to the control electrode of the third transistor (T3).

5. A current mirror as claimed in claim 4, wherein the first to the third transistor (T1, T2, T3) are bipolar transistors and the fourth transistor (T4) is a MOSFET transistor.

6. A current mirror as claimed in claim 2, 3, 4, or 5, further comprising a bias current source (26) coupled to the common terminal (8) to supply bias current to the common terminal (8).