Current mirror circuit

Description

BACKGROUND OF THE INVENTION

The invention relates to a current mirror comprising:

a first terminal for receiving an input current;

a second terminal for supplying an output current;

a common terminal;

a first transistor having a control electrode, and having a main current path arranged between the first terminal and the common terminal;

a second transistor having a control electrode connected to the control electrode of the first transistor, and having a main current path arranged between the second terminal and the common terminal.

Such a current mirror is known, for example, from U.S. Pat. No. 4,462,005 and is shown in FIG.

1

. In this well-known basic current mirror the interconnected control electrodes, in this case the bases, of the first transistor T

1

and the second transistor T

2

are connected to the first terminal which forms the current input terminal of the current mirror. The common terminal is connected to a reference terminal, in this case the negative supply terminal which serves as signal ground. As will be explained hereinafter, the bandwidth of this known current mirror strongly depends on the input current due to the presence of an input capacitance C

i

between the first terminal and the common terminal and of base-emitter capacitances C

be

of the first and the second transistor T

1

and T

2

. By adding degeneration resistors in series with the emitters of the first and the second transistor T

1

and T

2

, as shown in

FIG. 2

, the dependence on the input current can be avoided to some extent. However, this comes at the cost of a reduced bandwidth, an increased input impedance and a smaller voltage swing in comparison with to the basic current mirror of FIG.

1

.

It is known to obtain an improvement in bandwidth by adding a gain stage GS as shown in FIG.

3

.

FIG. 4

shows gain stage formed by means of an emitter follower EF between the first terminal and the interconnected control electrodes of the first and the second transistor T

1

and T

2

. This improved current mirror still has a bandwidth which depends on the input current.

SUMMARY OF THE INVENTION

Therefore, it is an object of the invention to provide a current mirror with improved performance. To obtain the above object, according to the present invention, the current mirror of the type defined in the opening paragraph is characterized in that the current mirror further comprises:

a transconductance stage having an input terminal coupled to the first terminal, and having an output terminal coupled to the common terminal;

and a bias source for biassing the control electrode of the first transistor and the control electrode of the second transistor.

The voltage at the first terminal is sensed by the transconductance stage which drives the common terminal. In this way a feedback loop is created which makes the current through the first transistor equal to the input current, thus providing a low input impedance. The first and the second transistor, assuming that they are bipolar transistors are, in common base configuration and provide a large bandwidth. Advantageous embodiments are defined in the dependent Claims.

BRIEF DESCRIPTION OF THE DRAWING

These and other aspects of the invention will be described and explained with reference to the appended drawings, in which:

FIG. 1

is a circuit diagram of a known current mirror;

FIG. 2

is a circuit diagram of a known current mirror;

FIG. 3

is a circuit diagram of a known current mirror;

FIG. 4

is a circuit diagram of a known current mirror;

FIG. 5

is a circuit diagram of a first embodiment of a current mirror in accordance with the invention;

FIG. 6

is a circuit diagram of a second embodiment of a current mirror in accordance with the invention;

FIG. 7

is a circuit diagram of a third embodiment of a current mirror in accordance with the invention; and

FIG. 8

is a circuit diagram of a fourth embodiment of a current mirror in accordance with the invention.

In these Figures parts having the same function or purpose are denoted by the same references.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1

shows a circuit diagram of the well-known basic current mirror. Bipolar transistors are shown which each have an emitter and a collector which define the main current path of the transistor, and which each have a base which acts as a control electrode for controlling the current through the main current path. The current mirror has a first terminal

2

for receiving an input current I

i

from an input current source

4

, a second terminal

6

for supplying a mirrored output current I

o

and common terminal

8

which is connected to signal ground

10

. The main current path of a first transistor T

1

is arranged between the first terminal

2

and the common terminal

8

, and the main current path of a second transistor T

2

is arranged between the second terminal

6

and the common terminal

8

. The emitters of the transistors T

1

and T

2

are connected to the common terminal

8

. The bases of the transistor T

1

and T

2

are interconnected and the interconnected bases are connected to the first terminal

2

. The current mirror has an input capacitor

12

between the first terminal

2

and ground

10

.

The DC current transfer characteristic of the current mirror is:

\begin{matrix} I_{o} = I_{i} (1 - \frac{2}{β + 2}) & (1) \end{matrix}

where β is the current gain of the transistors T

1

and T

2

. The bandwidth fh of this current mirror strongly depends on the input current I

i

and can be calculated with the following equation (2):

\begin{matrix} fh = \frac{g_{m}}{2 π \cdot (C_{i} + 2 C_{be})} = \frac{I_{i}}{2 π \cdot (C_{i} + 2 C_{be}) \cdot V_{T}} & (2) \end{matrix}

where g

m

=I

i

/V

T

is the small signal transconductance of the transistor T

1

, C

i

the capacitance of input capacitor

12

, C

be

the base-emitter capacitance of the transistors T

1

and T

2

and V

T

the thermal voltage of a bipolar transistor. From equation 2 it is apparent that the bandwidth fh is directly proportional to the input current I

i

. This dependence can be reduced by applying emitter degeneration as shown in FIG.

2

. Degeneration resistors

14

and

16

are arranged in the emitter leads of the transistors T

1

and T

2

, respectively. The bandwidth fh for this configuration can be calculated with the following equation:

\begin{matrix} fh = \frac{1}{2 π \cdot (C_{i} + 2 C_{be}) \cdot (R_{e} + r_{e})} = \frac{1}{2 π \cdot (C_{i} + 2 C_{be}) \cdot (R_{e} + \frac{V_{T}}{I_{i}})} & (3) \end{matrix}

where r

e

=1/g

m

of the transistor T

1

, and R

e

the resistance of the degeneration resistor

14

. If R

e

>>r

e

, the bandwidth fh is mainly determined by the values of the capacitors and the degeneration resistor. The reduced input current dependence comes at the cost of a smaller bandwidth, an increased input impedance and a smaller voltage swing in comparison with the basic current mirror of FIG.

1

.

FIG. 3

shows a known improved current mirror. The direct connection between the first terminal

2

and the interconnected bases is replaced with a gain stage GS, which has a non-inverting input connected to the first terminal

2

, an inverting input connected to a reference voltage source

18

and an output connected to the interconnected bases. The input impedance r

i

of this current mirror is given by:

\begin{matrix} r_{i} = \frac{1}{A \cdot g_{m1}} = \frac{1}{A} \cdot \frac{V_{T}}{I_{i}} & (4) \end{matrix}

where A is the gain of the gain stage GS and g

m1

the transconductance of the transistor T

1

. The input impedance r

i

together with the capacitance C

i

of the input capacitor

12

form a pole which determines the bandwidth fh of the current mirror, and is given by:

\begin{matrix} fh = \frac{1}{2 π \cdot C_{i} \cdot r_{i}} = \frac{A \cdot I_{i}}{2 π \cdot C_{i} \cdot V_{T}} & (5) \end{matrix}

Compared with the bandwidth of the basic current mirror in equation 2, the bandwidth fh has increased owing to the gain A and the missing capacitance C

be

, but is still proportional to the input current I

i

. Again, emitter degeneration can be applied just as in the basic current mirror at the same cost of bandwidth, input impedance and voltage swing.

FIG. 4

shows a version of the current mirror of

FIG. 3

in which the gain stage is an emitter follower transistor EF which has its base connected to the first terminal

2

, its emitter connected to the interconnected bases of the transistors T

1

and T

2

and to a bias current source

20

. Owing to the high gain A the DC transfer characteristic of the current mirror of

FIG. 3

is:

I

o

=I

i

(5a)

while the DC current gain of the current mirror of

FIG. 4

is given by:

\begin{matrix} I_{o} = (I_{i} - \frac{I_{e}}{β + 1}) \cdot (1 - \frac{2}{β^{2} + 1}) & (5b) \end{matrix}

where I

e

is the current of bias current source

20

.

FIG. 5

shows a current mirror in accordance with the invention. The interconnected bases of the transistors T

1

and T

2

are biased by a bias source

22

. The current mirror further has a transconductance stage TS which has an inverting input coupled to the first terminal

2

, a non-inverting input to a bias source

24

and a current output to the common terminal

8

. The voltage at the first terminal

2

is sensed by the transconductance stage TS, which drives the emitter of transistor T

1

. The feedback loop thus formed adjusts the current through transistor T

1

until it is equal to the input current I

i

. The current through transistor T

1

is copied to the second terminal

6

by the transistor T

2

. The DC current transfer characteristic of this arrangement therefore is the same as given in equation 5a. The transistors T

1

and T

2

are operated in common-base configuration and thus have a large bandwidth. Assuming that the transconductance stage TS also has a large bandwidth, which is generally the case, the dominant pole is located at the first input terminal

2

of the current mirror. As a result, this configuration offers the advantageous possibility of a single pole design.

The input resistance r

i

of the

FIG. 5

current mirror is given by:

\begin{matrix} r_{i} = \frac{2}{g_{m}} & (6) \end{matrix}

where g

m

is the transconductance of the transconductance stage TS. The factor

2

in the equation 6 is due to the fact that the output current of the transconductance stage TS is halved by the transistors T

1

and T

2

. The input resistance r

i

and the input capacitance C

i

form a pole which dictates the bandwidth fh of the

FIG. 5

current mirror. This bandwidth is given by:

\begin{matrix} fh = \frac{1}{2 π \cdot C_{i} \cdot r_{i}} = \frac{g_{m} / 2}{2 π \cdot C_{i}} & (7) \end{matrix}

If the transconductance g

m

is independent of the input current I

i

, the bandwidth fh is also independent of the input current.

FIG. 6

shows an example of the transconductance stage TS with a transistor T

3

, which has its base coupled to the first terminal

2

, its collector coupled to the common terminal

8

and its emitter coupled to ground

10

. A bias current source

26

is also coupled to the common terminal

8

to provide a bias current I

b

. The transconductance g

m

of the transistor T

3

is made independent of the input current I

i

by adding the bias current I

b

to the collector of transistor T

3

. In that case the transconductance g

m

of the transistor T

3

is given by:

\begin{matrix} g_{m} = \frac{I_{b} + 2 I_{i}}{V_{T}} & (8) \end{matrix}

By making the bias current I

b

much larger than the input current I

i

the input impedance will not change significantly with the input current I

i

. It is to be noted that the extra bias current I

b

does not flow through the actual current mirror T

1

-T

2

and does not affect the output current I

o

. In other words, the current mirror transfer characteristic and the input impedance can be optimized independently of each other. Because the input impedance, together with the input capacitor

12

, determines the bandwidth, the bandwidth is also insensitive to the input current variations and can be optimized separately. The DC current transfer characteristic of the

FIG. 6

current mirror is given by:

\begin{matrix} I_{0} = (I_{i} - \frac{I_{b}}{β}) \cdot (1 - \frac{2}{β} - \frac{2}{β^{2}}) & (9) \end{matrix}

Instead of directly coupling the base of the transistor T

3

to the first terminal

2

, an emitter follower transistor T

4

can be placed between them as shown in FIG.

7

. The base of the transistor T

4

is coupled to the first terminal

2

and the emitter of the transistor T

4

drives the base of the transistor T

3

. A bias current source

28

supplies bias current to the emitter of transistor T

4

. This configuration with the emitter follower transistor T

4

provides a larger voltage swing at the first terminal

2

within the mirror circuit itself at the cost of a higher DC input voltage level.

FIG. 8

shows an alternative configuration in which transistor T

4

is a MOSFET, which has the advantage that no current is drawn from the first terminal

2

, resulting in a nearly perfect current mirror configuration with a 1 to 1 ratio between input current I

i

and output current I

o

(assuming equal transistors T

1

and T

2

).

In the embodiments mainly bipolar transistors are shown. However, instead of bipolar transistors unipolar or MOSFET transistors can be used. In that case the gate, source and drain of the unipolar transistor substitute respectively the base, emitter and collector, of the bipolar transistor. Multiple outputs are possible by providing copies of the transistor T

2

between the common terminal

8

and additional second terminals

6

.

Claims

1. A current mirror comprising:a first terminal for receiving an input current; a second terminal for supplying an output current; a common terminal; a first transistor having: a control electrode, and a main current path arranged between the first terminal and the common terminal; a second transistor having: a control electrode connected to the control electrode of the first transistor, and a main current path arranged between the second terminal and the common terminal, characterized in that the current mirror further comprises: a transconductance stage having: an input terminal coupled to the first terminal, and an output terminal coupled to the common terminal; and a bias source that is independent of the input current, and is configured to bias the control electrode of the first transistor and the control electrode of the second transistor to a bias voltage that differs from a voltage at the common terminal.
2. A current mirror comprising:a first terminal for receiving an input current; a second terminal for supplying an output current; a common terminal; a first transistor having: a control electrode, and a main current path arranged between the first terminal and the common terminal; a second transistor having: a control electrode connected to the control electrode of the first transistor, and a main current path arranged between the second terminal and the common terminal, characterized in that the current mirror further comprises: a transconductance stage having: an input terminal coupled to the first terminal, and an output terminal coupled to the common terminal; and a bias source that is independent of the input current, and is configured to bias the control electrode of the first transistor and the control electrode of the second transistor, and the transconductance stage comprises: a third transistor having a control electrode coupled to the first terminal, and a main current path coupled between the common terminal and a reference terminal.
3. A current mirror as claimed in claim 2, further comprisinga buffer stage arranged between the first terminal and the control terminal of the third transistor.
4. A current mirror as claimed in claim 3, whereinthe buffer stage comprises a fourth transistor operating as a voltage follower, the fourth transistor having: a control electrode coupled to the first terminal, and a main electrode coupled to the control electrode of the third transistor.
5. A current mirror as claimed in claim 4, whereinthe first, the second, and the third transistor are bipolar transistors and the fourth transistor is a MOSFET transistor.
6. A current mirror as claimed in claim 5, further comprisinga bias current source coupled to the common terminal to supply bias current to the common terminal.
7. A current mirror as claimed in claim 4, further comprisinga bias current source coupled to the common terminal to supply bias current to the common terminal.
8. A current mirror as claimed in claim 3, further comprisinga bias current source coupled to the common terminal to supply bias current to the common terminal.
9. A current mirror as claimed in claim 2, further comprisinga bias current source coupled to the common terminal to supply bias current to the common terminal.
10. A current mirror as claimed in claim 1, further comprisinga bias current source coupled to the common terminal to supply bias current to the common terminal.

Priority Claims (1)

Number	Date	Country	Kind
98203917	Nov 1998	EP

US Referenced Citations (6)

Number	Name	Date
4462005	Kusakabe et al.	Jul 1984
4563632	Palara et al.	Jan 1986
4574233	Taylor	Mar 1986
5629614	Choe et al.	May 1997
5666046	Mietus	Sep 1997
6124754	Afghabi	Sep 2000

Current mirror circuit

Information

Patent Number

Date Filed

Date Issued

Inventors

Original Assignees

Examiners

Agents

CPC

US Classifications

Field of Search

US

International Classifications

Abstract

Description

Claims

Priority Claims (1)

US Referenced Citations (6)