Claims
- 1. A driver circuit for providing a pair of inversely-related first and second predistorted control voltages to an amplifier circuit, the driver circuit comprising:
- a first current mirror circuit that provides a first predistortion current substantially proportional to a control current when the control current falls within a first predetermined range, the first predistortion current being offset by a first offset amount from its ideal proportional level when the control current falls outside the first predetermined range;
- a second current mirror circuit that receives a differential current, equivalent to the amount by which a reference current exceeds the control current, and that provides a second predistortion current substantially proportional to the differential current when the differential current falls within a second predetermined range, the second predistortion current being offset by a second offset amount from its ideal proportional level when the differential current falls outside the second predetermined range; and
- a predistortion circuit that provides (1) the first predistorted control voltage in response to the first predistortion control current being output by the first current mirror circuit and (2) the second predistorted control voltage in response to the second predistortion control current being output by the second current mirror circuit.
- 2. The driver circuit of claim 1 wherein the predistortion circuit substantially implements a hyperbolic tangent function.
- 3. The driver circuit of claim 1 further comprising:
- a first operational amplifier circuit for generating the control current proportional to a control voltage; and
- a second operational amplifier circuit for generating the reference current substantially equal to a level indicative of maximum control current.
- 4. The driver circuit of claim 1 further comprising a third current mirror circuit for providing a mirror control current proportional to the control current, the third current mirror circuit being coupled to the second current mirror circuit which receives the differential current.
- 5. A method of providing first and second differential control voltages to an amplifier circuit, the method comprising the steps of:
- receiving a control signal;
- providing a first control current substantially proportional to the control signal, the first control current being within a first predetermined range and being offset by a first offset amount when the control signal falls outside the first predetermined range;
- providing a second control current substantially inversely proportional to the control signal, the second control current being within a second predetermined range and being offset by a second offset amount when the second control signal falls outside the second predetermined range;
- generating the first differential control voltage from the difference between the first and second control currents; and
- generating the second differential control voltage from the difference between the second and first control currents, the second differential control voltage being substantially similar to the first differential control voltage.
- 6. A three-input amplifier circuit for controlling fading between first and second input signals and a control signal, the amplifier comprising:
- a control circuit for providing a first control current that is proportional to the control signal and a second control current, such that the second control current is a function of the first control current;
- a predistortion circuit coupled to the control circuit to provide four control voltages in response to the first and second control currents being output by the control circuit;
- a first input stage for receiving the first input signal;
- a second input stage for receiving the second input signal;
- an output stage for providing an output signal;
- first and second cross-coupled multiplier stages, the first multiplier stage being coupled to the predistortion circuit to receive first and second control voltages, the second multiplier stage being coupled to the predistortion circuit to receive third and fourth control voltages, the multiplier stages also being coupled to the first and second input stage and the output stage, the multiplier stages appropriately steering the first and second input signals to the output stage in response to the control voltages provided by the predistortion circuit.
- 7. A two-input amplifier circuit for controlling fading between first and second input signals, the amplifier comprising:
- a control circuit for providing a first and a second control current;
- a predistortion circuit coupled to the control circuit to provide four control voltages in response to the first and second control currents being output by the control circuit;
- a first input stage for receiving the first input signal;
- a second input stage for receiving the second input signal;
- an output stage for providing an output signal;
- first and second cross-coupled multiplier stages, the first multiplier stage being coupled to the predistortion circuit to receive first and second control voltages, the second multiplier stage being coupled to the predistortion circuit to receive third and fourth control voltages, the multiplier stages also being coupled to the first and second input stage, the multiplier stages appropriately steering the first and second input signals to the output stage in response to the control voltages provided by the predistortion circuit, wherein the multiplier stages steer only the first input signal to the output stage when the first control current exceeds the second control current by a predetermined amount.
- 8. A two-input amplifier circuit for controlling fading between first and second input signals, the amplifier comprising:
- a control circuit for providing a first and a second control current;
- a predistortion circuit coupled to the control circuit to provide four control voltages in response to the first and second control currents being output by the control circuit;
- a first input stage for receiving the first input signal;
- a second input stage for receiving the second input signal;
- an output stage for providing an output signal;
- first and second cross-coupled multiplier stages, the first multiplier stage being coupled to the predistortion circuit to receive first and second control voltages, the second multiplier stage being coupled to the predistortion circuit to receive third and fourth control voltages, the multiplier stages also being coupled to the first and second input stage, the multiplier stages appropriately steering the first and second input signals to the output stage in response to the control voltages provided by the predistortion circuit, wherein the multiplier stages steer only the second input signal to the output stage when the second control current exceeds the first control current by a predetermined amount.
- 9. A two-input amplifier circuit for controlling fading between first and second input signals, the amplifier comprising:
- a control circuit for providing a first and a second control current;
- a predistortion circuit coupled to the control circuit to provide four control voltages in response to the first and second control currents being output by the control circuit;
- a first input stage for receiving the first input signal;
- a second input stage for receiving the second input signal;
- an output stage for providing an output signal;
- first and second cross-coupled multiplier stages, the first multiplier stage being coupled to the predistortion circuit to receive first and second control voltages, the second multiplier stage being coupled to the predistortion circuit to receive third and fourth control voltages, the multiplier stages also being coupled to the first and second input stage, the multiplier stages appropriately steering the first and second input signals to the output stage in response to the control voltages provided by the predistortion circuit, wherein the multiplier stages steer a proportional combination of the first input signal and the second input signal to the output stage when the first control current does not exceed the second control current by a first predetermined amount and the second control current does not exceed the first control current by a second predetermined amount.
- 10. A two-input amplifier circuit for controlling fading between first and second input signals, the amplifier comprising:
- a control circuit for providing a first and a second control current, the control circuit including:
- a first current mirror circuit for providing the first control current at a current which is substantially proportional to a control signal when the control signal falls within a first predetermined range, the first control current being offset by a first offset amount from its ideal proportional level when the control signal falls outside the first predetermined range;
- a second current mirror circuit for monitoring a differential signal, equivalent to the amount by which a reference signal exceeds the control signal, and for providing the second control current at a current which is substantially proportional to the differential signal when the differential signal falls within a second predetermined range, the second control current being offset by a second offset amount from its ideal proportional level when the differential signal falls outside the second predetermined range;
- a predistortion circuit coupled to the control circuit to provide four control voltages in response to the first and second control currents being output by the control circuit;
- a first input stage for receiving the first input signal;
- a second input stage for receiving the second input signal;
- an output stage for providing an output signal;
- first and second cross-coupled multiplier stages, the first multiplier stage being coupled to the predistortion circuit to receive first and second control voltages, the second multiplier stage being coupled to the predistortion circuit to receive third and fourth control voltages, the multiplier stages also being coupled to the first and second input stage, the multiplier stages appropriately steering the first and second input signals to the output stage in response to the control voltages provided by the predistortion circuit.
- 11. A two-input amplifier circuit for controlling fading between first and second input signals, the amplifier comprising;
- a control circuit for providing a first and a second control current;
- a predistortion circuit coupled to the control circuit to provide four control voltages in response to the first and second control currents being output by the control circuit;
- a first input stage for receiving the first input signal;
- a second input stage for receiving the second input signal;
- an output stage for providing an output signal;
- first and second cross-coupled multiplier stages, the first multiplier stage being coupled to the predistortion circuit to receive first and second control voltages, the second multiplier stage being coupled to the predistortion circuit to receive third and fourth control voltages, the multiplier stages also being coupled to the first and second input stage, the multiplier stages appropriately steering the first and second input signals to the output stage in response to the control voltages provided by the predistortion circuit, wherein the predistortion circuit includes:
- first and second PNP transistors coupled to the first multiplier stage, the PNP transistors having commonly coupled bases, the first PNP transistor providing the first control voltage and the second PNP transistor providing the second control voltage; and
- first and second NPN transistors coupled to the second multiplier stage, the first NPN transistor being coupled to the collector of the first PNP transistor for providing the third control voltage, the second NPN transistor being coupled to the second PNP transistor for providing the fourth control voltage.
- 12. The amplifier circuit of claim 6, wherein the output stage comprises:
- an output buffer for providing the output signal;
- a first current mirror coupled to the first multiplier stage and to the output buffer; and
- a second current mirror coupled to the second multiplier stage and to the output buffer.
- 13. The amplifier circuit of claim 6, wherein the first multiplier stage comprises:
- first and second NPN transistors having emitters commonly coupled to the first input stage, the first NPN transistor having a base coupled to the predistortion circuit to receive the second control voltage and a collector coupled to a positive reference voltage supply, the second NPN transistor having a base coupled to the predistortion circuit to receive the first control voltage and a collector coupled to the output stage; and
- third and fourth NPN transistors having emitters commonly coupled to the second input stage, the third NPN transistor having a base coupled to the predistortion circuit to receive the first control voltage and a collector coupled to a positive reference voltage supply, the fourth NPN transistor having a base coupled to the predistortion circuit to receive the second control voltage and a collector coupled to the output stage.
- 14. The amplifier circuit of claim 6, wherein the second multiplier stage comprises:
- first and second PNP transistors having emitters commonly coupled to the first input stage, the first PNP transistor having a base coupled to the predistortion circuit to receive the fourth control voltage and a collector coupled to a negative reference voltage supply, the second PNP transistor having a base coupled to the predistortion circuit to receive the third control voltage and a collector coupled to the output stage; and
- third and fourth PNP transistors having emitters commonly coupled to the second input stage, the third PNP transistor having a base coupled to the predistortion circuit to receive the third control voltage and a collector coupled to a negative reference voltage supply, the fourth PNP transistor having a base coupled to the predistortion circuit to receive the fourth control voltage and a collector coupled to the output stage.
- 15. An amplifier circuit for amplifying at least: (1) a first input signal and a first feedback signal; and (2) a second input signal and a second feedback signal, the amplifier circuit comprising:
- a first input stage including a first PNP transistor coupled to a first NPN transistor, the first PNP and NPN transistors being driven by the first input signal and for being coupled to receive the first feedback signal, one of the first transistors providing a first driver signal and the other first transistor providing a second driver signal;
- a second input stage including a second PNP transistor coupled to a second NPN transistor, the second PNP and NPN transistors being driven by the second input signal and for being coupled to the second feedback signal, one of the second transistors providing a third driver signal and the other second transistor providing a fourth driver signal;
- a first cross-coupled multiplier circuit comprising:
- first and second current steering transistors being coupled to receive the first driver signal from the first input stage, and
- third and fourth current steering transistors being coupled to receive the third driver signal from the second input stage; and
- a second cross-coupled multiplier circuit comprising:
- fifth and sixth current steering transistors being coupled to receive the second driver signal from the first input stage, and
- seventh and eighth current steering transistors being coupled to receive the fourth driver signal from the second input stage; and
- an output stage which produces an amplified output signal in response to the four driver signals being received by the multiplier circuits.
- 16. The amplifier circuit of claim 15 wherein the second and fourth current steering transistors, having commonly coupled collectors, provide a first current output signal to the output stage, and wherein the sixth and eighth current steering transistors, having commonly coupled collectors, provide a second current output signal to the output stage.
- 17. The amplifier circuit of claim 15 wherein all of the transistors in the first cross-coupled multiplier are of a type from the group of NPN transistors and PNP transistors and all of the transistors in the second cross-coupled multiplier are of the other type.
- 18. The amplifier circuit of claim 15, wherein:
- the bases of the second and third current steering transistors are commonly driven by a first predistorted control voltage;
- the bases of a the first and fourth current steering transistors are commonly driven by a second predistorted control voltage;
- the bases of the sixth and seventh transistors are commonly driven by a third predistorted control voltage; and
- the bases of the fifth and eighth transistors are commonly driven by a fourth predistorted control voltage; and wherein:
- the gain-controlled amplifier circuit further comprises a driver circuit to provide said first, second, third, and fourth predistorted control voltages.
- 19. The circuit of claim 18 wherein the driver circuit comprises:
- a first current mirror circuit that provides a first predistortion current in response to a control current being applied to the first current mirror circuit;
- a second current mirror circuit that receives a differential current, equivalent to an amount by which a reference current exceeds the control current, and provides a second predistortion current in response to the differential current being received; and
- a predistortion circuit for providing: (1) the first and third predistorted control voltages in response to the first predistortion control current being output by the first current mirror circuit; and (2) the second and fourth predistorted control voltages in response to the second predistortion control current being output by the second current mirror circuit.
- 20. The circuit of claim 19 wherein the predistortion circuit substantially implements a hyperbolic tangent function, whereby: (1) the first and third predistorted control voltages are related to the first predistortion control current by the hyperbolic tangent function; and (2) the second and fourth predistorted control voltages are related to the second predistortion control current by the hyperbolic tangent function.
- 21. The circuit of claim 19 wherein the driver circuit further comprises:
- a first operational amplifier circuit for generating the control current proportional to a control voltage; and
- a second operational amplifier circuit for generating the reference current substantially equal to a maximum level of control current.
- 22. The circuit of claim 19, wherein the driver circuit further comprises a third current mirror circuit for providing a mirror control current proportional to the control current, the third current mirror circuit being coupled to the second current mirror circuit which receives the differential current.
- 23. The circuit of claim 19 wherein:
- the first current mirror circuit operates to provide the first predistortion current at a current which is substantially proportional to the control current when the control current falls within a first predetermined range, and to provide the first predistortion current at a current which is offset by a first offset amount from its ideal proportional level when the control current falls outside the first predetermined range; and
- the second current mirror circuit operates to provide the second predistortion current at a current which is substantially proportional to the differential current when the differential current falls within a second predetermined range, and to provide the second predistortion current at a current which is offset by a second offset amount from its ideal proportional level when the differential current falls outside the second predetermined range.
CROSS-REFERENCE TO RELATED APPLICATION
This application is a division of application Ser. No. 08/346,395, filed Nov. 29, 1994, now Pat. No. 5,517,143 entitled CURRENT MIRROR CIRCUITS AND METHODS WITH GUARANTEED OFF STATE AND AMPLIFIER CIRCUITS USING SAME.
US Referenced Citations (8)
Non-Patent Literature Citations (3)
Entry |
"Elantec EL4095C Video Gain Control/Fader/Multiplexer," Elantec, Inc. Data Sheet Rev. A, Milpitas, California, pp. 1-24, published Aug. 1993. |
"Gennum GT4123, GT4123A Two Channel Video Multipliers," Gennum Corporation Preliminary Data Sheet, Canada, pp. 1-5, published Jun. 1992. |
"Linear Technology LT1251/LT1256 40 MHz Video Fader and DC Gain Controlled Amplifier," Linear Technology Corporation Data Sheet, Milpitas, California, pp. 1-24, published May 1994. |
Divisions (1)
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Number |
Date |
Country |
Parent |
346395 |
Nov 1994 |
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