Patent Application
20130154714
The present disclosure pertains generally to switched mode regulators, and more specifically to a current-mode sample and hold circuit for dead time control of switched mode regulators.
In a switched-mode regulator, “dead-time” refers to the time between when the output PMOS switch turns off and the output NMOS switch turns on. The output switching node capacitance requires a certain amount of time to discharge, which is proportional to the regulator load current. Internal monitoring circuitry is typically used to provide a current signal which is scaled copy of the regulator load current. To optimize the dead-time (and minimize the efficiency loss due to dead-time), the delay is controlled.
A system for current mode sample and hold, comprising a first PMOS transistor configured to generate a current to be sampled. A diode-connected NMOS transistor coupled to the first PMOS transistor and configured to receive the current. A switch coupled to the diode-connected NMOS transistor and configured to sample a gate-source voltage of the diode-connected NMOS transistor. A capacitor coupled to the switch and configured to stored the gate-source voltage of the diode-connected NMOS transistor. A second NMOS transistor coupled to the capacitor and configured to generate a current equal to the sampled current value.
Other systems, methods, features, and advantages of the present disclosure will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present disclosure, and be protected by the accompanying claims.
Aspects of the disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views, and in which:
In the description that follows, like parts are marked throughout the specification and drawings with the same reference numerals. The drawing figures might not be to scale and certain components can be shown in generalized or schematic form and identified by commercial designations in the interest of clarity and conciseness.
Power efficiency is an important performance metric for switched mode regulators. For example, the internal circuitry of the regulator should consume as little power as possible. Nevertheless, a complex assortment of internal housekeeping circuitry has been used to monitor performance and to control modes of operation of state of switched mode regulators.
There are several operating characteristics of switched mode regulators that degrade efficiency. One of these characteristics is the time duration from when the PMOS output power switch turns off to when the NMOS power switch turns on. This time-duration is called the ‘dead-time,’ which refers to the time between when the output PMOS switch turns off and the NMOS switch turns on.
The output switching node capacitance requires an amount of time to discharge that is proportional to the regulator load current. Internal monitoring circuitry can be used to provide a current signal which is a scaled copy of the regulator load current. In order to optimize the dead-time (and minimize the efficiency loss due to dead-time), the delay can be controlled through analog means, with dead-time delay circuitry that makes use of the scaled output load current to control the dead-time delay.
It is desirable to keep the dead-time as small as possible, since during that time, a parasitic body diode can conduct current from ground through the inductor to the output load. The forward-biased body diode VBE and the current that is conducted constitute a power loss that can be avoided, such as by turning on the NMOS stitch as soon as possible (and minimizing the dead-time) to lower the voltage drop from a forward-biased diode VBE (˜0.7v), to that of the NMOS power switch VDS (˜0.1V), thus resulting in a reduction in power loss and improvement in efficiency.
The minimum amount of time that the NMOS switch can be turned on is limited by how long it takes the output switching node to turn off. This amount of time is proportional to the load current being delivered during that particular switching cycle. Other monitoring circuitry provides a scaled-copy of the load current called the ‘load-sense’ current, which can be used to control the non-overlapping dead-time. Previously, other solutions have taken the load-sense current and converted it to a voltage, so that it can be sampled and held with a commonly used voltage-mode sample and hold circuit. The sampled and held voltage copy of the load sense current is then converted back to current mode to control a current-starved delay element circuit to control the dead-time.
Dead-time delay control circuitry can be implemented with controllable current-starved inverter delays, where the delay control can have a fixed component and a variable component. The variable component can be derived from the ‘scaled’ load current information. In order for the ‘scaled’ load current signal to be used, it should be sampled and held constant for each switch mode regulator cycle. Sampling of this load current information is performed with a sample and hold circuit.
Power MOS module 102 includes NMOS and PMOS power switches. These switches are turned on by pulses having a predetermined pulse width, where the on state of the switches must not overlap in order to prevent damage. However, because the on state of the switches is also a function of the load, the pulse width cannot be static, but must vary as a function of the load. The time duration from when the PMOS output power switch turns off to when the NMOS power switch turns on is called the “dead-time.” It is generally desirable to keep the dead-time as small as possible, since during that time, a parasitic body diode can conduct current from ground through the inductor to the output load. A forward-biased body diode VBE and the current that is conducted through it constitute a power loss, which can be avoided as discussed herein. Turning on the NMOS power switch as soon as possible (and minimizing the dead-time) lowers the voltage drop from a forward-biased diode VBE (˜0.7v), to that of the NMOS power switch VDS (˜0.1V), thus resulting in a reduction in power loss and improvement in efficiency.
Width control 104 receives inputs from current mode sample and hold 106 and dead time control 108 and generates width control for the pulses generated by power MOS module 102, and otherwise drives the operation of the NMOS and PMOS power switches.
Current mode sample and hold 106 receives output current sensing signals from power MOS module 102 and generates a held current output. Current mode sample and hold 106 avoids the need to convert a sampled current to a voltage for sampling and holding, and instead uses a current sampling circuit that provides improved efficiency.
Dead time control 108 receives outputs from current mode sample and hold 106 and tri-mode controller 112 and generates an output to width control 104 to reduce the amount of dead time between when a PMOS output power switch of power MOS module 102 turns off to when the NMOS power switch turns on. As previously discussed, the pulse width is a function of the load being provided by the power MOS module 102.
Tri-mode controller 112 receives an output from mode decoder 114 and dither 166 and generates pulse width modulation, dithering skip modulation and pulse frequency modulation control signals.
Mode decoder 114 and dither 116 receive an output from current mode sample and hold 106 and generate dithering skip pulses and other suitable outputs for tri-mode controller 112.
In operation, system provides for current mode sample and hold for use in a switched mode regulator, which eliminates the need to convert a sampled current value to a voltage, to store the voltage, and then to convert the voltage back to a current value. By using diode-connected matched FET devices, the gate voltage of an input device (which corresponds to the current flowing through the device) can be stored and used to set the gate voltage of an output device, so as to allo for current mode sample and hold.
Algorithm 300 begins at 302, where a current to be sampled is received at an input device. In one exemplary embodiment, the input transistor can be a diode-connected NFET transistor, a diode-connected PFET transistor or other suitable devices. The algorithm then proceeds to 304.
At 304, a sample switch is actuated. In one exemplary embodiment, a sample control can be generated based on input voltage and current values from a power MOS module, based on timing data, or based on other suitable data, in order to sample a current value, such as a load current value or other suitable current values. The algorithm then proceeds to 306.
At 306, a parameter is stored, such as a gate to source voltage or other suitable parameters. In one exemplary embodiment, a diode-connected NFET can be used as the input device and a gate-source voltage of the diode-connected NFET can be stored, such as by using a storage capacitance that is connected in parallel with the diode-connected NFET. The algorithm then proceeds to 308, where the parameter is applied to an output device, such as NFET The algorithm then proceeds to 310 where a current is provided to a delay. The algorithm then proceeds to 312 where it is determined whether a new switch mode regulator cycle is occurring. If a new cycle is occurring, the algorithm returns to 302, otherwise, the algorithm remains at 312.
A diode-connected PMOS transistor in the current mode sample and hold stage is connected to a PMOS transistor in the a control current signal conditioning and scaling stage, which generates a current that is provided to an NMOS transistor.
The control current signal conditioning and scaling stage receives the load dependent current IS and generates a conditioned and scaled delay current IDELAY that equals IS plus a first bias current IB and minus a second bias current IB1. The bias currents IB and IB1 are used to provide control current signal condition and scaling. The magnitude of IB should be such that at an average load current, the variable POFF to NON is optimized for maximum power efficiency. The minimum value of IDELTA is set by the value of IB1, and the maximum value is set by IS-IB1. For symmetrical delay variation, IB1 can be half of the maximum value of IS. The value of IDELTA is typically a small fraction of IDELAY, and appropriate for the variation of POFF to NON delay as a function of regulator load current.
The controllable delay for P off to N on dead time stage provides a suitable number of controllable delay stages for processing the sampled current, and provides inputs to the non-overlapping power switch control stage, which generates the NFET and PFET control signals. A stage for generating a fixed delay for non-critical N off to P on dead time is also provided.
In operation, system 400 provides for current mode sample and hold for use in a switched mode regulator, which eliminates the need to convert a sampled current value to a voltage, to store the voltage, and then to convert the voltage back to a current value. By using diode-connected matched FET devices, the gate voltage of an input device (which corresponds to the current flowing through the device) can be stored and used to set the gate voltage of an output device, so as to allow for current mode sample and hold.
It should be emphasized that the above-described embodiments are merely examples of possible implementations. Many variations and modifications may be made to the above-described embodiments without departing from the principles of the present disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims.
The present application claims priority to U.S. Provisional application 61/578,213, filed Dec. 20, 2011, entitled “CURRENT-MODE SAMPLE AND HOLD FOR DEAD TIME CONTROL OF SWITCHED MODE REGULATORS,” which is hereby incorporated by reference for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 61578213 | Dec 2011 | US |
