CURRENT SENSING IN A DISK-DRIVE SPINDLE MOTOR

Abstract

One embodiment of the invention includes a disk-drive spindle motor power regulator system. The system includes a switching system comprising at least one power transistor for each of a plurality of phases of a disk-drive spindle motor. The system also includes a switching controller configured to generate a plurality of switching signals configured to control the at least one power transistor for each of the plurality of phases of the disk-drive spindle motor. The system further includes a current monitor configured to measure a magnitude of an individual phase current through at least one of the plurality of phases of the disk-drive spindle motor.

Description

TECHNICAL FIELD

This invention relates to electronic circuits, and more specifically to current sensing in a disk-drive spindle motor.

BACKGROUND

There is an ever increasing demand for power conversion and regulation circuitry to operate with increased efficiency and reduced power to accommodate the continuous reduction in size of electronic devices. Switching regulators have been implemented as an efficient mechanism for providing a regulated output in power supplies. One such of regulator is known as a switching regulator or switching power supply, which controls the flow of power to a load by controlling the on and off duty-cycle of one or more switches coupled to the load. Many different classes of switching regulators exist today.

Switching regulators can be implemented in any of a variety of applications. One such application is in a control system for disk-drive spindle motors. It is sometimes desirable to be able to monitor a magnitude of current that flows through the switches of a switching regulator for a disk-drive spindle motor, such as to control a rotational speed of the disk-drive spindle motor. Some spindle motor power regulator integrated circuits (ICs) may incorporate additional input/output (I/O) pins to accommodate an external sense resistor and/or associated sensing circuitry. Such methods thus can be subject to additional cost and/or space to incorporate the additional I/O pins and the associated circuitry. In addition, typical current sensing schemes for spindle motor power regulators may incorporate a sense resistor that interconnects all of the low-side power transistors with ground or a common low voltage rail, such that the current that is sensed is an aggregate current of each of the phases of the spindle motor.

SUMMARY

One embodiment of the invention includes a disk-drive spindle motor power regulator system. The system includes a switching system comprising at least one power transistor for each of a plurality of phases of a disk-drive spindle motor. The system also includes a switching controller configured to generate a plurality of switching signals configured to control the at least one power transistor for each of the plurality of phases of the disk-drive spindle motor. The system further includes a current monitor configured to measure a magnitude of an individual phase current through at least one of the plurality of phases of the disk-drive spindle motor.

Another embodiment of the invention includes a method for measuring an individual phase current through at least one of a plurality of phases of a disk-drive spindle motor. The method includes generating a plurality of switching signals that control at least one power transistor for each of the plurality of phases of the disk-drive spindle motor and identifying which of at least one of the plurality of phases through which the respective individual phase current is to be measured based on the plurality of switching signals. The method also includes switching a plurality of reference currents corresponding to the respective individual phase current to a respective current sense system and measuring the magnitude of the respective individual phase current of the at least one of the plurality of phases based on the plurality of reference currents. The method further includes calculating a magnitude of one or more remaining phase currents based on the magnitude of the respective individual phase current.

Another embodiment of the invention includes a disk-drive spindle motor power regulator system. The system includes means for generating a plurality of switching signals associated with each of a first phase, a second phase, and a third phase, respectively, of the disk-drive spindle motor. The system also includes means for generating a first phase current, a second phase current, and a third phase current through the first, second, and third phases respectively, of the disk-drive spindle motor in response to the plurality of switching signals. The system further includes means for measuring a magnitude of two of the first, second, and third phase currents and means for calculating a magnitude of a remaining one of the first, second, and third phase currents based on the measured magnitude of the two of the first, second, and third phase currents.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example of a spindle motor power regulator system in accordance with an aspect of the invention.

FIG. 2 illustrates another example of a spindle motor power regulator system in accordance with an aspect of the invention.

FIG. 3 illustrates an example of a current-sense system in accordance with an aspect of the invention.

FIG. 4 illustrates an example of a high-side current-sense system in accordance with an aspect of the invention.

FIG. 5 illustrates an example of a phase switch and operational amplifier (OP-AMP) arrangement in accordance with an aspect of the invention.

FIG. 6 illustrates an example of a phase switch and OP-AMP system in accordance with an aspect of the invention.

FIG. 7 illustrates an example of a low-side current-sense system in accordance with an aspect of the invention.

FIG. 8 illustrates an example of a method for determining individual phase currents of a disk-drive spindle motor in accordance with an aspect of the invention.

DETAILED DESCRIPTION

The invention relates to electronic circuits, and more specifically to current sensing in a disk-drive spindle motor. As an example, the disk-drive spindle motor can be a permanent magnet three-phase synchronous DC motor with a center tap of windings that is floating or otherwise unconnected from a low-voltage power rail (e.g., ground). A disk-drive spindle motor power regulator system includes a switching controller that provides switching signals to a switching system. The switching system can include a set of one or more power transistors for each phase of the disk-drive spindle motor. Therefore, the switching controller can define a commutation state or cycle for the spindle motor through each set of switching signals to each of the respective sets of one or more power transistors to control the rotation of the spindle motor.

As an example, during each commutation cycle, two sets of switching signals corresponding to two of the phases of the spindle motor are pulse-width modulated (PWM) at a fixed PWM frequency. A PWM duty-cycle can be different for the sets switching signals, with one set of the switching signals having a greater duty-cycle than the other. The PWM duty-cycle can change for each of the two sets of the switching signals from one PWM period to another, but the relationship between the duty-cycles between the two sets of the switching signals can remain the same during the commutation cycle. Specifically, one of the sets of switching signals can have a PWM duty-cycle that is always greater than the other during the commutation cycle, and thus has a greatest duty-cycle in each PWM period of the commutation cycle. The third set of switching signals is provided to pull down the respective phase of the spindle motor to the ground during the commutation cycle, such that the third set of switching signals does not have a PWM duty-cycle. The sets of the switching signals thus control three separate phases of the spindle motor during each commutation cycle.

As described herein, the three phases of the spindle motor are the CAP phase, the SLOPE phase, and the GROUND phase. The respective phases of the spindle motor thus conduct a CAP phase current, a SLOPE phase current, and a GROUND phase current, respectively. The CAP phase and the SLOPE phase are each controlled by sets of the switching signals having a PWM duty-cycle. The PWM duty-cycle of the switching signals that control the CAP phase is greater than the set of switching signals that control the SLOPE phase. Thus, the CAP phase current is substantially constantly sourced to the spindle motor during the commutation cycle. The SLOPE phase current, however, changes direction during the commutation cycle. Thus, the SLOPE phase current is not constantly sourced to the spindle motor during the commutation cycle, but instead is sunk from the spindle motor during at least a portion of the commutation cycle. The switching signals that control the GROUND phase do not have a PWM duty-cycle. Thus, the GROUND phase current is substantially constantly sunk from the spindle motor during the commutation phase. The phases change from one commutation cycle to the next, such as to control the speed and torque of the spindle motor. Thus, the rotation and speed control of the spindle motor can be achieved by combining the proper different commutation states in sequence.

The power regulator system can also include a current monitor that is configured to measure a magnitude of an individual current flow through one or more of the phases of the spindle motor during each PWM cycle. The switching controller can identify which of the switching signals correspond to control of the associated phases of the spindle motor. Thus, the current monitor can measure the magnitude of the CAP phase current that is substantially constantly sourced to a first phase of the spindle motor during the commutation cycle. The current monitor can also measure the magnitude of the GROUND phase current that is substantially constantly sunk from a second phase of the spindle motor to the low-voltage power rail during the commutation cycle. The SLOPE phase current can be either a sourcing current or a sinking current, and the corresponding set of switching signals can have a duty-cycle that is very small. Therefore, the current monitor may not measure the SLOPE phase current.

The current monitor can include a current sense system for each of the phase currents that are to be measured (i.e., a high-side current sense system and a low-side current sense system). The current sense systems can each include one or more current sensing transistors, such as laterally-diffused metal-oxide semiconductor field-effect transistors (LDMOSFETs), that are configured to conduct a respective one or more reference currents in response to a control signal that controls the power transistor. The reference currents can be provided to an operational amplifier (OP-AMP) that is configured to generate a sense current that is substantially proportional to (i.e., highly linear with respect to) the output current. As an example, the current sense system can include sets of phase switches that direct the reference currents corresponding to the respective phase to the OP-AMP for measurement, and the OP-AMP can include a current control circuit that is configured to generate a sense voltage that is proportional to a magnitude of the respective phase current.

The current monitor can also include an analog-to-digital converter (ADC) that is configured to convert the sense voltage corresponding to each of the respective measured phase currents to a digital value. The digital sense voltages can thus be provided to a processor which can calculate a delivered power to the disk-drive spindle motor, and thus the speed of the disk-drive spindle motor. As an example, the current monitor can calculate a magnitude of the SLOPE phase current of the spindle motor based on the calculated magnitudes of the CAP and GROUND phase currents. The phase current magnitude information can thus be implemented by the processor to control and/or adjust the rotational speed and torque of the spindle motor, such as to control the spindle motor to rotate silently at a substantially constant speed.

FIG. 1 illustrates an example of a spindle motor power regulator system 10 in accordance with an aspect of the invention. The spindle motor power regulator system 10 can be implemented to control the rotational motion of a spindle motor 12. As an example, the spindle motor 12 can be a three-phase synchronous DC motor with a center tap of windings that is floating or otherwise unconnected from a low-voltage power rail (e.g., ground). The spindle motor 12 can be implemented in any of a variety of disk-drive systems. For example, the spindle motor 12 can be implemented in a magnetic disk-drive system such as a hard-disk-drive (HDD) or a peripheral disk-drive, or can be implemented in an optical disk-drive system, such as a compact disc (CD) drive, or a digital video disc (DVD) drive. In addition, the spindle motor power regulator system 10 can be implemented on or as a portion of an integrated circuit (IC).

The spindle motor power regulator system 10 includes a switching controller 14 that is configured to generate a plurality of switching signals SW. The switching signals SW are provided to a switching system 16 that is configured to control the flow of a set of phase currents through the respective phases of the spindle motor 12. In the example of FIG. 1, the set of phase currents are demonstrated as a current I_PH. The switching system 16 includes power transistors 18 that are responsive to the switching signals SW.

As an example, the switching signals SW can include a high-side switching signal and a low-side switching signal for each phase of the spindle motor 12. For example, the switching controller 14 can include a set of drivers for each of the phases of the spindle motor that generate the respective sets of the switching signals SW in response to one or more logic signals, such as to substantially mitigate a shoot-through current through the power transistors 18. As an example, the power transistors 18 can be LDMOSFETs (hereinafter “FETs”), and can include a high-side transistor and a low-side transistor for each of the respective phases of the spindle motor 12. The high-side and low-side switching signals of the plurality of switching signals SW can each include one or more digital and/or analog signals corresponding to activation and/or status of the power transistors 18. Therefore, in the example of FIG. 1, a portion of the switching signals SW can be pulse-width modulated (PWM) digital signals that can each be separately asserted and de-asserted by the switching controller 14 in a given commutation cycle. For example, two of the sets of the switching signals SW can have a defined duty-cycle corresponding to control of a CAP phase and a SLOPE phase, respectively, of the spindle motor 12 and a third set of the switching signals can have no PWM duty-cycle, thus controlling a GROUND phase of the spindle motor 12. Accordingly, the power transistors 18 of the switching system 16 are activated and deactivated based on a predetermined PWM scheme to rotate the spindle motor 12 based on commutation in response to the magnetic field energy generated by the inductive load of the phases.

The spindle motor power regulator system 10 also includes a current monitor 20 that is configured to measure the magnitude of at least one of the individual phase currents I_PH that flow through the spindle motor 12 during each PWM cycle. As an example, the current monitor 20 can be configured to measure a magnitude of the CAP phase current and the GROUND phase current. Specifically, the current monitor 20 can be configured to measure a magnitude of the phase current that results from a PWM duty-cycle and is substantially constantly sourced to the respective one of the phases of the spindle motor 12 during the commutation cycle. The current monitor 20 can also be configured to measure a magnitude of the phase current that results from no PWM duty-cycle and thus has a substantially constant flow through the respective one of the phases to a low-voltage power rail (e.g., ground).

In the example of FIG. 1, the switching controller 14 is configured to generate phase control signals PH that are indicative of which of the phase currents flowing through the spindle motor 12 are to be measured. As an example, in a commutation cycle, the switching controller 14 generates two sets of the switching signals SW as having a PWM duty-cycle for controlling the CAP phase current and the SLOPE phase current via the switching system 16. The set of the switching signals SW controlling the CAP phase can have a significantly greater PWM duty-cycle in each PWM period of the commutation cycle than the switching signals controlling the SLOPE phase. The switching controller 14 also generates a set of the switching signals SW that is a non-PWM signal for controlling the GROUND phase current via the switching system 16. Therefore, phase control signals PH are provided to the current monitor 20 to identify which of the sets of phase currents I_PH corresponds to the CAP phase current and which of the sets of phase currents I_PH corresponds to the GROUND phase current based on the manner in which the switching signals SW are provided to the switching system 16.

The current monitor 20 includes one or more current sense systems 22 that are configured to measure the respective phase currents. As an example, the current sense system(s) 22 can switch reference currents corresponding to the CAP and GROUND phases, as identified by the phase control signals PH, to an OP-AMP for measurement of the magnitude of the respective phase currents. In addition, the current monitor 20 can calculate the magnitude of the remaining phase current (i.e., the SLOPE phase current) of the spindle motor 12 to ascertain commutation speed and torque information associated with the spindle motor 12. The current monitor 20 can thus generate a feedback control signal FDBK that corresponds to commutation speed control of the spindle motor 12. In the example of FIG. 1, the feedback control signal FDBK is thus provided to the switching controller 14, such that the pulse-width modulation of the switching signals SW can be adjusted to appropriately control the commutation speed and torque of the spindle motor 12, such that the spindle motor can spin silently at a substantially constant speed.

FIG. 2 illustrates another example of a spindle motor power regulator system 50 in accordance with an aspect of the invention. The spindle motor power regulator system 50 can be implemented to control the rotational motion of a three-phase synchronous DC spindle motor (not shown). In the description herein, the three phases of the spindle motor are described as “A”, “B”, and “C”. In addition, as described herein, “X” corresponds to a respective one of the phases A, B, or C of the spindle motor, such as can be applicable to any one or a respective one of the phases A, B, or C. Similar to as described above in the example of FIG. 1, the spindle motor can be implemented in an HDD or a peripheral disk-drive. The spindle motor power regulator system 50 can be implemented on or as a portion of an IC.

The spindle motor power regulator system 50 includes a switching controller 52 that is configured to generate a set of switching signals for each of the three-phases of the spindle motor. In the example of FIG. 2, the switching signals are demonstrated as SW_A corresponding to control of the first phase of the spindle motor, SW_B corresponding to control of the second phase of the spindle motor, and SW_C corresponding to control of the third phase of the spindle motor. The switching signals SW_A, SW_B, and SW_C are provided to a switching system 54. In the example of FIG. 2, the switching system 54 includes first phase (i.e., “PHASE A”) power transistors 56, second phase (i.e., “PHASE B”) power transistors 58, and third phase power transistors 60 (i.e., “PHASE C”). The first, second, and third phase power transistors 56, 58, and 60 are configured to control the flow of a phase current I_PH—A, a phase current I_PH—B, and a phase current I_PH—C through the respective phases of the spindle motor.

As an example, each set of the switching signals SW_A, SW_B, and SW_C can include a high-side switching signal that controls a high-side transistor and a low-side switching signal that controls a low-side transistor of the respective first, second, and third phase power transistors 56, 58, and 60. The high-side and low-side switching signal of each set of the switching signals SW_A, SW_B, and SW_C can include one or more digital and/or analog signals corresponding to activation and/or status of the power transistors 56, 58, and 60. As another example, the switching signals SW_A, SW_B, and SW_C can each include signals that mutually exclusively activate/deactivate the high-side and low-side transistors of each of the respective first, second, and third phase power transistors 56, 58, and 60, such as to substantially mitigate a shoot-through current through the respective high-side and low-side transistors of each phase of the spindle motor. As an example, the first, second, and third phase power transistors 56, 58, and 60 can be configured as FETs. The respective high-side and low-side transistors can thus couple the respective phases of the spindle motor to one of a high-voltage power rail 62, demonstrated as having a voltage V_EXT that can be a power voltage provided to the IC that houses the spindle motor power regulator system 50, and a low-voltage power 64, demonstrated as ground. Therefore, in the example of FIG. 2, the sets of switching signals SW_A, SW_B, and SW_C can be PWM digital signals that can each be separately asserted and de-asserted by the switching controller 52 in a commutation cycle. Accordingly, the first, second, and third phase power transistors 56, 58, and 60 of the switching system 54 are activated and deactivated based on a predetermined PWM scheme to rotate the spindle motor.

As an example, the switching controller can switch between commutation cycles, such as based on a desired rotation speed of the spindle motor. Each of the commutation cycles can be defined as two of the sets of the switching signals SW_A, SW_B, and SW_C having the same PWM frequency, with one of the two sets having a higher duty-cycle in each PWM period of the commutation cycle and the other of the two sets having a significantly lower duty-cycle in each PWM period of the commutation cycle. The remaining one of the sets of the switching signals SW_A, SW_B, and SW_C can have no PWM duty-cycle. As described herein, having no PWM duty-cycle is defined as a low-side transistor of the respective one of the first, second, and third phase power transistors 56, 58, and 60 being activated throughout the entirety of the commutation cycle, such that the respective phase is grounded throughout the entirety of the commutation cycle.

The spindle motor power regulator system 50 includes a current monitor 66 that is configured to determine the magnitudes of the phase currents I_{PH—A, IPH—B, and IPH—C} that flow through the spindle motor for each PWM cycle. The current monitor 66 includes a high-side current-sense system 68 and a low-side current-sense system 70. The high-side current sense system 68 is configured to measure a magnitude of a phase current (i.e., the CAP phase current) that is substantially constantly sourced to the respective phase of the spindle motor in a commutation cycle. As an example, the CAP phase current can identified as being the one of the phase-currents I_{PH—A, IPH—B}, and I_PH—C resulting from the corresponding one of the sets of the switching signals SW_A, SW_B, and SW_C having the highest PWM duty-cycle in each PWM period of the commutation cycle. The low-side current sense system 70 is configured to measure a magnitude of a phase current (i.e., the GROUND phase current) that is substantially constantly sunk from the respective one of the phases to the low-voltage power rail 64 in the commutation cycle. As an example, the low-side sinking phase current can be the one of the phase-currents I_PH—A, I_PH—B, and I_PH—C resulting from the corresponding one of the sets of the switching signals SW_A, SW_B, and SW_C having no PWM duty-cycle.

Each of the high-side and low-side current sense systems 68 and 70 include a set of sense FETs 72, a set of phase switches 74, and an operational amplifier (OP-AMP) 76. As an example, for each of the high-side and low-side current sense systems 68 and 70, the set of sense FETs 72 can include a pair of matched FETs for each high-side and low-side transistor of the first, second, and third phase power transistors 56, 58, and 60, respectively. The pairs of matched FETs can be configured, respectively, as LDMOSFETs that conduct a first reference current from a phase node associated with the respective power transistors 56, 58, and 60 and a second reference current from the respective one of the power rails 62 and 64 in response to the respective switching signals SW_X. As an example, each of the FETs in the sense FETs 72 can have a gate area that is smaller than the respective power transistors in the first, second, and third phase power transistors 56, 58, and 60.

The phase switches 74 can be configured to switch the reference currents of the corresponding set of the sense FETs 72 to the OP-AMP 76 for measurement. Specifically, as described above, the high-side current sense system 68 is configured to measure the magnitude of the high-side sourcing phase current, and the low-side current sense system 70 is configured to measure the magnitude of the low-side sinking phase current. The switching controller 52 identifies which of the phase currents I_PH—A, I_PH—B, and I_PH—C is the high-side sourcing phase current that is to be measured and which of the phase currents I_PH—A, I_PH—B, and I_PH—C is the low-side sinking phase current that is to be measured. Specifically, the switching controller 52 generates phase control signals HS_PH and LS_PH that are provided to the phase switches 74 of the high-side and low-side current sense systems 68 and 70, respectively. The phase control signals HS_PH thus identifies which of the phase currents I_PH—A, I_PH—B, and I_PH—C is the high-side sourcing phase current that controls the CAP phase current and the phase control signals LS_PH thus identifies which of the phase currents I_PH—A, I_PH—B, and I_PH—C is the low-side sinking phase current that controls the GROUND phase. Therefore, the phase switches 74 can switch the corresponding reference currents provided from the sense FETs 72 corresponding to the high-side sourcing phase current and the low-side sinking phase current to the respective OP-AMPs 76 in response to the phase control signals HS_PH and LS_PH.

The OP-AMPs 76 are configured to measure the magnitudes of the high-side sourcing phase current and the low-side sinking phase current, respectively. Specifically, the OP-AMPs 76 can generate respective sense voltages V_SNS—HS and V_SNS—LS that have magnitudes that are proportional to (i.e., highly linear with respect to) the high-side sourcing phase current and the low-side sinking phase current, respectively, in response to the reference currents that are provided from the sense FETs 72 via the phase switches 74. The sense voltages V_SNS—HS and V_SNS—LS are each provided to an analog-to-digital converter (ADC) 78 that is configured to sample and convert the sense voltages V_SNS—HS and V_SNS—LS to respective digital values. As an example, the ADC 78 can sample one or more times during each PWM cycle depending on speed and torque control requirements for the spindle motor. The ADC 78 thus generates a digital signal DIG_CURR that is indicative of the magnitudes of the sense voltages V_SNS—HS and V_SNS—LS.

The digital signal DIG_CURR is provided to a processor 80 that can be configured to calculate magnitudes of each of the first, second, and third phase currents I_PH—A, I_PH—B, and I_PH—C. As an example, the processor 80 can be configured to calculate the measured magnitudes of the CAP phase current and the GROUND phase current by implementing previous calibrated gains and offsets stored in the processor 80 and assuming a linear relationship from an ADC output value to a measured phase current. In addition, the processor 80 can be configured to calculate the magnitude of the remaining one of the first, second, and third phase currents I_PH—A, I_PH—B, and I_PH—C (i.e., the SLOPE phase current) in response to the calculated magnitudes of the high-side sourcing phase current and the low-side sinking phase currents.

As a result, because the magnitudes of the phase currents I_PH—A, I_PH—B, and I_PH—C are directly related to the commutation speed and torque of the spindle motor, the processor 80 can be configured to modify/control the commutation speed and torque of the spindle motor. In the example of FIG. 2, the processor 80 is demonstrated as generating a feedback control signal FDBK that is provided to the switching controller 52. Therefore, the switching controller 52 can adjust the pulse-width modulation scheme of the switching signals SW_A, SW_B, and SW_C in response to the feedback control signal FDBK. As an example, the feedback control signal FDBK can provide information as to how the pulse-width modulation of the switching signals SW_A, SW_B, and SW_C should be adjusted, or can provide information as to what the pulse-width modulation of the switching signals SW_A, SW_B, and SW_C should be to compensate for error in the commutation speed and torque of the spindle motor, such that the spindle motor can spin silently at a substantially constant speed.

It is to be understood that the spindle motor power regulator system 50 is not limited to the example of FIG. 2. As an example, one or more of the system components demonstrated in the example of FIG. 2 can be configured as part of or separately from other demonstrated system components. For example, the processor 80 can be incorporated into the switching controller 52, such that the ADC 78 provides the signal DIG_CURR directly to the switching controller 52. In addition, as demonstrated in greater detail below, additional signal interaction between the system components may be omitted from the example of FIG. 2. Thus, the spindle motor power regulator system 50 can be configured in any of a variety of ways.

FIG. 3 illustrates an example of a current-sense system 100 in accordance with an aspect of the invention. The example of FIG. 3 also demonstrates the switching system 54, including the first, second, and third phase power transistors 56, 58, and 60. The current sense system 100 can thus correspond to one of the high-side current sense system 68 or the low-side current sense system 70 in the example of FIG. 2. Specifically, the current sense system 100 demonstrated in the example of FIG. 3 can be one of the high-side current sense system 68 and the low-side current sense system 70, such that another current sense system that is configured similar to the current sense system 100 can likewise be coupled with the switching system 54. Therefore, reference is to be made to the example of FIG. 2 in the following description of the example of FIG. 3.

In the example of FIG. 3, the first, second, and third phase power transistors 56, 58, and 60 are demonstrated as FETs. Specifically, the first phase power transistors 56 include a high-side power FET HS_A and a low-side power FET LS_A, the second phase power transistors 58 include a high-side power FET HS_B and a low-side power FET LS_B, and the third phase power transistors 60 include a high-side power FET HS_C and a low-side power FET LS_C. Therefore, the first, second, and third phase power transistors 56, 58, and 60 are responsive to the switching signals SW_A, SW_B, and SW_C, respectively (not shown in the example of FIG. 3), to generate the respective phase currents I_PH—A, I_PH—B, and I_PH—C by coupling the respective the phases of the spindle motor to either the high-voltage rail 62 (i.e., the voltage V_EXT) or the low-voltage rail 64 (i.e., ground).

The current sense system 100 includes a first set of sense FETs 102, a second set of sense FETs 104, and a third set of sense FETs 106 corresponding, respectively, to each of the phases of the spindle motor. In the example of FIG. 3, the phase current I_PH—A is demonstrated as being provided to the first set of sense FETs 102, the phase current I_PH—B is demonstrated as being provided to the second set of sense FETs 104, and the phase current I_PH—C is demonstrated as being provided to the third set of sense FETs 106. It is to be understood that only a portion of each of the phase currents I_PH—A, I_PH—B, and I_PH—C may be provided to each of the respective sets of sense FETs 102, 104, and 106, as opposed to the entirety of the phase currents I_PH—A, I_PH—B, and I_PH—C.

Each of the sets of sense FETs 102, 104, and 106 can include a pair of matched FETs for each of the high-side power FETs HS_A, HS_B, and HS_C, respectively, for the current sense system 100 being configured as the high-side current sense system 54. Alternatively, each of the sets of sense FETs 102, 104, and 106 can include a pair of matched FETs for each of the low-side power FETs LS_A, LS_B, and LS_C, respectively, for the current sense system 100 being configured as the low-side current sense system 70. The pairs of matched FETs can be configured, respectively, to conduct a first reference current from a phase node associated with the respective power FETs 56, 58, and 60 and a second reference current from the respective one of the power rails 62 and 64 in response to the respective switching signals SW_X. As an example, each of the FETs in the respective sets of sense FETs 102, 104, and 106 can have a gate area that is smaller than the respective high-side or low-side power FETs in the first, second, and third phase power FETs 56, 58, and 60.

Coupled to the sets of sense FETs 102, 104, and 106 are respective sets of phase switches 108, 110, and 112. The sets of phase switches 108, 110, and 112 are configured to switch the first and second reference currents from one of the sets of sense FETs 102, 104, and 106, as well as one or more additional reference currents, such as a third reference current that is also conducted from the respective phase node associated with one of the sets of sense FETs 102, 104, and 106 to the OP-AMP 76. In the example of FIG. 3, the reference currents that are provided to the OP-AMP 76 are demonstrated as currents I_REF. The switching of the currents I_REF to the OP-AMP 76 can be in response to the phase control signals HS_PH for the current sense system 100 being configured as the high-side current sense system 68 or in response to the signals LS_PH for the current sense system 100 being configured as the low-side current sense system 70.

The OP-AMP 76 is thus configured to measure the magnitude of the respective one of the phase currents I_PH—A, I_PH—B, or I_PH—C based on the currents I_REF. For example, for the current sense system 100 being configured as the high-side current sense system 68, the switching controller 52 identifies which of the phase currents I_PH—A, I_PH—B, or I_PH—C is the high-side sourcing phase current (i.e., the CAP phase current) that is to be measured. The switching controller 52 thus provides the phase control signals HS_PH to the sets of phase switches 108, 110, and 112 to switch the currents I_REF from the respective one of the sets of sense FETs 102, 104, and 106 corresponding to the high-side sourcing phase current to the OP-AMP 76 for the OP-AMP 76 to measure the magnitude of the high-side sourcing phase current. Similarly, for the current sense system 100 being configured as the low-side current sense system 56, the switching controller 52 identifies which of the phase currents I_PH—A, I_PH—B, or I_PH—C is the low-side sinking phase current (i.e., the GROUND phase current) that is to be measured. The switching controller 52 thus provides the signals LS_PH to the sets of phase switches 108, 110, and 112 to switch the currents I_REF from the respective one of the sets of sense FETs 102, 104, and 106 corresponding to the low-side sinking phase current to the OP-AMP 76 for the OP-AMP 76 to measure the magnitude of the low-side sourcing phase current.

The OP-AMP 76 thus generates a sense voltage V_SNS in response to the currents I_REF. The voltage V_SNS can have a magnitude that is proportional to the magnitude of the measured one of the phase currents I_PH—A, I_PH—B, and I_PH—C. As an example, the OP-AMP 76 can be configured to conduct approximately equal bias currents through respective current paths of the OP-AMP 76, such that the bias currents set a magnitude of the sense voltage V_SNS to be proportional to the respective one of the phase currents I_PH—A, I_PH—B, and I_PH—C. For example, the OP-AMP 76 can include a cascode amplifier that is controlled by one or both of the conducted bias currents. Accordingly, because the sense voltage V_SNS generated by the OP-AMP 76 has a magnitude proportional to the magnitude of the high-side sourcing phase current or the low-side sinking phase current, the OP-AMP 76 is thus configured to measure the magnitude of the high-side sourcing phase current or the low-side sinking phase current.

It is to be understood that the current sense system 100 in the example of FIG. 3, as well as the switching system 54, are demonstrated simplistically. As such, the signal interaction and interconnection between the current sense system 100 and the switching system 54 are likewise demonstrated simplistically, such that a number of signals have been omitted and/or simplified in the example of FIG. 3. Furthermore, it is also to be understood that the current sense system 100 is not limited to implementing the sets of sense FETs 102, 104, and 106, the sets of phase switches 108, 110, and 112, and/or the OP-AMP 76 to measure the respective one or more of the phase currents I_PH—A, I_PH—B, and I_PH—C. Accordingly, the current sense system 100 can be configured in any of a variety of ways.

FIG. 4 illustrates an example of a high-side current-sense system 150 in accordance with an aspect of the invention. As an example, the high-side current-sense system 150 in the example of FIG. 4 can correspond to the high-side current-sense system 68 in the example of FIG. 2. As such, like reference numbers are used and reference is to be made to the example of FIGS. 2 in the following description of the example of FIG. 4.

Similar to as described above in the example of FIG. 2, the high-side current-sense system 150 is configured to monitor a magnitude of one of the phase currents I_PH—A, I_PH—B, or I_PH—C that flows through a respective one of the high-side power FETs, demonstrated in the example of FIG. 4 as high-side power FETs HS_A, HS_B, HS_C. The high-side current-sense system 150 includes respective sets of sense FETs 152, 154, and 156. In the example of FIG. 4, the sense FETs 152 are demonstrated as a first N-FET N1 and a second N-FET N2, the sense FETs 154 are demonstrated as a third N-FET N3 and a fourth N-FET N4, and the sense FETs 156 are demonstrated as a fifth N-FET N5 and a sixth N-FET N6. As an example, each of the N-FETs N1 through N6 can have a gate area that is less than the gate area of the high-side power FETs HS_A, HS_B, and HS_C.

Each of the first and second N-FETs N1 and N2 are controlled at a gate by the high-side switching signal SW_HS_A that likewise controls the high-side power FET HS_A. Similarly, each of the third and fourth N-FETs N3 and N4 are controlled at a gate by the high-side switching signal SW_HS_B that likewise controls the high-side power FET HS_B, and each of the fifth and sixth N-FETs N5 and N6 are controlled at a gate by the high-side switching signal SW_HS_C that likewise controls the high-side power FET HS_C. The first N-FET N1 is coupled at a drain to a phase node 158 and is configured to conduct a first reference current I_1—A that is a first portion of the phase current I_PH—A in response to the high-side control signal SW_HS_A. The second N-FET N2 is coupled at a drain to the high-voltage power rail 62 and is configured to conduct a second reference current I_2—A from the high-voltage power rail 62 in response to the high-side control signal SW_HS_A. Similarly, the third N-FET N3 is coupled at a drain to a phase node 160 and is configured to conduct a first reference current I_1—B that is a first portion of the phase current I_PH—B in response to the high-side control signal SW_HS_B. The fourth N-FET N4 is coupled at a drain to the high-voltage power rail 62 and is configured to conduct a second reference current I_2—B from the high-voltage power rail 62 in response to the high-side control signal SW_HS_B. The fifth N-FET N5 is coupled at a drain to a phase node 162 and is configured to conduct a first reference current I_1—C that is a first portion of the phase current I_PH—C in response to the high-side control signal SW_HS_C. The sixth N-FET N6 is coupled at a drain to the high-voltage power rail 62 and is configured to conduct a second reference current I_2—C from the high-voltage power rail 62 in response to the high-side control signal SW_HS_C. The high-side control signals SW_HS_A, SW_HS_B, and SW_HS_C can be analog activation signals that are generated from the respective high-side drivers in the switching control circuit 52 as demonstrated in the example of FIG. 2, and can thus constitute one of the switching signals SW_A, SW_B, and SW_C.

The first and second reference currents I_1—A and I_2—A, as well as a third reference current I_3—A that is conducted from the phase node 158, are provided to a set of phase switches 164. The phase switches 164 are controlled by a set of phase control signals HS_PH_A. Similarly, the first and second reference currents I_1—B and I_2—B, as well as a third reference current I_3—B that is conducted from the phase node 160, are provided to a set of phase switches 166 controlled by a set of phase control signals HS_PH_B. Furthermore, the first and second reference currents I_1—C and I_2—C, as well as a third reference current I_3—C that is conducted from the phase node 162, are provided to a set of phase switches 168 controlled by a set of phase control signals HS_PH_C. The phase control signals HS_PH_A, HS_PH_B, and HD₁₃ PH_C can collectively correspond to the phase control signals HS_PH generated by the switching controller 52 in the example of FIG. 2.

It is to be understood that, based on the flow of the first and third reference currents I_1—A and 13 A from the phase node 158, the magnitude of the current flow through the high-side power FET HS_A can be greater than the magnitude of the output current I_PH—A flowing from the phase node 158 to the load (not shown). However, the magnitude of the first and third reference currents I_1—A and I_3—A can be significantly less than the magnitude of the output current I_PH—A, such that the difference in magnitudes between the current flow through the high-side power FET HS_A and the output current I_PH—A can be substantially negligible. It is also to be understood that the difference in magnitudes between the current flow through the high-side power FET HS_B and the output current I_PH—B, as well as the current flow through the high-side power FET HS_C and the output current I_PH—C, can likewise be substantially negligible.

The phase control signals HS_PH_A, HS_PH_B, and HS_PH_C are thus provided by the switching controller 52 to couple a respective one of the sets of reference currents I_1—A, I_2—A, and I_3—A; I_1—B, I_2—B, and I_{3 B}; and I_1—C, I_2—C, and I_3—C to an OP-AMP 170. Therefore, the phase control signal HS_PH_A couples the reference currents I_1—A, I_2—A, and I_3—A to the OP-AMP 170 as the currents I_REF via the first set of phase switches 164. The phase control signals HS_PH_B and HS_PH_C thus disable the second and third sets of phase switches 166 and 168, respectively. Accordingly, the OP-AMP 170 can generate a high-side sense voltage V_SNS—HS that has a magnitude that is proportional to the magnitude of the phase current I_PH—A. Similarly, the reference currents I_1—B, I_2—B, and I_3—B or the reference currents I_1—C, I_2—C, and I_3—C could instead be coupled to the OP-AMP 170 upon the switching controller 52 identifying that the phase current I_PH—B or I_PH—C, respectively, is the CAP phase current, thus disabling the other two sets of the phase switches 164, 166, and 168.

In addition to the coupling of the respective reference currents I_REF to the OP-AMP 170, the sets of phase switches 164, 166, and 168 can also be configured to split the respective sets of reference currents I_1—A, I_2—A, and I_3—A; I_1—B, I_2—B, and I_3—B; and I_1—C, I_2—C, and I_{3 —C} into a sense current, a sense offset current, and a pair of bias currents that collectively form the currents I_REF. As an example, the pair of bias currents can be approximately equal bias currents that flow through respective current paths of the respective one of the sets of phase switches 164, 166, and 168 and the OP-AMP 170, such that the bias currents set a magnitude of the sense current from which the high-side sense voltage V_SNS—HS is generated. Furthermore, the respective one of the sets of phase switches 164, 166, and 168 can be configured to pre-bias the electronic components of the OP-AMP 170 prior to the full activation of the respective one of the high-side power FETs HS_A, HS_B, and HS_C. Accordingly, transient effects that can affect the magnitude of the high-side sense voltage V_SNS—HS can be substantially mitigated.

FIG. 5 illustrates an example of a phase switch and OP-AMP arrangement 200 in accordance with an aspect of the invention. The phase switch and OP-AMP arrangement 200 includes an OP-AMP 201 that can correspond to the OP-AMP 170 in the examples of FIG. 4. The example of FIG. 5 also demonstrates the sets of phase switches 164, 166, and 168. The first set of phase switches 164 is demonstrated as expanded, demonstrating the signals that are input to it. It is to be understood that the second and third sets of phase switches 166 and 168 receive a substantially similar set of input signals, with the respective “B” and “C” phase designations instead of “A”. Therefore, reference is to be made to the examples of FIG. 4 in the following description of the example of FIG. 5.

In the example of FIG. 5, upon being provided to the first set of phase switches 164, the first reference current I_1—A is split into a first bias current I_B1 and a sense offset current I_SE and the second reference current I_2—A is split into a second bias current I_B2 and a sense current I_SNS. As described in greater detail below, the sense offset current I_SE can be generated from an exact current source, such that the sense offset current I_SE can have a substantially constant magnitude. In addition, the phase control signal HS_PH_A and an activation signal HS_ON_A are also provided to the first set of phase switches 164. As an example, the phase control signal HS_PH_A and an activation signal HS_ON_A can each be a digital signal that controls an activation state of a plurality of switches in the first set of phase switches 164, as described in greater detail below. As demonstrated in the example of FIG. 5, an OP-AMP input-referred offset voltage V_OS having a minimal magnitude can exist between the inputs of the first set of phase switches 164 that receive the first and second bias currents I_B1 and I_B2. For example, the magnitude of the offset voltage V_OS can be based on process and temperature variations of the electronic components of the OP-AMP 201.

The OP-AMP 201 includes a current control circuit 202. The current control circuit 202 includes a first current path 204 that conducts the first bias current I_B1, a second current path 206 that conducts the second bias current I_B2, a third current path 208 that conducts the reference current I_3—A, and a fourth current path 210 that conducts the sense current I_SNS. As an example, the first and second current paths 204 and 206 can be configured substantially the same, such that the first and second bias currents I_B1 and I_B2 have approximately equal magnitudes. Specifically, the first and second current paths 204 and 206 can be configured as cascode current mirrors or a cascode amplifier to maintain high sensing linearity over a broad range of magnitudes of the respective phase current I_PH—X. As another example, to increase the dynamic range of the sense current I_SNS and reduce a systematic offset of the sense current I_SNS, the third current path 208 can be configured as a level-shifter that is controlled by at least one of the first and second current paths 204 and 206. Accordingly, the magnitude of the reference current I_3—A can be controlled by the first and/or second bias current I_B1 and/or I_B2. The output of the level-shifter in the third current path 208 can thus control a gate of a pass-MOSFET in the fourth current path 210 to generate the magnitude of the sense current I_SNS in the fourth current path 210. The high-side sense voltage V_SNS—HS, which is output from the current control circuit 202, can be generated from the sense current I_SNS.

The OP-AMP 201 further includes bias current sources 212. The bias current sources 212 include a first bias current source 214 that conducts the first bias current I_B1, a second bias current source 216 that conducts the second bias current I_B2, and an input bias current source 218 that conducts the sense offset current I_SE. As an example, the first and second bias current sources 214 and 216 can be mirrored from a common current source, and the input bias current source 218 can be an exact current source, such that the sense offset current I_SE has a substantially constant magnitude. For example, the sense offset current I_SE can have a magnitude that is selected such that, upon the magnitude of the respective one of the phase currents I_PH—A, I_PH—B, and I_PH—C being approximately zero, the OP-AMP 201 can be properly biased to maintain sufficient loop gain and speed under all variations of the offset voltage V_OS.

As described above in the example of FIG. 4, the sets of phase switches 164, 166, and 168 can direct the respective first, second, and third reference currents I_1—X, I_2—X, and I_3—X to the OP-AMP 201 in response to the respective phase control signals HS_PH_A, HS_PH_B, and HS_PH_C. Specifically, upon determining which of the phase currents I_PH—A, I_PH—B, and I_PH—C is the CAP phase current, the phase control signals HS_PH_A, HS_PH_B, and HS_PH_C corresponding to the other two of the phase currents I_PH—A, I_PH—B, and I_PH—C can be implemented in a commutation cycle to de-couple the current control circuit 202 and/or the bias current sources 212 from the corresponding sets of sense FETs 152, 154, and 156 and the corresponding phase nodes 158, 160, and 162 from the OP-AMP 201. In addition, the activation signal HS_ON_X corresponding to the CAP phase of the spindle motor phase through which high-side sourcing current flows can be implemented (e.g., de-asserted) prior to full activation of the respective one of the high-side power FETs HS_X via the high-side switching signal SW_HS_X to couple the current control circuit 202 to the voltage V_EXT.

As an example, in a PWM cycle of the CAP phase, the activation signal HS_ON_X can be asserted to indicate that the respective one of the high-side power FETs HS_X is nearly settled or fully activated in a first state, thus indicating that the CAP phase current is ready to be measured. For example, the activation signal HS_ON_X can be a substantially delayed version of the respective switching signal SW_HS_X based on an amount of time that it takes to activate the respective one of the high-side power FETs HS_X due to the large gate area of the respective one of the high-side power FETs HS_X. Similarly, the activation signal HS_ON_X can be de-asserted to indicate that the respective one of the high-side power FETs HS_X will be imminently deactivated or fully deactivated in a second state, thus indicating that the CAP phase current is not to be measured. Therefore, the electronic components in the current paths 204, 206, 208, and 210, as well as the bias current source 212, can be pre-biased at a substantially settled state. The pre-biasing of the electronic components in the current paths 204, 206, 208, and 210, as well as the bias current source 212 can thus substantially mitigate transient effects on the sense current I_SNS, such as in response to switching the high and low-side power FETs HS_X and LS_X of the CAP phase and can greatly improve sensing speed and accuracy.

FIG. 6 illustrates an example of a phase switch and OP-AMP circuit 250 in accordance with an aspect of the invention. The phase switch and OP-AMP circuit 250 includes an OP-AMP 251 that can correspond to the OP-AMP 201 in the example of FIG. 5, and a set of phase switches 252 that can correspond to one of the sets of phase switches 164, 166, or 168 in the examples of FIGS. 4 and 5. Therefore, reference is to be made to the examples of FIGS. 4 and 5 in the following description of the example of FIG. 6.

The OP-AMP 251 includes the current control circuit 202 and the bias current sources 212. The current control circuit 202 includes the first current path 204 that conducts the first bias current I_B1 and the second current path 206 that conducts the second bias current I_B2. Each of the first and current paths 204 and 206 include respective PNP bipolar junction transistors (BJTs) Q1 and Q2 in series with respective P-MOSFETs P1 and P2. The BJTs Q1 and Q2 are arranged in a cascoded current-mirror configuration via an interposing P-MOSFET P3 having a source that is coupled to the bases of the BJTs Q1 and Q2, a gate that is coupled to the collector of the BJT Q2, and a drain that is coupled to ground. Similarly, the P-MOSFETs P1 and P2 are arranged in a current-mirror configuration based on the coupling of the respective gates of the P-MOSFETs P1 and P2 and the drain of the P-MOSFET P2 at a node 254. The cascoded current-mirror configuration of the BJTs Q1 and Q2 and P-MOSFETs P1 and P2 is configured to substantially increase the open-loop gain of the OP-AMP 251, to reduce a current mismatch between the first and second current paths 204 and 206 due to a limited output impedance of the BJTs Q1 and Q2, and to maintain substantially high-sensing linearity over a broad range of magnitudes of the respective phase current I_PH—X.

In addition, the current control circuit 202 includes the third current path 208 that includes a PNP BJT Q3, a diode-configured PNP BJT Q4, and a P-MOSFET P4. The base of the BJT Q3 is coupled to the bases of the BJTs Q1 and Q2, and the gate of the P-MOSFET P4 is coupled to a node 256 that is coupled to the drain of the P-MOSFET P1. Therefore, the third current path 208 is configured as a level-shifter having a current magnitude that is controlled by the first and second current paths 204 and 206. The output of the level-shifter of the third current path 208 is demonstrated in the example of FIG. 6 as a node 258 that controls a gate of a P-MOSFET P5 through which the sense current I_SNS flows in the fourth current path 210. The level-shifter can substantially increase the dynamic range of the sense current I_SNS and substantially reduce the systematic offset of the sense current I_SNS. In addition, in the example of FIG. 6, the nodes 254 and 256 are separated by a series connection of a resistor R_C1, a capacitor C₁, and a resistor R_C2, with the resistors R_C1 and R_C2 having approximately the same resistance magnitude, that are configured to substantially increase a sensing speed in response to transients and to stabilize a frequency response associated with the OP-AMP 251.

Additionally, the bias current sources 212 includes a current-mirror network 260 that is configured to generate the first bias current I₁ and the second bias current I₂. Specifically, the current-mirror network 260 includes a current source 262 configured to generate a current I_SI that flows through N-MOSFETs N7 and N8 and through a resistor R₂. As an example, the current source 262 can be generated from an internal voltage supply. The current-mirror network 260 also includes N-MOSFETs N9 and N10 that are arranged in a current-mirror configuration with the N-MOSFETs N7 and N8, respectively, and a resistor R₃ that is configured in series with the N-MOSFETs N9 and N10. The N-MOSFETs N9 and N10 and the resistor R₃ thus constitutes the first bias current source 214 that conducts the first bias current I_B1. Similarly, the current-mirror network 260 also includes N-MOSFETs N11 and N12 that are arranged in a current-mirror configuration with the N-MOSFETs N7 and N8, respectively, and a resistor R₄ that is configured in series with the N-MOSFETs N11 and N12. The N-MOSFETs N11 and N12 and the resistor R₄ thus constitutes the second bias current source 216 that conducts the second bias current I_B2.

The set of phase switches 252 includes a plurality of resistors through which the first, second, and third reference currents I_1—X, I_2—X, and I_3—X flow depending on the state of a plurality of switches in response to the activation signal HS_ON_X (not shown). Specifically, the set of phase switches 252 includes a first set of switches S_N—OP and a second set of switches S_N—PB that are mutually exclusively controlled by the activation signal HS_ON_X, where N is an integer from 1 to 5 as demonstrated in the example of FIG. 6. All of the resistors R_N—PB and R_N—OP, as well as the resistors R₂, R₃ and R₄, can be substantially the same type of the resistors.

Each of the switches S_2—PB, S_3—PB, and S_4—PB interconnects the high power voltage rail 62 with respective resistors R_2—PB, R_3—PB, and R_4—PB. The switch S_1—PB and respective resistor R_1—PB interconnect the current source 218 and the first current path 204 at the emitter of the BJT Q1, and the switch S_5—PB and respective resistor R_5—PB interconnect the source of the P-MOSFET P5 and the second current path 206 at the emitter of the BJT Q2. Thus, the switches S_X—PB are activated by de-asserting the activation signal HS_ON_X for pre-biasing the current control circuit 202, as described in greater detail below. Alternatively, the activation signal HS_ON_X is asserted to activate the switches S_N—OP to couple the first, second, and third reference currents I_1—X, I_2—X, and I_3—X to the current control circuit 202 via the respective resistors R_N—OP (demonstrated by the state of the switches S_N—OP in the example of FIG. 6). Furthermore, it is to be understood that, upon the first, second, and third reference currents I_1—X, I_2—X, and I_3—X being determined not to be associated with the high-side sourcing phase current, the corresponding phase control signal HS_PH_X can open all of the switches S_N—OP and S_N—PB to decouple the first, second, and third reference currents I_1—X, I_2—X, and I_3—X from the OP-AMP 251.

In the example of FIG. 6, the resistors R_2—OP and R_3—OP and their respective switches S_2—OP and S_3—OP, the resistors R_2—PB and R_3—PB and their respective switches S_2—PB and S_3—PB, the resistors R_1—PB and R_5—PB and their respective switches S_1—PB and S_5—PB, the BJTs Q1 and Q2, the P-MOSFETs P1 and P2, the N-MOSFETs N9 and N11 , the N-MOSFETs N10 and N12, and the resistors R₃ and R₄ can all be matched components relative to each other, such that the first and second bias currents I_B1 and I_B2 have substantially equal magnitudes. As a result, the sense current I_SNS can have a good power supply rejection ration (PSRR) with respect to the voltage V_EXT. The current source 262 that conducts the current I_SI, along with the first and second bias current sources 214 and 216 that conduct the respective currents I_B1 and I_B2, can be such that a voltage drop across the respective resistors R₂, R₃, and R₄ remains substantially constant under process and temperature variations. Furthermore, the bias current sources 212 include the input bias current source 218 that can be an exact current source that conducts the sense offset current I_SE.

In the example of FIG. 6, just prior to assertion of the activation signal HS_ON_X, the respective high-side power FET HS_X is about to be fully activated, and all of the switches S_N—OP are open and all of the switches S_N—PB are closed. Therefore, the input bias current source 218 conducts the sense offset current I_SE from the voltage V_EXT via the resistors R_1—PB and R_2—PB, and the first and second bias current sources pull the respective first and second bias currents I_B1 and I_B2 from the voltage V_EXT via the respective resistors R_2—PB and R_3—PB and the respective first and second current paths 204 and 206. Likewise, the third reference current I_3—X flows from the voltage V_EXT via the resistor R_4—PB and through the third current path 208. The sense current I_SNS flows from the voltage V_EXT via the resistors R_3—PB and R_5—PB through the P-MOSFET P5 in the fourth current path 210. Thus, the sense current I_SNS can remain at a magnitude that is substantially equal to the magnitude of the sense offset current I_SE. As a result, the current control circuit 202 and the bias current sources 212 are pre-biased at a substantially settled state. Accordingly, prior to the assertion of the activation signal HS_ON_X, the switching of the respective high-side and low-side power FETs HS_X and LS_X of the CAP phase has substantially no transient effect on the magnitude of the sense current I_SNS.

Upon the activation signal HS_ON_X being asserted, all of the switches S_N—OP are closed and all of the switches S_N—PB are opened (i.e., as demonstrated in the example of FIG. 6). Therefore, the sense offset current I_SE and the first bias current I_B1 are conducted from the first reference current I_1—X (i.e., from the first sense FET N1) via the resistors R_{1 OP} and R_{2 OP}, respectively. Similarly, the second bias current I_B2 and the sense current I_SNS are conducted from the second reference current I_2—X (i.e., from the second sense FET N2) via the resistor R_3—OP and the switch S_5—OP, respectively. Likewise, the third reference current I_3—X is conducted from the respective one of the phase nodes 158, 160, and 162 via the resistor R_4—OP, and has a magnitude that is based on the magnitudes of the first and second bias currents I_B1 and I_B2. The magnitude of the sense current I_SNS is controlled by the voltage magnitude at the node 258.

The OP-AMP 251 thus begins to sense the magnitude of the respective phase current I_PH—X. Because the current control circuit 202 and the bias current sources 212 are pre-biased at the substantially settled state and the respective high-side power FET HS_X is substantially fully activated, switching transient effects that could affect the magnitude of the sense current I_SNS are substantially mitigated. As a result, the sense current I_SNS can quickly settle for accurate sensing of the magnitude of the respective phase current I_PH—X. The sensing speed and the sensing accuracy are thus substantially improved, particularly if the PWM frequency becomes too high and the PWM duty-cycle becomes too low for the CAP phase.

The OP-AMP 251 continues to track and sense the respective phase current I_PH—X until the activation signal HS_ON_X is de-asserted. At approximately the time that the activation signal HS_ON_X becomes de-asserted and the respective high-side power FET HS_X is nearly or fully activated, all of the switches in the set of phase switches 252 change state. As a result, the respective high-side power FET HS_N_X and the sense FETs N1 and N2 are all de-coupled from the OP-AMP 251. Therefore, transient effects on the sense current I_SNS, such as in response to deactivation of the respective high power FETs HS_X, are substantially mitigated. While the activation signal HS_ON_X remains de-asserted, the sense current I_SNS is held at approximately the same amplitude as the sense offset current I_SE, assuming no variation between the associated electronic components. As a result, the current control circuit 202 and the bias current sources 212 are pre-biased at a favorable settled state to await the next sense request via the next assertion of the activation signal HS_ON_X.

As described above, the current control circuit 202 includes the fourth current path 210 through which the sense current I_SNS flows. Specifically, the sense current I_SNS flows through the P-MOSFET P5 and a resistor R_LIM to a common voltage V_COM via a parallel connection of a resistor R_F, a capacitor C_F, and a switch S_F. As an example, the common voltage V_COM can be a negative rail voltage having a magnitude that is selected based on an input dynamic range of the ADC 78 in the example of FIG. 2. As another example, the common voltage V_COM can be ground, or can be greater than ground. The switch Scan be controlled by the activation signal HS_ON_X or can be substantially synchronized with the switches S_X—PB. As an example, the switch S_F can be opened during sensing of the respective phase current I_PH—X, such as when the activation signal HS_ON_X is asserted or when the switches S_X—PB are opened. The switch S_F can be closed when the activation signal HS_ON_X is de-asserted or when the switches S_X—PB are closed. As a result, the resistor R_F, the capacitor C_F, and the switch S_F are configured to mitigate switching transients and/or other high-frequency noise associated with the sense current I_SENSE.

The sense current I_SNS generates a sense voltage V_SNS—HS at a sensing node 264. The resistor R_LIM is implemented to limit the magnitude of the sense current I_SNS, and to thus limit the sense voltage V_SNS—HS at the sensing node 264 based on the voltage drop across the resistor R_LIM. In addition, the OP-AMP 251 also includes a voltage clamp 266 that is coupled to the sensing node 264. The voltage clamp 266 is configured to clamp the magnitude of the sense voltage V_SNS—HS, such as by shunting excess current to ground. As such, the magnitude of the sense voltage V_SNS—HS does not exceed the magnitude of a voltage V_DD. As an example, the voltage V_DD can be an internally provided analog voltage supply for the ADC 78 that is generated at a magnitude that is less than the external voltage V_EXT. As a result, the ADC 78 can implement smaller, low-voltage electronic devices to conserve IC layout area.

Based on the above described operation of the OP-AMP 251, the magnitude of the sense current I_SNS during sensing of the respective phase current I_PH—X can be described by the following expression:

$\begin{array}{cc}{I}_{\mathrm{SNS}}=\left(\frac{I_{\mathrm{PH\_X}}}{M_{\mathrm{PH\_X}}}\right)+I_{\mathrm{OS\_X}}+I_{\mathrm{SE}}& \mathrm{Equation}1\end{array}$

Where:M_PH—X is a proportionality constant of the size mirroring ratio of the high-side power FET HS_X relative to the respective sense FETs N1 through N6; and

• • I_OS—X is a sense offset current related to the respective high-side phase.As demonstrated by Equation 1, a linear relationship exists between the magnitude of the sense current I_SNS and the phase current I_PH—X. To achieve the linear relationship, as demonstrated in Equation 1, the high-side power FET HS_X and the respective N-FETs N1 through N6 can be operating well within the triode/linear region. Based on Equation 1, the sense voltage V_SNS—HS can thus be expressed as follows:

$\begin{array}{cc}{V}_{\mathrm{SNS\_HS}}=I_{\mathrm{SNS}}*R_F=\left(\left(\frac{I_{\mathrm{PH\_X}}}{M_{\mathrm{PH\_X}}}\right)+I_{\mathrm{OS\_X}}+I_{\mathrm{SE}}\right)*R_F& \mathrm{Equation}2\end{array}$

As a result, the sense voltage V_SNS—HS has a magnitude that is proportional to the sense current I_SNS, and thus to the respective phase current I_PH—X.

As described above, the first and second bias currents I_B1 and I_B2 have substantially equal magnitudes based on substantially matched electronic components in each of the set of phase switches 252, the current control circuit 202, and the bias current sources 212. Such matching can improve PSRR of the sense current I_SNS with respect to the voltage V_EXT. In addition, the source degeneration structure of each of the bias current sources 212 can improve matching of the bias currents I_B1 and I_B2, thus mitigating the magnitude of an input-referred offset voltage V_OS of the set of phase switches 252 and the OP-AMP 251, as well as possible noise contributions of the N-MOSFETs N10 and N12. However, temperature and process variations in the electronic components of the set of phase switches 252, the current control circuit 202, and the bias current sources 212 can result in the generation of an offset voltage V_OS between the inputs of the set of phase switches 252 and the OP-AMP 251 that receive the first and second bias currents I_B1 and I_B2. The sources of the offset voltage V_OS can be quantified based on a number of expressions.

A first contribution V_OS1 to the offset voltage V_OS can result from a mismatch in physical parameters between the N-MOSFETs N10 and N12, as described by the following expression:

$\begin{array}{cc}{V}_{\mathrm{OS}1}={\left(\frac{A_{\beta }}{\sqrt{\mathrm{WL}}}\right)}_{N10,N12}*\frac{1}{1+\frac{I_{\mathrm{SI}}*R_b}{\left(\frac{V_{\mathrm{GS}}-\mathrm{Vth}}{2}\right)}}*\left(V_T+I_{\mathrm{SI}}*R_{\mathrm{IN}}\right)& \mathrm{Equation}3\end{array}$

Where: A_β is a percentage mismatch parameter between the physical parameters of the N-MOSFETs N10 and N12;

• • WL is a theoretical area of the N-MOSFETs N10 and N12;
  • R_b is an average resistance value of the resistors R₂ and R₃;
  • V_GS is a gate-source voltage of the N-MOSFETs N10 and N12;
  • Vth is a threshold voltage of the N-MOSFETs N10 and N12;
  • V_T is equal to k*T/q; and
  • R_IN is an average resistance value of the resistors R_2—OP and R_3—OP in series with the switches S_2—OP and S_3—OP, respectively.A second contribution V_OS2 to the offset voltage V_OS can result from a mismatch in threshold voltage between the N-MOSFETs N10 and N12, as described by the following expression:

$\begin{array}{cc}{V}_{\mathrm{OS}2}={\left(\frac{A_{\mathrm{Vth}}}{\sqrt{\mathrm{WL}}}\right)}_{N10,N12}*\frac{1}{\left(\frac{V_{\mathrm{GS}}-\mathrm{Vth}}{2}\right)+I_{\mathrm{SI}}*R_b}*\left(V_T+I_{\mathrm{SI}}*R_{\mathrm{IN}}\right)& \mathrm{Equation}4\end{array}$

Where:A_Vth is a voltage mismatch parameter between the threshold voltages of the N-MOSFETs N10 and N12.A third contribution V_OS3 to the offset voltage V_OS can result from a mismatch in resistance magnitudes between the resistors R₂ and R₃, as described by the following expression:

$\begin{array}{cc}{V}_{\mathrm{OS}3}=\left(\frac{\Delta R_b}{R_b}\right)*\frac{1}{1+\frac{I_{\mathrm{SI}}*R_b}{\left(\frac{V_{\mathrm{GS}}-\mathrm{Vth}}{2}\right)}}*\left(V_T+I_{\mathrm{SI}}*R_{\mathrm{IN}}\right)& \mathrm{Equation}5\end{array}$

Where:ΔR_b is a resistance mismatch between the resistors R₂ and R₃.Equations 3 through 5 above thus represent contributions to the offset voltage V_OS based on the N-MOSFETs N10 and N12 operating in a strong inversion saturation region. A fourth contribution V_OS4 to the offset voltage V_OS can result from a mismatch in resistance magnitudes of the resistors R_2—OP and R_3—OP in series with the switches S_2—op and S_3—OP, respectively, as described by the following expression:

$\begin{array}{cc}{V}_{\mathrm{OS}4}=\left(\frac{\Delta R_{\mathrm{IN}}}{R_{\mathrm{IN}}}\right)*I_{\mathrm{SI}}*R_{\mathrm{IN}}& \mathrm{Equation}6\end{array}$

Where:ΔR_IN is a resistance mismatch between the resistors R_2—OP and R_3—OP in series with the switches S_2—OP and S_3—OP, respectively.A fifth contribution V_OS5 to the offset voltage V_OS can result from a mismatch in area of the BJTs Q1 and Q2, as described by the following expression:

$\begin{array}{cc}{V}_{\mathrm{OS}5}={\left(\frac{A_C}{\mathrm{AREA}}\right)}_{Q1,Q2}*V_T& \mathrm{Equation}7\end{array}$

Where: A_C is a percentage mismatch parameter between the collector currents of the BJTs Q1 and Q2; and

• • AREA is a theoretical area of the BJTs Q1 and Q2.Based on Equations 3 through 7 above, a total magnitude of the offset voltage V_OS can be described by the following expression:

V_OS=√{square root over (V_OS1²+V_OS2²+V_OS3²+V_OS4²+V_OS5²)}  Equation 8

A non-zero magnitude of the offset voltage V_OS can thus contribute to offset associated with the sense current I_SNS.

The offset voltage V_OS can be obtained by design optimization of these offset contributions based on Equations 3 through 8 above. As a result, offset and gain can be digitally calibrated for each phase of the spindle motor. Specifically, referring back to the example of FIG. 2, the ADC 78 samples and converts the sense voltage V_SNS—HS across the resistor R_F. As an example, a full conversion voltage scale V_ADC—FS of the ADC 78 can be proportional to the resistance magnitude of the resistor R_F, such that the conversion digital output code of the ADC 78 is independent on any process variations of the resistor R_F. Assuming the full conversion voltage scale V_ADC—FS can be expressed as I_ADC—REF*R_ADC, where R_ADC approximately matches the resistor R_F with a ratio of K and the current I_ADC—REF is the exact reference current, the sampled sense voltage V_SNS—HS can be expressed as a digital value D_ADC—OUT. Specifically, referring back to Equation 2, the digital value D_ADC—OUT can be expressed as follows:

$\begin{array}{cc}\begin{array}{c}{D}_{\mathrm{ADC\_OUT}}=\frac{V_{\mathrm{SNS\_HS}}}{V_{\mathrm{ADC\_FS}}}\\ =\frac{I_{\mathrm{SNS}}*R_F}{I_{\mathrm{ADC\_REF}}*R_{\mathrm{ADC}}}\\ =\frac{\left(\left(\frac{I_{\mathrm{PH\_X}}}{M_{\mathrm{PH\_X}}}\right)+I_{\mathrm{OS\_X}}+I_{\mathrm{SE}}\right)}{I_{\mathrm{ADC\_REF}}*K}\end{array}& \mathrm{Equation}9\end{array}$

Equation 9 also demonstrates the digital value for the magnitude of the respective one of the phase currents I_PH—A, I_PH—B, and I_PH—C that is the high-side sourcing phase current. Based on Equation 9, a linear relationship between the respective phase current I_PH—X and the respective digital value D_ADC—OUT can be described by the following expressions:

I _{PH — X}=GAIN_PH—X*D_ADC—OUT−OFFSET_PH—X   Equation 10

OFFSET_PH—X=M_PH—X*(I_OS—X+I_SE)   Equation 11

GAIN_PH—X=K*M_PH—X*I_ADC—REF   Equation 12

The offset and gain associated with each high-side phase can vary with process and temperature variations. In order to accurately sense the respective one of the phase currents I_PH—A, I_PH—B, and I_PH—C, the offset and gain calibration can be performed for each high-side phase of the spindle motor. For example, in the example of FIG. 2, the respective known high-side sourcing phase currents I_PH—A, I_PH—B, and I_PH—C can be provided to the spindle motor power regulator system 50, such as during operation of the spindle motor or externally through the respective high-side power transistors 56, 58 and 60. The high-side current sense system 68 and the ADC 78 can be configured to measure the magnitude of the respective known phase currents I_PH—A, I_PH—B, and I_PH—C and to generate the respective digital value, respectively. An optimization algorithm or routine can be employed to perform the calibration and extract and store conversion gain and/or offset information for each phase. As an example, the processor 80 can store the respective high-side gains GAIN_{PH A}, GAIN_{PH B}, and GAIN_{PH C} and the respective high-side offsets OFFSET_PH—A, OFFSET_PH—B, and OFFSET_PH—C in the digital format. The processor 80 can thus implement the stored high-side gain and/or offset information to subsequently calculate the respective high-side sourcing phase currents I_PH—A, I_PH—B, and I_PH—C by implementing Equation 10.

It is to be understood that the phase switch and OP-AMP circuit 250 is not intended to be limited to the example of FIG. 6. As an example, additional circuit configurations for each of the set of phase switches 252, current control circuit 202, and the bias current sources 212 are conceivable for the phase switch and OP-AMP circuit 250. Accordingly, the phase switch and OP-AMP circuit 250 can be configured in any of a variety of ways.

FIG. 7 illustrates an example of a low-side current-sense system 300 in accordance with an aspect of the invention. As an example, the low-side current-sense system 300 in the example of FIG. 7 can correspond to the low-side current-sense system 70 in the example of FIG. 2. As such, like reference numbers are used and reference is to be made to the example of FIG. 2 in the following description of the example of FIG. 7.

Similar to as described above in the example of FIG. 2, the low-side current-sense system 300 is configured to monitor a magnitude of one of the phase currents I_PH—A, I_PH—B, or I_PH—C that flows through a respective one of the low-side power FETs, demonstrated in the example of FIG. 7 as low-side power FETs LS_A, LS_B, LS_C. The low-side current-sense system 300 includes respective sets of sense FETs 302, 304, and 306. In the example of FIG. 7, the sense FETs 302 are demonstrated as a first N-FET N13 and a second N-FET N14, the sense FETs 304 are demonstrated as a third N-FET N15 and a fourth N-FET N16, and the sense FETs 306 are demonstrated as a fifth N-FET N17 and a sixth N-FET N18. As an example, each of the N-FETs N13 through N18 can have a gate area that is less than the gate area of the low-side power FETs LS_A, LS_B, and LS_C.

Each of the first and second N-FETs N13 and N14 are controlled at a gate by the low-side switching signal SW_LS_A that likewise controls the low-side power FET LS_A. Similarly, each of the third and fourth N-FETs N15 and N16 are controlled at a gate by the low-side switching signal SW_LS_B that likewise controls the low-side power FET LS_B, and each of the fifth and sixth N-FETs N17 and N18 are controlled at a gate by the low-side switching signal SW_LS_C that likewise controls the low-side power FET LS_C. The first N-FET N13 is coupled at a source to the phase node 158 and is configured to conduct a first reference current I_1—A that is a first portion of the phase current I_PH—A in response to the low-side control signal SW_LS_A. The second N-FET N14 is coupled at a source to the low-voltage power rail 64 and is configured to conduct a second reference current I_2—A to the low-voltage power rail 64 in response to the low-side control signal SW_LS_A. Similarly, the third N-FET N15 is coupled at a source to the phase node 160 and is configured to conduct a first reference current I_1—B that is a first portion of the phase current I_PH—B in response to the low-side control signal SW_LS_B. The fourth N-FET N16 is coupled at a source to the low-voltage power rail 64 and is configured to conduct a second reference current I_2—B from the low-voltage power rail 64 in response to the low-side control signal SW_LS_B. The fifth N-FET N17 is coupled at a source to the phase node 162 and is configured to conduct a first reference current I_1—C that is a first portion of the phase current I_PH—C in response to the low-side control signal SW_LS_C. The sixth N-FET N18 is coupled at a drain to the low-voltage power rail 64 and is configured to conduct a second reference current I_2—C from the low-voltage power rail 64 in response to the low-side control signal SW_LS_C.

It is to be understood that the low-side control signals SW_LS_A, SW_LS_B and SW_LS_C can be analog activation signals that are generated from the respective low-side drivers in the switching control circuit 52 as demonstrated in the example of FIG. 2, and can thus constitute one of the switching signals SW_A, SW_B and SW_C. In addition, the phase nodes 158, 160 and 162 in the example of FIG. 7 can be the same nodes corresponding, respectively, to the phase nodes 158, 160 and 162 in the example of FIG. 4. Furthermore, the drains of the N-FETs N13, N15, and N17 in the example of FIG. 7 can be connected respectively with the sources of the N-FETs N1, N3, and N5 in the example of FIG. 4.

The first and second reference currents I_1—A and I_2—A, as well as third reference current I_3—A that is conducted from the phase node 158, are provided to a set of phase switches 314. The phase switches 314 are controlled by a set of phase control signals LS_PH_A. Similarly, the first and second reference currents I_1—B and I_2—B, as well as third reference current I_3—B that is conducted from the phase node 160, are provided to a set of phase switches 316 controlled by a set of phase control signals LS_PH_B. Furthermore, the first and second reference currents I_1—C and I_2—C, as well as third reference current I_3—C that is conducted from the phase node 162, are provided to a set of phase switches 318 controlled by a set of phase control signals LS_PH_C. The phase control signals LS_PH_A, LS_PH_B, and LS_PH_C can collectively correspond to the phase control signals LS_PH generated by the switching controller 52 in the example of FIG. 2.

It is to be understood that, based on the flow of the first and third reference currents I_1—A and I_3—A into the phase node 158, the magnitude of the current flow through the low-side power FET LS_A can be greater than the magnitude of the output current I_PH—A flowing into the phase node 158 from the load (not shown). However, the magnitude of the first and third reference currents I_1—A and I_3—A can be significantly less than the magnitude of the output current I_PH—A, such that the difference in magnitudes between the current flow through the low-side power FET LS_A and the output current I_PH—A can be substantially negligible. It is also to be understood that the difference in magnitudes between the current flow through the low-side power FET LS_B and the output current I_PH—B, as well as the current flow through the low-side power FET LS_C and the output current I_PH—C, can likewise be substantially negligible.

The phase control signals LS_PH_A, LS_PH_B, and LS_PH_C are thus provided by the switching controller 52 to switch a respective one of the sets of reference currents I_1—A, I_2—A, and I_3—A; I_1—B, I_2—B, and I_3—B; and I_1—C, I_2—C, and I_3—C from an OP-AMP 320. Therefore, the phase control signal LS_PH_A switches currents I_REF generated from the OP-AMP 320 as the reference currents I_1—A, I_2—A, and I_3—A via the first set of phase switches 314. The phase control signals LS_PH_B and LS_PH_C thus disable the second and third sets of phase switches 316 and 318, respectively. Accordingly, the OP-AMP 320 can generate a low-side sense voltage V_SNS—LS that has a magnitude that is proportional to the magnitude of the phase current I_PH—A. Similarly, the reference currents I_1—B, I_2—B, and I_3—B or the reference currents I_1—C, I_2—C, and U_3—C could instead be switched from the OP-AMP 320 upon the switching controller 52 identifying that the phase current I_PH—B or I_PH—C, respectively, is the low-side sinking phase current, thus disabling the other two sets of the phase switches 314, 316, and 318.

In addition to the coupling of the respective reference currents I_REF from the OP-AMP 320, the sets of phase switches 314, 316, and 318 can also be configured to split the respective sets of reference currents I_1—A, I_2—A, and I_3—A; I_1—B, I_2—B, and I_3—B; and I_1—C, I_2—C, and I_3—C into a sense current, a sense offset current, and a pair of bias currents that collectively form the currents I_REF, similar to as described above regarding the high-side current sense system 150. As an example, the pair of bias currents can be approximately equal bias currents that flow through respective current paths of the respective one of the sets of phase switches 314, 316, and 318 and the OP-AMP 320, such that the bias currents set a magnitude of the sense current from which the low-side sense voltage V_SNS—LS is generated. Furthermore, the respective one of the sets of phase switches 314, 316, and 318 can be configured to pre-bias the electronic components of the OP-AMP 320 prior to the full activation of the respective one of the low-side power FETs LS_A, LS_B, and LS_C. Accordingly, transient effects that can affect the magnitude of the low-side sense voltage V_SNS—LS can be substantially mitigated.

Based on the above description of the low-side current-sense circuit 300, it is demonstrated that the low-side current-sense circuit 300 operates substantially similar to the high-side current-sense circuit 150. As an example, the OP-AMP 320 in the example of FIG. 7 can be configured as a substantially inverted version of the OP-AMP 251 in the example of FIG. 6, such as to include a reversed current-flow direction of the first and second reference currents I_1—X and I_2—X, and thus also of the first and second bias currents I_B1 and I_B2. For example, the OP-AMP 320 can include a current control circuit, similar to the current control circuit 202, that includes NPN BJTs and N-MOSFETs in the current paths for the first and second bias currents I_B1 and I_B2 and the third reference current I_3—X. Similarly, the OP-AMP 320 can include bias current sources that conduct the currents I_SE, I_SI, I_B1, and I_B2 from the voltage V_INT or the voltage V_EXT at the positive voltage rail 62, such as via P-MOSFETs in the case of the currents I_S1, I_B1, and I_B2.

Furthermore, it is to be understood that the direction of the flow of the low-side sense current can be from an internal voltage V_COM to the respective one of sense FETs N14, N16, and N18, or can be changed by adding one or more current mirrors to the OP-AMP 320. Accordingly, the low-side current-sense system 300 can be configured in any of a variety of ways. It is also to be understood that, in order to accurately sense the respective one of the phase currents I_PH—A, I_PH—B, and I_PH—C, the spindle motor power regulator system 50 in the example of FIG. 2 can be configured to perform the offset and gain calibration for each low-side phase of the spindle motor. The processor 80 can thus implement the stored low-side gain and/or offset information to subsequently calculate the respective low-side sourcing phase currents I_PH—A, I_PH—B, and I_PH—C by implementing Equation 10.

In view of the foregoing structural and functional features described above, certain methods will be better appreciated with reference to FIG. 8. It is to be understood and appreciated that the illustrated actions, in other embodiments, may occur in different orders and/or concurrently with other actions. Moreover, not all illustrated features may be required to implement a method.

FIG. 8 illustrates an example of a method 350 for determining individual phase currents of a disk-drive spindle motor in accordance with an aspect of the invention. At 352, a plurality of switching signals that control at least one power transistor are generated for each of the plurality of phases of the disk-drive spindle motor. The switching signals can be provided from a switching controller, and can be provided to a set of power transistors, such as a high-side and low-side power FET for each phase of the spindle motor. At 354, it is identified which of at least one of the plurality of phases through which the respective individual phase current is to be measured based on the plurality of switching signals. The measurement can be a CAP phase current, which can be a current that is substantially constantly sourced to one of the phases of the spindle motor in a commutation cycle, and of a GROUND phase current, which can be a current that is substantially constantly sunk from a second one of the phases of the spindle motor to a low-voltage power rail. The identification can be based on the switching signal having the greatest PWM duty-cycle in each PWM period of the commutation cycle in the case of the CAP phase current (i.e., relative to a SLOPE phase current) and the switching signal having no PWM duty-cycle in the case of the low-side sinking phase current.

At 356, a plurality of reference currents corresponding to the respective individual phase current are switched to a respective current sense system. The respective current sense system can include a high-side current sense system to measure the high-side sourcing phase current and a low-side current sense system to measure the low-side sinking phase current. The reference currents can be generated from a respective plurality of sense FETs arranged with respect to the respective one of the high-side or low-side FETs through which the respective phase current flows. At 358, the magnitude of the respective individual phase current of the at least one of the plurality of phases is measured based on the plurality of reference currents. A sense voltage having a magnitude that is proportional to the magnitude of the respective phase current can be generated from an OP-AMP in response to the reference currents.

At 360, a magnitude of one or more remaining phase currents is calculated based on the magnitude of the respective individual phase current. The phase voltage(s) can be provided to an ADC that converts the sense voltage to a digital value. The digital value of the high-side sourcing phase current and the low-side sinking phase current can be used to calculate the magnitude of the third phase current of the spindle motor. The digital values can also be implemented in a calibration routine for the subsequent measurement of the CAP phase currents. For example, the sourcing current can be measured individually through each of the phases of the spindle motor, and offset and/or gain information can be ascertained from the digital values. The offset and/or gain information can then be implemented in subsequent measurements of the CAP phase current through each of the phases of the spindle motor. Therefore, the magnitude of all three phase currents of the spindle motor can be identified by a respective processor, such that commutation speed information associated with the spindle motor can be implemented to adjust and/or control the rotation speed of the spindle motor.

What have been described above are examples of the invention. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the invention, but one of ordinary skill in the art will recognize that many further combinations and permutations of the invention are possible. Accordingly, the invention is intended to embrace all such alterations, modifications, and variations that fall within the scope of this application, including the appended claims.

Claims

1. A disk-drive spindle motor power regulator system comprising: a switching system comprising at least one power transistor for each of a plurality of phases of a disk-drive spindle motor;a switching controller configured to generate a plurality of switching signals configured to control the at least one power transistor for each of the plurality of phases of the disk-drive spindle motor;a current monitor configured to measure a magnitude of an individual phase current through at least one of the plurality of phases of the disk-drive spindle motor.

2. The system of claim 1, wherein the current monitor is configured to measure a first phase current that is substantially constantly sourced to a respective first one of the plurality of phases of the disk-drive spindle motor in a commutation cycle and to measure a magnitude of a second phase current that is substantially constantly sunk from a respective second one of the plurality of phases of the disk-drive spindle motor to a low voltage power rail in the commutation cycle.

3. The system of claim 1, wherein the current monitor comprises at least one current sense system configured to measure the magnitude of the individual phase current through the respective at least one of the plurality of phases of the disk-drive spindle motor.

4. The system of claim 3, wherein each of the at least one current sense system comprises: a first sense transistor configured to conduct a first reference current one of to and from a phase node associated with the respective one of the plurality of phases of the disk-drive spindle motor;a second sense transistor configured to conduct a second reference current one of to and from a power rail; andan operational amplifier (OP-AMP) configured to receive the first reference current, the second reference current, and a third reference current that flows one of to and from the phase node associated with the respective one of the plurality of phases of the disk-drive spindle motor and to generate a sense voltage that is substantially proportional to the individual phase current.

5. The system of claim 4, wherein the first sense transistor and the second sense transistor comprise a first of a plurality of sense transistor pairs that each correspond to a respective one of the plurality of phases of the spindle motor, and wherein the OP-AMP comprises a switching control circuit that is configured to selectively couple the OP-AMP with one of the plurality of sense transistor pairs for the OP-AMP to measure the corresponding individual phase current.

6. The system of claim 5, wherein the switching system couples the OP-AMP to the respective one of the plurality of sense transistor pairs in response to a set of phase control signals for the OP-AMP to measure one of a magnitude of a first phase current that is substantially constantly sourced to a respective first one of the plurality of phases of the disk-drive spindle motor in a commutation cycle and a magnitude of a second phase current that is substantially constantly sunk from a respective second one of the plurality of phases of the disk-drive spindle motor to a low voltage power rail in the commutation cycle.

7. The system of claim 3, wherein the plurality of phases comprises three phases, the at least one current sense system comprising: a high-side current sense system configured to measure a first phase current that is substantially constantly sourced to a respective first one of the plurality of phases of the disk-drive spindle motor in a commutation cycle based on a respective first one of the plurality of switching signals having a greatest duty-cycle in each pulse width modulation (PWM) period of the commutation cycle; anda low-side current sense system configured to measure a magnitude of a second phase current that is substantially constantly sunk from a respective second one of the plurality of phases of the disk-drive spindle motor to a low voltage power rail in the commutation cycle based on a respective second one of the plurality of switching signals having no duty-cycle.

8. The system of claim 7, wherein the high-side current sense system is further configured to generate a high-side sense voltage that is proportional to a magnitude of the first phase current and wherein the low-side current sense system is further configured to generate a low-side sense voltage that is proportional to a magnitude of the second phase current, and wherein the current monitor further comprises: an analog-to-digital converter (ADC) configured to convert each of the first and second sense voltages to digital values corresponding to the magnitudes of the first and second phase currents, respectively; anda processor configured to calculate a magnitude of a third phase current based on the digital values and to generate a feedback control signal corresponding to a commutation speed of the disk-drive spindle motor.

9. An integrated circuit comprising the disk-drive spindle motor power regulator system of claim 1.

10. A method for determining individual phase currents of a disk-drive spindle motor, the method comprising: generating a plurality of switching signals that control at least one power transistor for each of the plurality of phases of the disk-drive spindle motor;identifying which of at least one of the plurality of phases through which the respective individual phase current is to be measured based on the plurality of switching signals;switching a plurality of reference currents corresponding to the respective individual phase current to a respective current sense system;measuring the magnitude of the respective individual phase current of the at least one of the plurality of phases based on the plurality of reference currents; andcalculating a magnitude of one or more remaining phase currents based on the magnitude of the respective individual phase current.

11. The method of claim 10, wherein identifying which of the at least one of the plurality of phases through which the respective individual phase current is measured comprises: identifying measurement of a first phase current that is substantially constantly sourced to a respective first one of the plurality of phases of the disk-drive spindle motor in a commutation cycle based on a respective first one of the plurality of switching signals associated with the first phase current having a greatest pulse width modulation (PWM) duty-cycle in each PWM period of the commutation cycle; andidentifying a magnitude of a second phase current flowing that is substantially constantly sunk from a respective second one of the plurality of phases of the disk-drive spindle motor to a low voltage power rail in the commutation cycle based on a respective second one of the plurality of switching signals associated with the second phase current having no PWM duty-cycle;wherein measuring the magnitude of the respective individual phase current comprises measuring the magnitude of the first phase current and the second phase current.

12. The method of claim 11, further comprising converting the magnitude of the first phase current and the second phase current to respective digital values, and wherein calculating the magnitude of one or more remaining phase currents comprises calculating a magnitude of a third phase current based on the digital values.

13. The method of claim 11, further comprising: implementing a calibration routine to calculate at least one of offset and gain information associated with each of the plurality of phases of the disk-drive spindle motor; andstoring the at least one of the offset and gain information to compensate for at least one of process and temperature variations in measuring the magnitude of the first phase current.

14. The method of claim 13, wherein implementing the calibration routine comprises: measuring a sourcing current through each of the plurality of phases of the disk-drive spindle motor;generating digital values associated with the measured sourcing current through each of the plurality of phases of the disk-drive spindle motor; andcalculating the at least one of the offset and gain information based on the digital values.

15. The method of claim 10, further comprising: generating a first reference current one of to and from a phase node associated with the at least one of the plurality of phases of the disk-drive spindle motor via a first sense transistor; andgenerating a second reference current one of to and from a power rail via a second sense transistor;wherein switching a plurality of reference currents comprises switching the first and second reference currents to an operational amplifier (OP-AMP) configured to generate the sense voltage in response to the first reference current, the second reference current, and a third reference current that flows one of to and from the phase node associated with the at least one of the plurality of phases of the disk-drive spindle motor.

16. The method of claim 10, wherein switching the plurality of reference currents corresponding to the respective individual phase current to the respective current sense system comprises: switching a first plurality of reference currents corresponding to a first phase current flowing from a high-voltage power rail through a respective first one of the plurality of phases of the disk-drive spindle motor to a high-side current sense system; andswitching a second plurality of reference currents corresponding to a second phase current flowing through a respective second one of the plurality of phases of the disk-drive spindle motor to a low-side current sense system.

17. A disk-drive spindle motor power regulator system comprising: means for generating a plurality of switching signals associated with each of a first phase, a second phase, and a third phase, respectively, of the disk-drive spindle motor;means for generating a first phase current, a second phase current, and a third phase current through the first, second, and third phases respectively, of the disk-drive spindle motor in response to the plurality of switching signals;means for measuring a magnitude of two of the first, second, and third phase currents; andmeans for calculating a magnitude of a remaining one of the first, second, and third phase currents based on the measured magnitude of the two of the first, second, and third phase currents.

18. The system of claim 17, wherein the means for measuring comprises: means for generating a first sense voltage corresponding to a magnitude of a first one of the first, second, and third phase currents;means for generating a second sense voltage corresponding to a magnitude of a second one of the first, second, and third phase currents;means for switching a first one of the first, second, and third phase currents to the means for generating the first sense voltage; andmeans for switching a second one of the first, second, and third phase currents to the means for generating the second sense voltage in response to the plurality of switching signals.

19. The system of claim 18, wherein the means for generating the plurality of switching signals comprises means for identifying the first one of the first, second, and third phase currents that is substantially constantly sourced to a respective first one of the first, second, and third phases of the disk-drive spindle motor in a commutation cycle to be measured and for measuring the second one of the first, second, and third phase currents that is substantially constantly sunk from a respective second one of the plurality of phases of the disk-drive spindle motor to a low voltage power rail in the commutation cycle to be measured.

20. The system of claim 18, further comprising means for converting the first and second sense voltages to digital values, the means for calculating being configured to calculate the remaining one of the first, second, and third phase currents based on the digital values.