Patent Application
20230408556
This application claims the benefit under 35 U.S.C. § 119(a) of European Application No. 22179832.5 filed Jun. 20, 2022, the contents of which are incorporated by reference herein in their entirety.
Aspects of the present disclosure generally relate to a system for sensing a current through a transistor. Aspects of the present disclosure further relate to a DC-DC converter comprising one or more such systems. Aspects of the present disclosure are especially suitable for sensing a current through power switching transistors, such as power MOSFETs.
Transistors are used in electronic circuits in a variety of applications. Such applications may benefit or even necessitate that a current through one or more specific transistors is measured and regulated accordingly. One such application concerns DC-DC converters, in which a transistor is used as a switching element and can typically conduct a relatively large current.
Hereinafter, a DC-DC converter 100 known in the art is described with reference to
Switching module 102 comprises a high-side transistor MH and a low-side transistor ML, which are metal-oxide-semiconductor field-effect transistors (MOSFETs) in the example shown in
Input voltage supply VI may be a stable voltage source, such as a battery of an electronic device comprising said DC-DC converter 100. Converter module 101 may be configured to provide, at its output, an output voltage having a voltage level and a corresponding ripple. The skilled person will readily understand that characteristics of the output voltage signal, such as its voltage level and the ripple, may be determined or dictated by at least one of the input voltage, the switching frequency and drive strength (i.e., applied voltage level) for transistors MH, ML as provided by driving module 103, device characteristics of transistors MH, ML, a shaping circuit formed by inductor LO and output capacitor CO, and load ZL, among others. The output voltage signal can be applied to load ZL to deliver power thereto.
The exemplary DC-DC converter shown in
Alternatively to the configuration shown in
During operation, high-side transistor MH and/or low-side transistor ML may conduct a relatively large current. It may be of great importance to ensure that certain transistors operate correctly and conduct a current in a desired current range for safety reasons or for the purpose of controlling the transistors accordingly based on said current(s). This may especially apply to complex systems comprising a plurality of such transistors.
An example of such a complex system may be an electronic device that may comprise a plurality of DC-DC converters for converting an input voltage (or a plurality of input voltages) to a plurality of respective output voltage levels. In another example, the electronic device may comprise a multi-phase DC-DC converter, as appreciated by the person skilled in the art, which also comprises a plurality of individual converter modules, each with their own switching transistors.
Depending on the application, a current may flow in one or either direction through the transistor, e.g., from drain to source or from source to drain in the case of a MOS transistor. In particular, in DC-DC converter 100 shown in
Although the description above primarily focuses on DC-DC converters, it is noted that other applications involving transistors can similarly benefit significantly from being able to effectively and efficiently sense a current through a transistor.
As apparent from the above, there is a need for a system including one or more transistors in which a current can be sensed through said transistor(s) in an effective and efficient manner, for example with the purpose of more precise regulation of the output voltage level of the DC-DC converter.
A summary of aspects of certain embodiments disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these certain embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, this disclosure may encompass a variety of aspects and/or a combination of aspects that may not be set forth.
According to an aspect of the present disclosure, a system is provided. The system comprises a transistor module, comprising a primary transistor electrically connected between a first terminal and a second terminal, and a secondary transistor electrically connected between the first terminal and a third terminal, wherein a control terminal of the secondary transistor is electrically connected to a control terminal of the primary transistor. The system further comprises a current sensing module electrically connected to the transistor module and having an output terminal.
In accordance with the present disclosure, the system is configured to be operable in a first mode in which the current sensing module is configured to output, at the output terminal, a first output signal indicative of a current through the primary transistor in a first current direction based on a voltage difference between the third terminal and the second terminal, the first current direction being from the first terminal to the second terminal.
By using the system according to the present disclosure, the current sensing module does not need to be designed for potential high voltages at its input. In particular, when the primary transistor and secondary transistor are activated via their control terminal by a driving signal, the primary transistor may conduct a current accordingly and a voltage at the first terminal may be relatively low. However, when the primary transistor and secondary transistor are deactivated during operation, the voltage at the first terminal may be controlled by other elements or circuitry external to the system, such as a high-side switching transistor in the case of a synchronous DC-DC converter. This voltage may be relatively high compared to the voltage when the primary transistor and the secondary transistor are activated.
In other words, by including the secondary transistor as described above and sensing the current through the primary transistor based on the voltage across the third terminal and the second terminal, the current sensing module does not need to be directly electrically connected to the first terminal and is thus prevent or limited from being exposed to relatively high voltages.
Moreover, as described further below, current sensing in a second current direction opposite the first current direction can be implemented without including additional terminals to the transistor module, allowing for an area-efficient current sensing implementation.
The current sensing module may comprise a first sensing unit. The first sensing unit may comprise a first comparing unit having a first input terminal and a second input terminal and being configured to compare a voltage at an intermediate node, said voltage being received at the first input terminal, to a voltage corresponding to the voltage difference between the third terminal and the second terminal, received at the second input terminal, and to generate a first control signal based on a result of said comparison. Additionally, the first sensing unit may further comprise a first transistor connected between the output terminal of the current sensing module and the intermediate node. The first transistor may be configured to receive, at a control terminal thereof, the first control signal, and to enable a first current to flow between the output terminal and the intermediate node based on said first control signal. Said first current may correspond to the first output signal or may be used to generate the first output signal. In other words, the first current may either directly or indirectly correspond to the first output signal
The first sensing unit may further comprise an electrical network that is electrically connected between the first transistor and a reference terminal connected to a reference voltage, and the first current may additionally flow through said electrical network. Furthermore, the first comparing unit and the first transistor may together form at least part of a first negative feedback loop configured to adjust the first current such that the voltage at the first input terminal and the voltage at the second input terminal are substantially equal. The adjusted first current may correspond to the first output signal or may be used to generate the first output signal.
The electrical network may comprise a compensation transistor, and the current sensing module may further comprise a temperature compensation unit configured to sense a temperature at or near the primary transistor and to control a control terminal of the compensation transistor such that an on-resistance of the compensation transistor substantially corresponds to that of the primary transistor during operation.
Using the temperature compensation unit and the compensation transistor, a change in temperature of the primary transistor can be compensated for by adjusting a voltage at the control terminal of the compensation transistor, thereby changing its on-resistance. Said voltage can be adjusted based on a temperature at or near the primary resistor. In some embodiments, the temperature compensation unit can disable the temperature compensation by applying a same voltage to the control terminal of the compensation transistor as to the control terminal of the primary transistor. Here, it is noted that the compensation transistor may have a similar size (i.e., the same effective width) as the primary transistor, or be the relatively scaled version of the primary transistor size, which characteristics may be accounted for in the temperature compensation unit. The control from the temperature compensation unit may be implemented in various ways, such as using an mathematical function implemented by an analog circuit, a predefined model, or a look-up table.
The current sensing module may comprise a first switch configured to, when the system is operating in the first mode, provide a first voltage signal corresponding to the voltage difference between the third terminal and the second terminal to the output terminal of the current sensing module. Said first voltage signal may correspond to the first output signal or may be used to generate the first output signal. In a further embodiment, the system may further comprise a temperature compensation unit configured to adjust the first voltage signal based on a temperature at or near the primary transistor.
The current sensing module may further comprise an amplifying unit electrically connected between the transistor module and the first sensing unit. The amplifying unit may be configured to amplify the voltage difference between the third terminal and the second terminal. In addition, the current sensing module may then be configured to generate the first signal based on the amplified voltage difference between the third terminal and the second terminal.
The system may be further configured to be operable in a second mode in which the sensing module is configured to output, at the output terminal, a second output signal indicative of a current through the primary transistor in a second current direction, the second current direction being from the second terminal to the first terminal, which may be referred to as a ‘positive current’. To output the second output signal, the current sensing module may be configured to adjust a current through the secondary transistor such that a voltage at the third terminal substantially equals a voltage at the second terminal, and to output the second output signal based on the adjusted current.
The current sensing module described above, and thus being operable in both the first mode and the second mode, enables employing a bidirectional current sensing technique whilst only using one additional terminal in addition to the terminals of the primary transistor. As a result, a bidirectional current sensing module can be realized in an area-efficient and cost-effective manner.
The current sensing module may comprise a second sensing unit. The second sensing unit may comprise a second comparing unit configured to compare a voltage at the second terminal to a voltage at the third terminal, and to generate a second control signal based on a result of said comparison. The second sensing unit may further comprise a second transistor connected between the third terminal and a reference terminal. The second transistor may be configured to receive the second control signal at a control terminal thereof, and to enable a second current to flow from the reference terminal to the secondary transistor through said second transistor based on said second control signal. Said second current may correspond to the second output signal or may be used to generate the second output signal.
The second comparing unit and the second transistor may together form at least part of a second negative feedback loop configured to adjust the second current such that the voltage at the second terminal and the voltage at the third terminal are substantially equal.
The current sensing module may further comprise a current mirror configured to receive the second current in a first branch thereof and to generate a scaled second current signal corresponding to the second current times a predetermined factor in a second branch thereof. The second branch of the current mirror may be directly or indirectly electrically connected to the output terminal. The second current signal may correspond to the second output signal, or may be fed into a resistor to generate a second voltage signal corresponding to the second output signal.
The current sensing module may further comprise a second switch configured to, when the system is operating in the second mode provide the second voltage signal to the output terminal of the current sensing module as the second output signal.
The system may further comprise a third transistor electrically connected between the second terminal and the third terminal, and a blanking unit configured to generate a pulse having a predetermined width and to provide said pulse to a control terminal of the third transistor based on a voltage signal at the control terminal of the primary and secondary transistor. The pulse may be configured to enable the third transistor to form a low-impedance path between the second terminal and the third terminal for a duration corresponding to the predetermined width.
The primary transistor and the secondary transistor may have a scale ratio of NS:1, respectively. In some embodiments, NS may be greater than unity. As a result, additional power consumption due to a current flowing through the secondary transistor can be minimized. As an example, NS may be greater than 10, preferably greater than 100, and more preferably greater than 1,000. In some embodiments, NS may be equal to 10,000 or even higher.
The primary transistor and the secondary transistor may be integrated on a same semiconductor die. In some embodiments, the electrical connection between the terminals of the primary and secondary transistor may be implemented in an integrated manner on the semiconductor die. As a result, only four terminals for external contact need to be arranged on the semiconductor die to realize the transistor module, allowing for an area-efficient and cost-effective implementation of the transistor module while nonetheless enabling negative or bidirectional current sensing by the current sensing module in the system. Alternatively, the primary transistor may be integrated on a first semiconductor die and the secondary transistor may be integrated on a second semiconductor die separate from the first semiconductor die.
The current sensing module may be partially or even fully realized as an integrated circuit. The current sensing module may be at least partially integrated on a third semiconductor die different from the semiconductor die(s) on which the primary transistor and/or the secondary transistor are integrated, though the present disclosure is not limited thereto. In some embodiments, the current sensing module is at least partially realized using discrete components rather than integrated components.
The primary transistor and the secondary transistor may be metal-oxide-semiconductor field-effect transistors (MOSFETs). Furthermore, in some embodiments, one or more of the above-described first transistor, second transistor and third transistor may be a MOSFET. As an example only, the primary transistor and the secondary transistor may be n-type enhancement mode MOSFETs.
The transistor module may further comprise a power transistor electrically connected between the first terminal and a fifth terminal. A control terminal of the power transistor may be electrically connected to the second terminal or to a reference voltage. The current through the primary transistor additionally substantially flows through the power transistor.
Since the current through the primary transistor is substantially equal to the current through the power transistor due to the series-connection, a sensed current through the primary transistor using the system according to the present disclosure also substantially reflects the current through the power transistor.
The power transistor may be configured to be always on (i.e., activated), and a current path from the fifth terminal to the second terminal may be provided by activating the primary transistor to enable a current flow between the first terminal and the second terminal.
In a preferred embodiment, the power transistor may be a Gallium Nitride, ‘GaN’, based high electron mobility transistor, ‘HEMT’, and may be a depletion mode transistor, and the primary transistor may be Silicon, ‘Si’, based. The power transistor may be integrated on a fourth semiconductor die different from the semiconductor die(s) on which the current sensing module, the primary transistor and the secondary transistor are integrated.
Moreover, the power transistor may have a higher voltage handling capability than the primary transistor. To that end, the use of a GaN HEMT device as the power transistor is especially useful, since this type of transistor and its technology typically allow for a relatively high voltage rating. Rather than directly connecting the primary transistor to external circuitry, the power transistor may be connected thereto instead. When the power transistor is rated at a higher voltage, it can handle high voltages imposed on the fifth terminal by external circuitry and can thereby protect a remainder of the system from such high voltages. A voltage rating or voltage handling capability may, for example, reflect a breakdown voltage of the transistor.
According to another aspect of the present disclosure, a DC-DC converter is provided. The DC-DC converter comprises a first system configured as the system in accordance with the above. The primary transistor of the first system corresponds to a switching transistor of the DC-DC converter.
The DC-DC converter may further comprise a second system configured as the system in accordance with the above. The DC-DC converter may comprise a high-side switching transistor and a low-side switching transistor. In that case, the primary transistor of the first system may correspond to a high-side switching transistor of the DC-DC converter, and a primary transistor of the second system may correspond to a low-side switching transistor of the DC-DC converter.
Next, the present disclosure will be described in more detail with reference to the appended drawings, wherein:
The present disclosure is described in conjunction with the appended FIGS. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
In the appended FIGS., similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.
Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” As used herein, the terms “connected,” “coupled,” or any variant thereof means any connection or coupling, either direct or indirect, between two or more elements; the coupling or connection between the elements can be physical, logical, electromagnetic, or a combination thereof. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the detailed description using the singular or plural number may also include the plural or singular number respectively. The word “or,” in reference to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.
The teachings of the technology provided herein can be applied to other systems, not necessarily the system described below. The elements and acts of the various examples described below can be combined to provide further implementations of the technology. Some alternative implementations of the technology may include not only additional elements to those implementations noted below, but also may include fewer elements.
These and other changes can be made to the technology in light of the following detailed description. While the description describes certain examples of the technology, and describes the best mode contemplated, no matter how detailed the description appears, the technology can be practiced in many ways. Details of the system may vary considerably in its specific implementation, while still being encompassed by the technology disclosed herein. As noted above, particular terminology used when describing certain features or aspects of the technology should not be taken to imply that the terminology is being redefined herein to be restricted to any specific characteristics, features, or aspects of the technology with which that terminology is associated. In general, the terms used in the following claims should not be construed to limit the technology to the specific examples disclosed in the specification, unless the detailed description section explicitly defines such terms. Accordingly, the actual scope of the technology encompasses not only the disclosed examples, but also all equivalent ways of practicing or implementing the technology under the claims.
To reduce the number of claims, certain aspects of the technology are presented below in certain claim forms, but the applicant contemplates the various aspects of the technology in any number of claim forms.
In
Here, it is noted that a transistor being electrically connected between two terminals is defined as the drain or collector terminal of the transistor being electrically connected to one of said two terminals, and the source or emitter terminal being electrically connected to the other of said two terminals. As a result, a current can flow between the two terminals under appropriate operating conditions, such as a particular gate-source voltage or base-emitter voltage. Furthermore, a ‘control terminal’ of the transistor is herein defined as the gate terminal or base terminal of the transistor, whichever applies.
Furthermore, in
Primary transistor MP and secondary transistor MS can be activated by applying a control voltage VC to the control terminals thereof via fourth terminal 11d. Depending on said control voltage VC as well as a voltage at first terminal 11a and second terminal 11b, a current will flow through primary transistor MP in a first current direction from first terminal 11a to second terminal 11b, or in a second current direction from second terminal 11b to first terminal 11a. In this embodiment, the voltage at second terminal 11b may be a reference voltage, such as ground (VGND).
System 1 as shown in
In particular, the impedance presented by current sensing module 20 in the first mode may be large enough to prevent or at least limit a current through secondary transistor MS and thereby increase the accuracy. For example, the impedance presented by current sensing module 20 at third terminal 11c in the first mode may be at least 10 kΩ, preferably at least 100 kΩ, and more preferably at least 1 MΩ. Additionally or alternatively, the impedance presented by current sensing module 20 at third terminal 11c in the first mode may be larger than an on-resistance (i.e., channel resistance) of primary transistor MP and/or secondary transistor MS during normal operation when activated, for example at least 10× larger, preferably at least 100× larger, more preferably at least 1000× larger. For example, the channel resistance of primary transistor MP may be about 1 mΩ when driven at control terminal 11d, the channel resistance of the secondary transistor MS may be about 10Ω when driven at control terminal 11d, and the impedance presented by current sensing module 20 may be greater than 1 MΩ. However, the present application is not limited to any such values.
Current sensing module 20 may generate the first output signal in various ways. For example, a model or a look-up table may be used to relate the voltage difference to a particular current value and to generate an appropriate output signal as the first output signal. Other approaches in accordance with the present disclosure will be described with reference to
In addition to the above, system 1 may be operable in a second mode in which the current through primary transistor MP flows in the second current direction during operation. In this mode, contrary to the first mode, the voltage at first terminal 11a will decrease with respect to the voltage at second terminal 11b due to the current flow in the second current direction. In particular, the voltage at first terminal 11a will be the voltage at second terminal 11b minus a voltage across primary transistor MP, which voltage drop depends on the current through primary transistor MP and an on-resistance thereof. Assuming current sensing module 20 (e.g., each of first sensing unit 21 and second sensing unit 22) initially presents a relatively high impedance between second terminal 11b and third terminal 11c during at least part of the operation in the first mode, a current through secondary transistor MS and hence the voltage drop across secondary transistor MS will be relatively small. As a result, and since secondary transistor MS is also activated by control voltage VC the voltage VSNS at third terminal 11c will become substantially equal to the voltage at first terminal 11a.
Current sensing module 20, or second sensing unit 22 in some embodiments, may then be configured to adjust a current through secondary transistor MS such that the voltage at third terminal 11c is substantially equal to the voltage at second terminal 11b. In this state, since the voltages at all corresponding terminals of primary transistor MP and secondary transistor MS are equal, a current through secondary transistor MS will be a function of at least the current through primary transistor MP and a relative of secondary transistor MS compared to primary transistor MP. For example, when the voltages at all corresponding terminals are equal and primary transistor MP has an effective width or scale of NS times that of secondary transistor MS, then the current through secondary transistor MS will be the current through primary transistor MP divided by said relative scaling NS. The current through secondary transistor MS may in turn be used by current sensing module 20 (e.g., by second sensing unit 22) to generate a second output signal indicative of a current through primary transistor MP in the second current direction. Said second output signal may then be provided to output terminal 23.
Current sensing module 20 (e.g., second sensing unit 22) may generate the second output signal in various ways. For example, a model or a look-up table may be used to relate the current through secondary transistor MS to a particular current through primary transistor MP and to generate an appropriate output signal as the second output signal. Other approaches in accordance with the present disclosure will be described with reference to
When system 1 is operating in the first mode, second sensing unit 22 may be configured to be disabled manually or automatically, or may be configured to present a high impedance to transistor module 10, thereby having little to no impact on system 1 in this mode. This may for example be realized using a control mechanism operating based on a polarity of the voltage difference between second terminal 11b and third terminal 11c.
Similarly, when system 1 is operating in the second mode, first sensing unit 21 may be configured to be disabled manually or automatically, or may be configured to present a high impedance to transistor module 10, thereby having little to no impact on system 1 in this mode.
When system 1 is configured to be operable in either the first mode and the second mode, bidirectional current sensing can be realized for currents through primary transistor MP. In the embodiment shown in
In
Power transistor MPT may be configured as an ‘always-on’ device. For example, power transistor MPT may be a depletion-mode transistor. A current through power transistor MPT can then be controlled by activating or deactivating primary transistor MP by controlling the control terminal thereof accordingly, for example using a driving circuit (not shown). In other words, primary transistor MP may act as a switch for enabling a current through power transistor MPT, and primary transistor MP is configured to enable a current flow through said power transistor MPT based on a voltage at the control terminal (e.g., gate terminal) of primary transistor MP.
Power transistor MPT may have a high voltage handling capability and current-handling capability and may thus be particularly useful in application requiring high power handling, such as various types of converters (e.g., DC-DC, AC-DC or DC-AC), circuit breakers or other switching circuits.
In an embodiment, power transistor MPT may be a gallium-nitride (GaN) based high electron mobility transistor (HEMT). For example, power transistor MPT may have a voltage rating of over 500 V, such as 650 V. In turn, primary transistor MP (and preferably also secondary transistor MS) may be a silicon (Si) based MOSFET, which may have a lower voltage rating than power transistor MPT, such as 50 V or 30 V. Therefore, if transistor module 10′ is electrically connected to an external node via fifth terminal 11e, power transistor MPT may have a suitable voltage handling capability to handle voltages during operation, while primary transistor MP is configured to enable or disable power transistor MPT by enabling or disabling a corresponding current path.
During operation, when primary transistor MP is activated, substantially all of the current flowing through power transistor MPT will also flow through primary power transistor MP, such that a remaining portion of system 1 of
In
DC-DC converter 50 may further comprise a controller 30 configured to control (e.g., enable or disable) various components thereof. For example, a driving module (e.g., driving module 103 of
High-side switching transistor MH is electrically connected between an input voltage VIN received from an input voltage supply (not shown), and a first terminal of inductor L. Low-side switching transistor ML is electrically connected between first terminal 11a, which is connected to the first terminal of inductor L, and second terminal 11b, which is electrically connected to a ground potential VGND. A switch node VSW is electrically connected to the first terminal of inductor L, and a voltage at said switch node may for example depend on which transistor among high-side and low-side switching transistor MH, ML is activated, and on a current through said activated transistor. A second terminal of inductor L is connected to an output node Vo of DC-DC converter 50. Furthermore, an output capacitor CO may be electrically connected between output node Vo and ground potential VGND. Input capacitor CI of
In another embodiment, transistor module 10 may be replaced with transistor module 10′ of
Current sensing module 20 may further comprise an amplifying unit formed by amplifier AMP and a resistive feedback network, the latter being comprised of a second resistor R2 and a third resistor R3. Amplifier AMP may be an operational amplifier. In this configuration, a voltage VAN at an output of amplifier AMP is equal to VAN=VSNS*(1+R2/R3). In an example, R2/R3 is selected such that VAN=100*VSNS. In another example, R2≈0, in which case the amplifying unit has an amplification factor substantially equal to unity and effectively forms a buffer, such that VAN≈VSNS. Amplifier AMP may present a high impedance between second terminal 11b and third terminal 11c. For convenience, a biasing circuit for amplifier AMP is omitted from
In the embodiment shown in
First comparing unit CMP1 compares a voltage at its non-inverting input to a voltage at its inverting input, and outputs a first control signal in accordance with a result of the comparison to a control terminal (e.g., a gate terminal) of first transistor M1.
In the first mode, since VSNS>VGND, first comparing unit CMP1 and first transistor M1 form a first negative feedback loop in which a first current through first transistor M1 is adjusted until the voltage at the inverting input of first comparing unit CMP1 equals the voltage at its non-inverting input. In other words, in absence of the above-described amplifying unit, the voltage difference between third terminal 11c and second terminal 11b is provided at the inverting input of first comparing unit CMP1 via the first negative feedback loop. If the amplifying unit is included, the output voltage VAN of amplifier AMP is provided at the inverting input of first comparing unit CMP1. In the embodiment shown in
The first current generated by first sensing unit 21 in the first mode may then correspond directly to the first output signal. Alternatively, the first current is fed into a resistor RX coupled between output terminal 23 and a reference voltage VREF, which resistor RX may be external to current sensing module 20 and may be external to system 1, to generate a corresponding first voltage at output terminal 23 which can be used by a controller external to DC-DC converter 50.
However, in the second mode, since VSNS≈VGND, the output voltage VAN of amplifier AMP will be substantially equal to zero, such that the inverting input of first comparing unit CMP1 will also be substantially equal to zero. As a result, first sensing unit 21 is automatically disabled, and hence the first current is substantially equal to zero.
First comparing unit CMP1 may be a high gain amplifier, such as an operational amplifier or a transconductor. A gain of first comparing unit CMP1 increases the closed-loop gain of the first negative feedback loop and, hence, can improve a current sensing accuracy of first sensing unit 21 in the first mode.
In the embodiment shown in
In the second mode, when initially VSNS<VGND, second comparing unit CMP2 and second transistor M2 form a second negative feedback loop in which a second current through second transistor M2 is adjusted until the voltage at the inverting input of second comparing unit CMP2 substantially equals the voltage at its non-inverting input, i.e., until VSNS≈VGND. The second current also substantially flows through low-side sensing transistor MLS, since first sensing unit 21 is disabled in the second mode or has a high input impedance. Under this condition, low-side sensing transistor MLS and low-side switching transistor ML are effectively fully in parallel, such that the second current is substantially equal to the current through low-side switching transistor ML divided by NS, wherein NS is the relative scaling of low-side switching transistor ML with respect to low-side sensing transistor MLS.
The second current generated by second sensing unit 21 in the second mode may then correspond directly to the second output signal. Alternatively, a scaled second current is provided to output terminal 23 as the second output signal via a cascoded current mirror formed by transistors M4-M7 and coupled to reference voltage VCC, as will be appreciated by the person skilled in the art. In some embodiments, cascode transistors M6 and M7 may be omitted, and the current mirror may be formed only by transistors M4 and M5. The (cascoded) current mirror may have a scaling factor NC, such that a current in a first branch of the current mirror formed by transistor M5 (and transistor M7) is NC times a current in a second branch formed by transistor M4 (and transistor M6). Hence, the second output signal may be current corresponding to iL/(NS*NC). Similarly, to the first current, the second current may be fed into resistor RX to generate a corresponding second voltage at output terminal 23 which can be used by a controller external to DC-DC converter 50.
However, in the first mode, since VSNS>VGND, second comparing unit CMP2 may provide a ‘low’ signal to second transistor M2, such that the second current is substantially equal to zero. In other words, in the first mode, second sensing unit 22 is automatically (substantially) disabled.
To have a same absolute current sensing ratio for both currents in the first current direction and currents in the second current direction, values for the various components can be chosen such that Ron_L=(Ron1+R1)*R3/[NC*NS*(R2+R3)]. Under this condition, the first output signal and the second output signal will have a substantial equal sensitivity to a current flowing through low-side switching transistor ML.
Second comparing unit CMP2 may be a high gain amplifier, such as an operational amplifier or a transconductor. A gain of second comparing unit CMP2 increases the closed-loop gain of the second negative feedback loop and, hence, can improve a current sensing accuracy of second sensing unit 22 in the second mode.
It will be appreciated that, while system 1 is applied to low-side switching transistor ML in
To mitigate parasitic impedance impacts on the current sensing accuracy during turn-on and turn-off transitions at the control terminals of low-side switching transistor ML (and/or high-side switching transistor MH), system 1 may further comprise a third transistor M3 electrically connected between second terminal 11b and third terminal 11c, and a blanking unit configured to generate a voltage pulse VB having a predetermined width and to provide said pulse to a control terminal of the third transistor based on VGL (or VGH). The voltage pulse may be configured to enable the third transistor to form a low-impedance path between second terminal 11b and third terminal 11c for a duration corresponding to the predetermined width. The predetermined width can be set in accordance with a time required for the control terminal voltage to settle (e.g., a gate charging time). When low-side switching transistor ML and low-side sensing transistor MLS are turned off (i.e., when VGL is ‘low’), blanking unit 24 may be configured to activate third transistor M3 to avoid false triggering of current sensing module 20.
In some embodiments, at least part of current sensing module 20 is realized in an integrated circuit. In some embodiments, current sensing module 20 is implemented as a separate integrated circuit with respect to transistor module 10. In some embodiments, system 1 (e.g., transistor module 10 and current sensing module is formed as a single integrated circuit. In some embodiments, at least part of DC-DC converter 50 is formed as a single integrated circuit.
In
In DC-DC converter 50′, current sensing module 20 generates voltages instead of currents as the first and second output signal. In particular, first sensing unit 21 directly uses an output voltage of amplifier AMP and provides said output voltage of amplifier AMP as the first output signal to output terminal 23 via a first switch S1. Current sensing module 20 may further comprise a first capacitor C1 electrically connected between output terminal 23 and a reference terminal (e.g., ground). Alternatively, first capacitor C1 is external to current sensing module 20 or external to system 1.
First switch S1 may be controlled by first switch voltage VS1 generated by a signal generation unit 26 based on a voltage VGL at the control terminal of low-side switching transistor ML and at third terminal 11c with respect to second terminal 11b. For example, signal generation unit 26 may detect whether low-side switching transistor ML is activated based on VGL, and may in turn determine whether the current therethrough is in the first or second current direction based on the voltage difference between second and third terminal 11b, 11c. If the current direction is the first current direction, first switch S1 is activated, and if the current direction is the second current direction, first switch S1 is deactivated. In other words, first switch S1 is activated in the first mode and deactivated in the second mode.
Optionally, temperature compensation unit 25 may be configured to adjust the second voltage signal to correct for a temperature at or near low-side switching transistor ML prior to providing it as the first output signal to output terminal 23 via first switch S1. As an example only, temperature compensation unit 25 may add (or subtract) a voltage value to (or from) the second voltage signal based on a look-up table to correct for a change in on-resistance of low-side switching transistor ML due to a change in temperature.
Further to the above, in DC-DC converter 50′, second sensing unit 22 may be configured to generate a second voltage signal by feeding the (scaled) second current into a fourth resistor R4, and provides said second voltage signal to output terminal 23 via a second switch S2. Similarly to first switch S1, second switch S2 may be controlled by second switch voltage VS2 generated by signal generation unit 26 based on a voltage VGL at the control terminal of low-side switching transistor ML and at third terminal 11c with respect to second terminal 11b. If the current direction is the first current direction, second switch S2 is deactivated, and if the current direction is the second current direction, second switch S2 is activated. In other words, second switch S2 is deactivated in the first mode and activated in the second mode.
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The ensuing description above provides preferred exemplary embodiment(s) only, and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the ensuing description of the preferred exemplary embodiment(s) will provide those skilled in the art with an enabling description for implementing a preferred exemplary embodiment of the disclosure, it being understood that various changes may be made in the function and arrangement of elements, including various modifications and/or combinations of features from different embodiments, without departing from the scope of the present disclosure as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 22179832.5 | Jun 2022 | EP | regional |
