Patent Application
20240356510
Aspects of the present disclosure relate generally to current sensing, and in particular, to a current sensor configured to sense (e.g., high side) current with a common mode voltage reduction or re-registration.
Many devices/circuits require monitoring a load current they draw from a voltage source, such as a battery, battery charger, voltage regulator, or power management integrated circuit (PMIC). In such scenarios, current sensors are used to sense the load current, and generate a current signal indicative of the load current. Additionally, in such scenarios, current management circuits may be employed to receive current signals from current sensors, and control the currents drawn by devices/circuits for many different reasons, such as power efficiency, thermal control, overcurrent protection, and others.
The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.
An aspect of the disclosure relates to an apparatus. The apparatus includes: a resistive device; a first capacitor selectively coupled in parallel with the resistive device; a second capacitor selectively coupled in parallel with the resistive device; and a common mode voltage source selectively coupled to respective first terminals of the first and second capacitors.
Another aspect of the disclosure relates to a method. The method includes generating a first voltage including a first common mode voltage across a resistive device; transferring the first voltage including the first common mode voltage across first and second capacitors during a first phase of operation; and re-referencing the first voltage across the first and second capacitors with a second common mode voltage during a second phase of operation.
Another aspect of the disclosure relates to an apparatus. The apparatus includes means for generating a first voltage including a first common mode voltage across a resistive device; means for transferring the first voltage including the first common mode voltage across first and second capacitors during a first phase of operation; and means for re-referencing the first voltage across the first and second capacitors with a second common mode voltage during a second phase of operation.
Another aspect of the disclosure relates to a wireless communication device. The wireless communication device includes: at least one antenna; a transceiver coupled to the at least one antenna; an integrated circuit (IC) including one or more signal processing cores coupled to the transceiver; a battery coupled to the one or more signal processing cores; and a current sensor coupled to the battery, wherein the current sensor comprises: a resistive device; a first capacitor selectively coupled in parallel with the resistive device; a second capacitor selectively coupled in parallel with the resistive device; and a common mode voltage source selectively coupled to respective first terminals of the first and second capacitors.
To the accomplishment of the foregoing and related ends, the one or more implementations include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of various implementations may be employed and the description implementations are intended to include all such aspects and their equivalents.
The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.
The current sensor 100 includes a voltage source 110, a current sensing resistive device RS, and a load 120, all coupled in series with each other. The voltage source 110 may be any type of voltage source, such as a battery, a battery charger, a voltage regulator, a power management integrated circuit (PMIC), or other. The current sensing resistive device RS may be a resistor (e.g., thin- or thick-film resistor, discrete resistor, etc.) or a semiconductor device (e.g., a field effect transistor (FET)). The load 120 may be one or more cores of a system on chip (SOC), an integrated circuit (IC), a discrete circuit, passive and/or active loads, or other. The voltage source 110 supplies a load current IL to the load 120 via the current sensing resistive device RS.
The current sensor 100 further includes a negative feedback current sense amplifier 130 including input resistors R1− and R1+, feedback resistors R2+ and R2−, and differential operational amplifier 132. The input resistor R1− is coupled between a first terminal of the current sensing resistive device RS (e.g., a node between the voltage source 110 and the current sensing resistive device RS) and a negative input (−) of the operational amplifier 132. The input resistor R1+ is coupled between a second terminal of the current sensing resistive device RS (e.g., a node between the current sensing resistive device RS and the load 120) and a positive input (+) of the operational amplifier 132. The feedback resistor R2+ is coupled between a positive output (+) and the negative input (−) of the operational amplifier 132. The feedback resistor R2− is coupled between a negative output (−) and the positive input (+) of the operational amplifier 132.
In operation, the voltage source 110 generates a supply voltage (e.g., V1) to produce a load current IL flowing to the load 120 via the current sensing resistive device RS. The load current IL flowing through the current sensing resistive device RS produces a voltage ΔVi=V1−V2 across the resistive device RS, where the voltage V1 is at the first terminal of the current sensing resistive device RS and voltage V2 is at the second terminal of the current resistive device RS. Accordingly, the voltage ΔVi across the current sensing resistive device RS is a measure or a function of the load current IL in accordance with Ohm's law (e.g., ΔVi=V1−V2=IL*RS, where RS also represents the resistance of the current sensing resistive device RS).
Via the input resistors R1− and R1+, the voltage ΔVi across the current sensing resistive device RS is provided to the differential inputs of the negative feedback current sense amplifier 130. The negative feedback current sense amplifier 130 amplifies the voltage ΔVi with a gain G of −R2/R1 to generate an output voltage ΔVo related to the load current IL (e.g., ΔVo=G*ΔVi=G*IL*RS). An analog-to-digital converter (ADC) may be coupled to the output of the negative feedback current sense amplifier 130 to convert the output voltage ΔVo into a digital signal for load current IL monitoring and management purposes.
A drawback of the current sensor 100 is that the voltages V1 and V2 or common mode voltage Vcmi (e.g., Vcmi=(V1+V2)/2) associated with the voltage ΔVi across the current sensing resistive device RS may be too high for the devices or FETs of the operational amplifier 132. For example, the operational amplifier 132 may have devices that are rated for a maximum gate-to-source voltage (Vgs) of five (5) Volts (V). However, if the voltage source 110 includes two or three stacked battery cells, where each cell generates 5V, the common mode voltage Vcmi may be around 10-15V. Thus, the operational amplifier 132 may not be appropriate in such case, where the high voltages (e.g., 10-15V) are beyond the maximum safety voltage levels for the operational amplifier 132.
In particular, the current sensor 200 includes a first voltage source (or a load) 210, a current sensing resistive device RS, and a second voltage source (or a load) 220, all coupled in series. In some cases, the first voltage source 210 generates a voltage V1 greater than a voltage V2 generated by the second voltage source 220 operating as a load in such case, where a load current IL flows from the first voltage source 210 to the second voltage source 220. In other cases, the second voltage source 220 generates a voltage V2 greater than a voltage V1 at the first voltage source 210 operating as a load in such case, where a load current IL flows from the second voltage source 220 to the first voltage source 210. Thus, the current sensor 200 may sense bi-directional load current IL. Similarly, the first or second voltage sources (or loads) 210 and 220 may be implemented as a battery, a battery charger, a voltage regulator, a PMIC, one or more cores of an SOC, an IC, a discrete circuit, passive and/or active loads, or other. The current sensing resistive device RS may be a resistor (e.g., thin- or thick-film resistor, discrete resistor, etc.) or a semiconductor device (e.g., FET).
The current sensor 200 further includes a set of switching devices M1 to M8, a first capacitor C1, a second capacitor C2, and an integrating amplifier 230. Each of the switching devices M1 to M8 may be implemented as an n-channel metal oxide semiconductor field effect transistor (NMOS FET). The first and second capacitors C1 and C2 may each be implemented as a polarized capacitor including a positive terminal (+) and a negative terminal (−). The integrating amplifier 230, in turn, includes a differential operational amplifier 232 and a pair of feedback capacitors C3+ and C3− coupled between positive (+) and negative (−) outputs and negative (−) and positive (+) inputs of the operational amplifier 232, respectively.
The first and seventh switching devices M1 and M7 are coupled in series between a first terminal of the current sensing resistive device RS and the negative input (−) of the operational amplifier 232 of the integrating amplifier 230. That is, the first switching device M1 includes a drain coupled to the first terminal of the current sensing resistive device RS, a gate configured to receive a first control signal ϕ1, and a source coupled to a first intermediate node n1. The seventh switching device M7 includes a drain coupled to the first intermediate node n1, a gate configured to receive a second control signal ϕ2, and a source coupled to the negative input (−) of the operational amplifier 232.
Similarly, the second and eighth switching devices M2 and M8 are coupled in series between a second terminal of the current sensing resistive device RS and the positive input (+) of the operational amplifier 232 of the integrating amplifier 230. That is, the second switching device M2 includes a drain coupled to the second terminal of the current sensing resistive device RS, a gate configured to receive the first control signal ϕ1, and a source coupled to a second intermediate node n2. The eighth switching device M8 includes a drain coupled to the second intermediate node n2, a gate configured to receive the second control signal ϕ2, and a source coupled to the positive input (+) of the operational amplifier 232.
The first capacitor C1 and third switching device M3 are coupled in series between the first and second intermediate nodes n1 and n2. That is, the first capacitor C1 includes a positive terminal (+) coupled to the first intermediate node n1, and a negative terminal coupled to a drain/source of the third switching device M3. The third switching device M3 includes a gate configured to receive the first control signal ϕ1, and a source/drain coupled to the second intermediate node n2. The drain/source and source/drain of the third switching device M3 may be drain and source when the load current IL flows from the first voltage source 210 to the second voltage source 220, or source and drain when the load current IL flows from the second voltage source 220 to the first voltage source 210. Additionally, the fourth switching device M4 is coupled between the drain/source of the third switching device M3 and a source of a target common mode voltage Vcmt. That is, the fourth switching device M4 includes a drain coupled to the drain/source of the third switching device M3, a gate configured to receive the second control signal ϕ2, and a source coupled to the source of the target common mode voltage Vcmt.
Similarly, the sixth switching device M6 and the second capacitor C2 are coupled in series between the first and second intermediate nodes n1 and n2. That is, the sixth switching device M6 includes a drain/source coupled to the first intermediate node n1, a gate configured to receive the first control signal ϕ1, and a source/drain coupled to a negative terminal (−) of the second capacitor C2. The drain/source and source/drain of the sixth switching device M6 may be drain and source when the load current IL flows from the first voltage source 210 to the second voltage source 220, or source and drain when the load current IL flows from the second voltage source 220 to the first voltage source 210. The second capacitor C2 includes a positive terminal (+) coupled to the second intermediate node n2. Additionally, the fifth switching device M5 is coupled between the source/drain of the sixth switching device M6 and the source of the target common mode voltage Vcmt. That is, the fifth switching device M5 includes a drain coupled to the source/drain of the sixth switching device M6, a gate configured to receive the second control signal ϕ2, and a source coupled to the source of the target common mode voltage Vcmt.
The current sensor 200 includes a control circuit 240 configured to generate the first and second control signals ϕ1 and ϕ2. In operation, in accordance with a first phase of operation, the control circuit 240 asserts (e.g., sets to a logic high) the first control signal ϕ1 and deasserts (e.g., sets to a logic low) the second control signal ϕ2. The asserted first control signal ϕ1 turns on switching devices M1, M2, M3, and M6, and the deasserted second control signal ϕ2 turns off switching devices M4, M5, M7, and M8. The turned-on switching devices M1, M2, M3, and M6 cause the voltage ΔVi across the current sensing resistive device RS to be transferred across the first and second capacitors C1 and C2. The turned-off switching devices M7 and M8 isolate the input common mode voltage Vcmi (e.g., Vcmi=(V1+V2)/2) from the differential inputs of the operational amplifier 232. For example, the input common mode voltage Vcmi may be relatively high (e.g., 10-15V), which, if they were to be applied to the differential inputs of the operational amplifier 232, may exceed the voltage rating of the devices (e.g., FETs) of the operational amplifier 232. The turned-off switching devices M4 and M5 isolate the source of the target common mode voltage Vcmt from the first and second capacitors C1 and C2, respectively.
In accordance with a second phase of operation, the control circuit 240 deasserts (e.g., sets to a logic low) the first control signal ϕ1 and asserts (e.g., sets to a logic high) the second control signal ϕ2. The deasserted first control signal ϕ1 turns off switching devices M1, M2, M3, and M6, and the asserted second control signal ϕ2 turns on switching devices M4, M5, M7, and M8. As switching devices M7 and M8 are turned on during the second phase, the turned-off switching devices M1 and M2 isolate the differential inputs of the operational amplifier 232 from the high input common mode voltage Vcmi at the first and second terminals of the current sensing resistive device RS. The turned-on switching devices M4 and M5 apply the target common mode voltage Vcmt to the negative terminals of the first and second capacitors C1 and C2 (the turned-off switching devices M3 and M6 isolate the second and first intermediate nodes n2 and n1 from the negative terminals of the first and second capacitors C1 and C2, respectively). The turned-on switching devices M1 and M8 route the current sense voltage ΔVi with the reduced or re-referenced common mode voltage Vcmt to the differential inputs of the operational amplifier 232, where the current sense voltage ΔVi with the reduced or re-referenced common mode voltage Vcmt do not exceed the voltage rating of the devices of the operational amplifier 232.
As an example, the devices or FETs of the operational amplifier 232 may have a maximum voltage rating of 5V. The voltage ΔVi across the current sensing resistive device RS may be 100 milliVolts (mV), with an input common mode voltage Vcmi of around 15V (e.g., V1=15, V2=14.9, and Vcmi=14.95V). If the target common mode voltage Vcmt is set to 2.5V, then voltage ΔVi of 100 mV with the target common mode voltage Vcmt of 2.5V (e.g., V5=2.6V, V6=2.4V, and Vcmt=2.5V) is applied to the differential inputs of the operational amplifier 232. Thus, the reduced or re-referenced common mode voltage Vcmt (e.g., 2.5V) is within the maximum voltage rating (e.g., 5V) of the devices or FETs of the operational amplifier 232.
The vertical axis, from top to bottom, represents the state or voltage levels of the first control signal ϕ1, the second control signal ϕ2, the voltage V3 at the first intermediate node n1, the voltage V4 at the second intermediate node n2, the voltage V5 at the negative input (−) of the operational amplifier 232, the voltage V6 at the positive input (+) of the operational amplifier 232, and the output voltage ΔVo of the integrating amplifier 230.
The first phase of operation is between time t0 and t1. During the first phase, the first control signal ϕ1 is asserted, and the second control signal ϕ2 is deasserted. As a result of the first phase of operation, the voltage V3 rises to substantially V1 and the voltage V4 rises substantially to V2. Accordingly, the first and second capacitors C1 and C2 are charged to ΔVi=V1−V2 with a common mode voltage Vcmi=(V1+V2)/2. During the first phase, the voltages V5 and V6 at the differential inputs of the integrating amplifier 230 may be substantially 0V; and thus, the output voltage ΔVo of the integrating amplifier 230 may also be substantially 0V.
The second phase of operation is between time t1 and t2. During the second phase, the first control signal ϕ1 is deasserted, and the second control signal ϕ2 is asserted. As a result of the second phase of operation, the voltage V3 decreases to substantially Vcmt+ΔVi and the voltage V4 decreases to substantially Vcmt-ΔVi. Thus, the common mode voltage associated with the current sensing voltage ΔVi has been reduced or re-referenced to a level safe to provide to the operational amplifier 232. As the switching devices M7 and M8 are turned on during the second phase, the voltages V5 and V6 rise substantially to Vcmt+ΔVi and Vcmt−ΔVi, respectively. Accordingly, the differential voltage at the input of the integrating amplifier 230 is V5−V6=(Vcmt+ΔVi)−(Vcmt−ΔVi)=2ΔVi. This also results in a six (6) decibels (dB) increase in the signal-to-noise ratio (SNR) associated with sensing the load current IL, as the differential voltage 2ΔVi at the inputs of the integrating amplifier 230 is twice the differential voltage ΔVi across the current sensing resistive device RS. The integrating amplifier 230 integrates the differential voltage 2ΔVi to generate an output voltage ΔVo. Accordingly, in this configuration, the output voltage ΔVo may be related to the product of the differential or input voltage 2ΔVi to the operational amplifier 232 and the ratio of the capacitance of either the first or second capacitor C1 or C2 and the capacitance of either feedback capacitor C3+ or C3−, respectively.
The method 600 further includes transferring the first voltage including the first common mode voltage across first and second capacitors during a first phase of operation (block 620). Examples of means for transferring the first voltage including the first common mode voltage across first and second capacitors during a first phase of operation include the switching devices M1, M2, M3, and M6, and the control circuits for controlling the aforementioned switching devices.
Further, the method 600 includes re-referencing the first voltage across the first and second capacitors with a second common mode voltage during a second phase of operation (block 630). Examples of means for re-referencing the first voltage across the first and second capacitors with a second common mode voltage during a second phase of operation include the switching devices M4 and M5, the control circuits for controlling the aforementioned switching devices, and the source of the target common mode voltage Vcmt.
In particular, the wireless communication device 700 includes an integrated circuit (IC) 710, which may be implemented as a system on chip (SOC). The IC 710 includes one or more signal processing cores 730 configured to generate a transmit (Tx) baseband (BB) signal and process a received (Rx) baseband (BB) signal.
The IC 710 further includes a current management circuit 720 for controlling the operations of the one or more signal processing cores 730 based on a digital current signal DO generated by a current sensor 740. The current sensor 740, which may be implemented per any of the current sensors 200, 300, 400, and 500 previously discussed, generates the digital current signal DO based on a load current IL supplied by a battery Vbatt to a power management integrated circuit (PMIC) 750 by sensing a voltage ΔV=V1−V2 across a current sensing resistive device RS, as previously discussed.
The PMIC 750 uses the voltage V2 to generate a set of one or more regulated voltages VR1 to VRN for the one or more signal processing cores 730. The one or more signal processing cores 730 may further be coupled to the PMIC 750 via a dynamic frequency voltage scaling (DFVS) control link for setting the one or more regulated voltages VR1 to VRN based on certain operation modes of the one or more signal processing cores 730, which, as discussed, may be controlled by the current management circuit 720 based on the digital current signal DO.
The wireless communication device 700 may further include a transceiver 760 and at least one antenna 770 (e.g., an antenna array). The transceiver 760 is coupled to the one or more signal processing cores 730 to receive therefrom the Tx BB signal and provide thereto the Rx BB signal. The transceiver 760 is configured to convert the Tx BB signal into a transmit (Tx) radio frequency (RF) signal, and convert a received (Rx) RF signal into the Rx BB signal. The transceiver 760 is coupled to the at least one antenna 770 to provide thereto the Tx RF signal for electromagnetic radiation into a wireless medium for wireless transmission, and receive the Rx RF signal electromagnetically picked up from the wireless medium by the at least one antenna 770.
The following provides an overview of aspects of the present disclosure:
Aspect 1: An apparatus, comprising: a resistive device; a first capacitor selectively coupled in parallel with the resistive device; a second capacitor selectively coupled in parallel with the resistive device; and a common mode voltage source selectively coupled to respective first terminals of the first and second capacitors.
Aspect 2: The apparatus of aspect 1, further comprising a control circuit configured to: couple the resistive device in parallel with the first and second capacitors during a first phase of operation; decouple the resistive device from the first and second capacitors during a second phase of operation; and couple the common mode voltage source to the first terminals of the first and second capacitors during the second phase of operation.
Aspect 3: The apparatus of aspect 2, further comprising: a first switching device coupled between a first terminal of the resistive device and a second terminal of the first capacitor; a second switching device coupled between a second terminal of the resistive device and a second terminal of the second capacitor; a third switching device coupled between the first terminal of the first capacitor and the second terminal of the second capacitor; and a fourth switching device coupled between the first terminal of the second capacitor and the second terminal of the first capacitor; wherein the control circuit is configured to turn on the first, second, third, and fourth switching devices to couple the resistive device in parallel with the first and second capacitors during the first phase of operation.
Aspect 4: The apparatus of aspect 3, wherein the first and second capacitors are polarized capacitors, wherein the first terminals of the first and second capacitors are negative terminals of the polarized capacitors, and wherein the second terminals of the first and second capacitors are positive terminals of the polarized capacitors.
Aspect 5: The apparatus of aspect 3 or 4, wherein at least one of the first, second, third, and fourth switching devices comprises a field effect transistor (FET).
Aspect 6: The apparatus of any one of aspects 3-5, further comprising: a fifth switching device coupled between the first terminal of the first capacitor and the common mode voltage source; and a sixth switching device coupled between the first terminal of the second capacitor and the common mode voltage source; wherein the control circuit is configured to turn on the fifth and sixth switching devices to couple the common mode voltage source to the first terminals of the first and second capacitors during the second phase of operation.
Aspect 7: The apparatus of aspect 6, wherein at least one of the fifth and sixth switching devices comprises a field effect transistor (FET).
Aspect 8: The apparatus of aspect 6 or 7, further comprising: a differential amplifier including first and second differential inputs; a seventh switching device coupled between the first switching device and the first differential input of the differential amplifier; and an eighth switching device coupled between the second switching device and the second differential input of the differential amplifier; wherein the control circuit is configured to turn on the seventh and eighth switching devices to couple the second terminals of the first and second capacitors to the first and second differential inputs during the second phase of operation, respectively.
Aspect 9: The apparatus of aspect 8, wherein at least one of the seventh and eighth switching devices comprises a field effect transistor (FET).
Aspect 10: The apparatus of aspect 8 or 9, wherein the differential amplifier comprises an integrating differential amplifier.
Aspect 11: The apparatus of any one of aspects 8-10, wherein the differential amplifier comprises: an operational amplifier including the first and second differential inputs and first and second differential outputs; a third capacitor coupled between the first differential input and the first differential output; and a fourth capacitor coupled between the second differential input and the second differential output.
Aspect 12: The apparatus of any one of aspects 8-11, further comprising an analog-to-digital converter (ADC) coupled to the differential amplifier.
Aspect 13: The apparatus of aspect 11 or 12, wherein the third and fourth capacitors are in a connection relationship with the first and second capacitors such that an output voltage of the operational amplifier is related to a product of twice an input voltage of the operational amplifier and a ratio of a capacitance of the first or second capacitor to a capacitance of the third or fourth capacitor.
Aspect 14: The apparatus of any one of aspects 1-13, further comprising: a first voltage source coupled to a first terminal of the resistive device; and a second voltage source coupled to a second terminal of the resistive device.
Aspect 15: The apparatus of aspect 14, wherein the first voltage source comprises a battery charger, and the second voltage source comprises a battery.
Aspect 16: The apparatus of aspect 14, wherein the first voltage source comprises a power management integrated circuit (PMIC), and the second voltage source comprises a battery.
Aspect 17: The apparatus of any one of aspects 1-13, further comprising: a voltage source coupled to a first terminal of the resistive device; and a load coupled to a second terminal of the resistive device.
Aspect 18: The apparatus of any one of aspects 1-17, wherein the resistive device comprises a resistor.
Aspect 19: The apparatus of any one of aspects 1-18, wherein the resistive device comprises a field effect transistor (FET).
Aspect 20: A method, comprising: generating a first voltage including a first common mode voltage across a resistive device; transferring the first voltage including the first common mode voltage across first and second capacitors during a first phase of operation; and re-referencing the first voltage across the first and second capacitors with a second common mode voltage during a second phase of operation.
Aspect 21: The method of aspect 20, wherein re-referencing the first voltage across the first and second capacitors with the second common mode voltage comprises applying the second common mode voltage to terminals of the first and second capacitors, respectively.
Aspect 22: The method of aspect 21, wherein the first and second capacitors are polarized capacitors, and the terminals of the first and second capacitors are negative terminals of the polarized capacitors.
Aspect 23: The method of any one of aspects 20-22, further comprising isolating the first and second capacitors from the resistive device during the second phase of operation.
Aspect 24: The method of any one of aspects 20-23, further comprising generating a second voltage across differential inputs of a differential amplifier based on the first voltage including the second common mode voltage during the second mode of operation, wherein the second voltage is different than the first voltage.
Aspect 25: An apparatus, comprising: means for generating a first voltage including a first common mode voltage across a resistive device; means for transferring the first voltage including the first common mode voltage across first and second capacitors during a first phase of operation; and means for re-referencing the first voltage across the first and second capacitors with a second common mode voltage during a second phase of operation.
Aspect 26: The apparatus of aspect 25, wherein the means for re-referencing the first voltage across the first and second capacitors with the second common mode voltage comprises means for applying the second common mode voltage to terminals of the first and second capacitors, respectively.
Aspect 27: The apparatus of aspect 26, wherein the first and second capacitors are polarized capacitors, and the terminals of the first and second capacitors are negative terminals of the polarized capacitors.
Aspect 28: The apparatus of any one of aspects 25-27, further comprising means for isolating the first and second capacitors from the resistive device during the second phase of operation.
Aspect 29: A wireless communication device, comprising: at least one antenna; a transceiver coupled to the at least one antenna; an integrated circuit (IC) including one or more signal processing cores coupled to the transceiver; a battery coupled to the one or more signal processing cores; and a current sensor coupled to the battery, wherein the current sensor comprises: a resistive device; a first capacitor selectively coupled in parallel with the resistive device; a second capacitor selectively coupled in parallel with the resistive device; and a common mode voltage source selectively coupled to respective first terminals of the first and second capacitors.
Aspect 30: The wireless communication device of aspect 29, wherein the current sensor further comprises a control circuit configured to: couple the resistive device in parallel with the first and second capacitors during a first phase of operation; decouple the resistive device from the first and second capacitors during a second phase of operation; and couple the common mode voltage source to the first terminals of the first and second capacitors during the second phase of operation.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
