Patent Application
20080238384
1. Field of the Invention
The present invention relates to a current source circuit, and more particularly to a current source circuit and a method of outputting output currents, which is used for current-driving an apparatus such as an organic EL apparatus.
2. Description of the Related Art
An organic EL display apparatus is of a spontaneously luminous type, and has a faster response speed. Also, the organic EL display apparatus has features of a thin shape, a light weight, and a wide viewing angle. For these reasons, the organic EL display apparatus is suitable for a video display and has high quality. As shown in
In the organic EL display apparatus, horizontal scanning is repeated in accordance with a signal from a horizontal scanning control circuit to select an organic EL device or a pixel circuit on the horizontal line. During a period corresponding to the horizontal line, a suitable voltage or current is supplied to each organic EL device or each pixel circuit on the horizontal line from a drive circuit for the organic EL display apparatus via data lines. A current that flows through the organic EL device is determined based on the supplied voltage and current, so that the brightness of the organic EL device is controlled for a display. The brightness and the supplied current to the organic EL device are in a linear relation and the brightness and the applied voltage are in a non-linear relation. Also, in the organic EL apparatus in the present situation, the brightness characteristics are degraded with the elapse of time and the brightness decreases. The time change of the brightness in case of the current supply is low compared with a case of the voltage application. Therefore, it is possible to achieve a higher quality display in a current drive method to the organic EL apparatus.
In the activist matrix-type organic EL display apparatus, it is necessary to suppress a deviation of currents supplied from drive transistors to a pixel circuit of an organic EL apparatus for prevention the decrease of the display quality, even if there is a deviation in the current characteristic of the drive transistors. For example, in the voltage application method to a pixel circuit shown in
In the above-mentioned situation, as the drive circuit for driving the organic EL device or the pixel circuit, a drive circuit is proposed which has a digital-analog conversion function to output an analog current in accordance with a digital display data. As such drive circuits, there are a first type drive circuit shown in
The first type drive circuit shown in
Also, the second type drive circuit shown in
In the above second type drive circuit, the transistors for the current mirror circuit can be arranged closer, because the current mirror circuit is provided for every reference current. Therefore, a deviation of the transistors in the characteristic due to the manufacturing processes can be suppressed low and the precision of the output currents can be improved. On the other hand, in the first type drive circuit, because the mirror transistor is single and the plurality of output transistors exist, current mirror is composed by equal to or more than two plurality of transistors, a deviation of the transistors in the characteristic due to the manufacturing processes is large, compared with the second type drive circuit. Therefore, the precision of the output currents is low, compared with the second type drive circuit.
The display quality of the organic EL display apparatus depends on the current which the drive circuit supplies to an organic EL device or a pixel circuit. Therefore, it is possible to improve the display quality of the organic EL display apparatus by adopting the above second or third drive circuit. However, in the above second and third drive circuits, the current source circuit is required to supply a plurality of reference currents with a suitable current ratio to the drive circuit.
In addition to the above description, a conventional current source circuit is disclosed in Japanese Laid Open Patent Application (JP-P2000-293245A). This conventional current source circuit can generate a plurality of reference currents to the above drive circuit. As shown in
Also, Japanese Laid Open Patent Application (JP-P2000-148089A) discloses a technique similar to the Japanese Laid Open Patent Application (JP-P2000-293245A).
Also, Japanese Laid Open Patent Application (JP-P2003-066904A) discloses a technique in which a current is time-divided into N currents by transistors POUT1 to POUTN arranged redundantly to suppress a deviation of outputs from current sources.
Also, Japanese Laid Open Patent Application (JP-P2003-066906A) discloses a technique similar to the Japanese Laid Open Patent Application (JP-P2003-066904A).
In addition, a drive circuit for a current driven type display panel is disclosed in Japanese Laid Open Patent Application (JP-P2003-122307A). In this conventional example, the drive circuit is formed of a polysilicon TFT (thin film transistor) integrated circuit, and uses a current mirror circuit in which a value of a current which flows through the thin film transistor on a reference side is copied to the thin film transistor on a mirror side. The threshold of the thin film transistor on the reference side and the threshold of the thin film transistor on the mirror side are detected for every predetermined period. A change in the threshold of the thin film transistor on the reference side and the threshold of the thin film transistor on the mirror side is corrected based on the detection result. Thus, a change in the current value of the current mirror circuit is corrected.
In the above conventional example, the output currents of the current source circuit are determined based on a ratio of the current abilities between the mirror transistors Tr2 and the output transistors Tr3 to Tr5. However, even if the ratio of the current abilities is set by changing the channel widths, there is a case that the ratio of the current abilities is not a value as designed. In this case, the precision of the output currents decreases. For example, when the transistors are formed as a LTPS TFT (Low Temperature Polysilicon Thin Film Transistor) or an a-Si TFT (Amorphous Silicon TFT), the precision decreases largely, because these transistors have a large deviation of the current characteristic.
An object of the present invention is to provide a current source circuit and a method of outputting output current, in which a deviation of output currents can be suppressed.
An object of the present invention is to provide a current source circuit and a method of outputting output current, in which a current copier or a mirror circuit is adopted for a current source.
An object of the present invention is to provide a current source circuit and a method of outputting output current, in which transistors of a current mirror are sued in a current source.
Another object of the present invention is to provide a current source circuit and a method of outputting output current, in which desired output currents can be obtained by a simple adjustment.
In an aspect of the present invention, a current source circuit includes a voltage output section which outputs a voltage signal; a current source section and a conversion section. The current source section has at least one current source block comprising a plurality of current sources, each of which outputs an output current. The conversion section is provided between the voltage output section and the current source section and outputs a reference current to the plurality of current sources of the at least one current source block based on the voltage signal such that the output current from each of the plurality of current sources is set based on the reference current.
Here, the setting of the output current may be carried out in time series over the plurality of current sources.
Also, the current source section may include two of the current source blocks as first and second current source blocks. The first current source block alternately carries out a current setting operation to set a value of the output current and a current outputting operation to output the output currents. The second current source block carries out the current setting operation when the first current source block carries out the current outputting operation and the current outputting operation when the first current source block carries out the current setting operation.
Also, the voltage output section may include a plurality of resistances connected in series between a first voltage and a second voltage; and a switch set connected with the plurality of resistances to output as the voltage signal, one of voltages which are generated by the plurality of resistances and the first and second voltages. In this case, a value of the output current may be adjusted based on the first voltage. Also, the voltage output section may further include a switch circuit which determines the voltage signal based on a display data. In this case, the current source circuit drives an organic EL display apparatus, and the display data is for display on the organic EL display apparatus.
Also, each of the plurality of current sources may include a transistor. The conversion section may include a current setting resistance and an amplifier which outputs the reference current based on the voltage signal, the current setting resistance and the transistor in the each current source. In this case, the conversion section may further include an offset canceling section which cancels an offset of the amplifier. Also, the voltage output section may include a plurality of resistances connected in series between a first voltage and a second voltage; and a switch set connected with the plurality of resistances to output as the voltage signal, one of voltages which are generated by the plurality of resistances and the first and second voltages. The amplifier is an operation amplifier which has an inversion input connected with the voltage signal from the voltage output section and an non-inversion input connected with one end of the current setting resistance, the other end of the current setting resistance being connected with a third voltage. The operation amplifier outputs the reference current.
In this case, the second voltage may be same as the third voltage, or the second voltage may be different from the third voltage.
Also, each of the plurality of current sources may include first and second transistors connected in series, wherein a source of the first transistor is connected with a fourth voltage, a gate of the first transistor is connected with a drain of the first transistor via a first switch, and a gate of the second transistor is connected with the reference current via a second switch; a first holding capacitance which is connected between the fourth voltage and the gate of the first transistor; and a second holding capacitance which is connected between the fourth voltage and the gate of the second transistor. A drain of the transistor may be connected with a conversion common node via a third switch, and the output current may be outputted from the drain of the second transistor.
Also, each of the plurality of current sources may include a transistor which has a source connected with a fourth voltage; a holding capacitance connected between the fourth voltage and a gate of the transistor which is connected with the reference current via a first switch. A drain of the transistor is connected with a conversion common node via a second switch, and the output current is outputted from the drain of the transistor. In this case, the conversion section may include a current setting resistance; and an operation amplifier which has an inversion input connected with the voltage signal from the voltage output section and a non-inversion input connected with one end of the current setting resistance as the conversion common node, the operation amplifier outputting the reference current. Also, the current source circuit may include a plurality of current driver ICs, each of which contains the voltage output section, the current source section and the conversion section other than the current setting resistance. The current setting resistance is common to the plurality of current driver ICs. Also, the current source circuit comprises a plurality of current driver ICs, each of which contains the current source section and the conversion section other than the current setting resistance. The voltage output section and the current setting resistance may be common to the plurality of current driver ICs, and may be respectively connected via two switches with each of the plurality of current driver ICs. Also, the current source circuit may be a plurality of current driver ICs, each of which contains the current source section. A set of the voltage output section and the conversion section other than the current setting resistance and the current setting resistance may be common to the plurality of current driver ICs, and may be respectively connected via two switches with each of the plurality of current driver ICs.
Also, each of the plurality of current sources may include first and second transistor, each of which has a source connected with a fourth voltage and which constitute a current mirror; and a holding capacitance connected between the fourth voltage and gates of the first and second transistor, the holding capacitance is connected with the reference current via a first switch. A drain of the first transistor may be connected with a conversion common node via a second switch, and the output current may be outputted from the drain of the second transistor. In this case, the conversion section may include a current setting resistance; and an operation amplifier which has an inversion input connected with the voltage signal from the voltage output section and a non-inversion input connected with one end of the current setting resistance, the operation amplifier outputting the reference current. In this case, the current source circuit may be a plurality of current driver ICs, each of which contains the voltage output section, the current source section and the conversion section other than the current setting resistance. The current setting resistance may be common to the plurality of current driver ICs.
Also, the current source circuit may include a plurality of current driver ICs, each of which contains the current source section and the conversion section other than the current setting resistance. The voltage output section and the current setting resistance may be common to the plurality of current driver ICs, and may be respectively connected via two switches with each of the plurality of current driver ICs. Also, the current source circuit may be a plurality of current driver ICs, each of which contains the current source section. A set of the voltage output section and the conversion section other than the current setting resistance and the current setting resistance may be common to the plurality of current driver ICs, and may be respectively connected via two switches with each of the plurality of current driver ICs.
Also, each of the plurality of current sources may include a transistor which has a source connected with a fourth voltage; and a holding capacitance which is connected between the fourth voltage and a gate of the transistor and which is connected with a drain of the transistor via a first switch. The drain of the transistor may be connected with the reference current via a second switch, and the output current may be outputted from the drain of the transistor. In this case, the current source circuit may include a plurality of current driver ICs, each of which contains the current source section. The reference current may be common to the plurality of current driver ICs and may be connected with each of the plurality of current driver ICs via a third switch.
Also, each of the plurality of current sources may include first and second transistor, each of which has a source connected with a fourth voltage and which constitute a current mirror; and a holding capacitance which is connected between the fourth voltage and gates of the first and second transistor, and which is connected with a drain of the first transistor via a first switch. The drain of the first transistor may be connected with the reference current via a second switch, and the output current may be outputted from the drain of the second transistor. The current source section may further include an input current copier which is provided in common to the plurality of current sources and which may include a third transistor having a drain connected with the reference current, a source connected with a fifth voltage, and a gate connected with the reference current via a third switch; and a second holding capacitance connected between the source and gate of the third transistor. In this case, the current source circuit may include a plurality of current driver ICs, each of which contains the current source section, and the reference current may be common to the plurality of current driver ICs and may be connected with each of the plurality of current driver ICs via a third switch.
In another aspect of the present invention, a method of outputting output currents, is achieved by outputting a voltage signal from a voltage output section; by outputting a reference current to a current source section from a conversion section based on the voltage signal and a voltage drop across a current setting resistance in the conversion section; by carrying out a current setting operation of setting a value of an output current to each of a plurality of current sources in the current source section based on the reference current, wherein the current source section has at least one current source block comprising the plurality of current sources; and by carrying out a current outputting operation of outputting the output current of the set value from each of the plurality of current sources.
Here, the carrying out a current setting operation may be achieved by sequentially carrying out the current setting operation to the plurality of current sources during a period. The carrying out a current outputting operation may be achieved by sequentially carrying out the current outputting operation to the plurality of current sources during a period next to the period.
Also, the current source section may include two of the current source blocks as first and second current source blocks. The carrying out a current setting operation may be achieved by sequentially carrying out the current setting operation to the first and second current source blocks. The carrying out an current outputting operation may be achieved by carrying out the current outputting operation to the second current source block when the current setting operation is carried out to the first current source block; and carrying out the current outputting operation to the first current source block when the current setting operation is carried out to the second current source block.
Also, the outputting a voltage signal may be achieved by outputting as the voltage signal, one of voltages which are generated by a plurality of resistances connected in series between first and second voltages. The method may further include adjusting the first voltage to adjust a value of the output current. Also, the outputting one of voltages may include outputting as the voltage signal, one of the voltages based on a display data.
Also, the one end of the current setting resistance may be connected with a third voltage. The method further may be achieved by adjusting the second voltage and the third voltage independently.
Also, the conversion section includes an amplifier having an offset. The outputting a reference current may be achieved by canceling the offset of the amplifier.
Also, each of the plurality of current sources may include a transistor which has a source connected with a fourth voltage; a holding capacitance connected between the fourth voltage and a gate of the transistor which is connected with the reference current via a first switch.
A drain of the transistor is connected with the current setting resistance via a second switch. The output current may be outputted from the drain of the transistor via a third switch. The sequentially carrying out the current outputting operation may be achieved by turning on the first and second switches in order in the plurality of current sources; and by turning off the third switch in order in the plurality of current sources. The sequentially carrying out the current outputting operation may be achieved by turning off the first and second switches in all of the plurality of current sources; and by turning on the third switch in all of the plurality of current sources.
Also, each of the plurality of current sources may include first and second transistor, each of which has a source connected with a fourth voltage and which constitute a current mirror; a holding capacitance connected between the fourth voltage and gates of the first and second transistor, the holding capacitance is connected with the reference current via a first switch. A drain of the first transistor may be connected with the current setting resistance via a second switch, and the output current may be outputted from the drain of the second transistor. The sequentially carrying out the current outputting operation may be achieved by turning on the first and second switches in order in the plurality of current sources. The sequentially carrying out the current outputting operation may be achieved by turning on the first and second switches in all of the plurality of current sources. The sequentially carrying out the current outputting operation and the sequentially carrying out the current outputting operation are carried out at a same time.
Also, each of the plurality of current sources may be achieved by first and second transistors connected in series, wherein a source of the first transistor is connected with a fourth voltage, a gate of the first transistor is connected with a drain of the first transistor via a first switch, and a gate of the second transistor is connected with the reference current via a second switch; a first holding capacitance which is connected between the fourth voltage and the gate of the first transistor; and a second holding capacitance which is connected between the fourth voltage and the gate of the second transistor. A drain of the transistor may be connected with the current setting resistance via a third switch. The output current may be outputted from the drain of the second transistor via a fourth switch. The sequentially carrying out the current outputting operation may be achieved by turning on the first to third switches in order in the plurality of current sources; and by turning off the fourth switch in order in the plurality of current sources. The sequentially carrying out the current outputting operation may be achieved by turning off the first to third switches in all of the plurality of current sources; and by turning on the fourth switch in all of the plurality of current sources.
a to 37I are timing charts showing the operation of the reference current source circuit in the thirteenth embodiment;
a to 39J are timing charts showing the operation of the reference current source circuit in the fourteenth embodiment; and
Hereinafter, a reference current source circuit of semiconductor devices, and an organic EL display apparatus using the same of the present invention will be described in detail with reference to the attached drawings. In this embodiment, the current source circuit outputs six kinds of currents having a current ratio of 1:2:4:8:16:32, as shown in
As shown in
The resistance string section 2 is composed of 32 resistances R1, R2, . . . , R32, and six switches SW0, SW1, SW2, . . . SW5. The switches are supplied with control signals which are given the same names as the switches. The 32 resistances have a same resistance value and are connected in series. Voltages VCin (VCS) and VSin are applied across both ends of the resistance string. Each of the six switches is connected at one end with a common node NRCOM as an output of the resistance string section 2 to output a voltage Vin. The other end of each of the six switches is connected with one of a node between the resistances R1 and R2 (VC0), a node between the resistances R2 and R3 (VC1), a node between the resistances R4 and R5 (VC2), a node between the resistances R8 and R9 (VC3), a node between the resistances R16 and R17 (VC4), and a node to which the voltage Vcin (=VC5) is applied. Here, it should be noted that signal lines for the above control signals are not shown in
The V-I conversion section 4 is composed of a current setting resistance Rc and an operation amplifier OP. One end of the current setting resistance Rc is connected with the voltage Vsin. The other end of the current setting resistance Rc is connected with a common node NCCOM. The voltage Vin outputted from the resistance string section 2 is connected with the inversion input of the operation amplifier OP. The non-inversion input of the operation amplifier OP is connected with the common node NCCOM. The output of the operation amplifier OP is connected with an input of the current source section 6.
The current source section 6 is composed of an odd frame current source block 6-1 and an even frame current source block 6-2. The odd frame current source block 6-1 is composed of six current copier current sources 0O to 5O, and the even frame current source block 6-2 is composed of six current copier current sources 0E to 5E. Each of the six current copier current sources 0E to 5E in the even frame current source block 6-2 is composed of a P-type transistor PTEi (i is an integer and 0≦i≦5), a S capacitance CEi, three switches SEi_M1, SE and SEi_M2. The source of the P-type transistor PTEi is connected with a power supply voltage VDDI, and the capacitance CEi is connected between the power supply voltage VDDI and the gate of the P-type transistor PTEi. The switch SEi_MI is provided between the gate of the P-type transistor PTEi and the output of the V-I conversion section 4 and is controlled in response to a control signal SEi_M1. The switch SEi_M2 is provided between the drain of the P-type transistor PTEi and the common node NCCOM, i.e., the non-inversion input of the operation amplifier OP of the V-I conversion section 4 and is controlled by a control signal SEi_M2. The switch SE is provided between the drain of the P-type transistor PTEi and an output Ioi of the current source circuit and is controlled by a control signal SE.
Also, each of the six current copier current sources 0O to 5O in the odd frame current source block 6-1 is composed of a P-type transistor PTOi (i is an integer and 0≦i≦5), a capacitance COi, three switches SOi_M1, SO and SOi_M2. The source of the P-type transistor PTOi is connected with the power supply voltage VDDI, and the capacitance COi is connected between the power supply voltage VDDI and the gate of the P-type transistor PTOi. The switch SOi_M1 is provided between the gate of the P-type transistor PTOi and the output of the V-I conversion section 4 and is controlled in response to a control signal SOi_M1. The switch SOi_M2 is provided between the drain of the P-type transistor PTOi and the common node NCCOM, i.e., the non-inversion input of the operation amplifier OP of the V-I conversion section 4 and is controlled by a control signal SOi_M2. The switch SO is provided between the drain of the P-type transistor PTOi and an output Ioi of the current source circuit and is controlled by a control signal SO.
Next, an operation of the current source section will be described below. Each of the odd frame and even frame current source blocks 6-1 and 6-2 of the present invention has two operation states: one is a current setting operation and the other is a current outputting operation. The even frame current source block 6-2 of the current source section 6 carries out the current setting operation in an odd frame period and the current outputting operation in an even frame period. On the other hand, the odd frame current source block 6-1 carries out the current outputting operation in the odd frame period and the current setting operation in the even frame period.
The even frame current source block 6-2 carries out the current setting operation in the odd frame period. In this period, in each of the current copier current sources iE of the even frame current source block 6-2, the switches SO are turned on as shown in
Also, in the odd frame period, the switch SW5 in the resistance string section 2, and the switches SE5_M1 and SE5_M2 in the current copier current source 5E of the even frame current source block 6-2 are turned on in response to the control signals SW5, SE5_M1 and SE5_M2, as shown in
In the operating state, the voltage VC5 (=VCin) is applied to the inversion input of the operation amplifier OP in the V-I conversion section 4, and the non-inversion input of the operation amplifier OP is connected with the current setting resistance Rc. At this time, the operation amplifier OP, the P-type transistor PTE5 in the current copier current source 5E and the current setting resistance Rc constitute a new operation amplifier. In other words, a voltage follower is formed in which the non-inversion input of the original operation amplifier OP functions as the inversion input, the inversion input of the original operation amplifier OP functions as the non-inversion input, the P-type transistor PTE5 of the current copier current source 5E and the current setting resistance Rc become an output stage. Therefore, the output voltage of the new voltage follower is VC5, and current I5 (=(VC5−VSin)/Rc) flows through the P-type transistor in the current copier current source SE and the current setting resistance Rc. At this time, a voltage is applied to the gate of the P-type transistor PTE5 in the current copier current source SE such that the current I5 flows between the drain and the source of the P-type transistor PTE5 (see
Next, the control signal SW5 is set to the low level and the control signals SW4, SE4_M1 and SE4_M2 are set to the high level, as shown in
Next, the switches SE4_M1 and SE4_M2 are turned off in response to the control signals SE4_M1 and SE4_M2. At this time, the gate voltage of the P-type transistor PTE4 of the current copier current source 4E is held to a voltage by the holding capacitance CE4 such that the current I4 flows between the drain and the source of the P-type transistor PTE4.
In the odd frame period, the current copier current sources 3E, 2E, 1E and 0E in the even frame current source block 6-2 carry out the same operation as described above. Thus, the voltages held by the holding capacitances CE3, CE2, CE1, and CE0 are applied to the gates of the P-type transistors PTE3, PTE2, PTE1 and PTE0 in the current copier current sources 3E, 2E, 1E and 0E in the even frame current source block 6-2 such that the currents I3 (=(VC2−VSin)/Rc), I2 (=(VC2−VSin)/Rc), II (=(VC1−VSin)/Rc), I0 (=(VC0−VSin)/Rc) flow through the respective P-type transistors.
Through the above-mentioned process, the current setting operation ends.
Here, an attention should be paid to the timing of the switch control. In this embodiment, it is necessary that the control signals SWi, SEi_M1 and SEi_M2 (i is an integer and 0≦i≦5) are generated such that the switches SEi_M2 and SWi are turned off at a same time as the switch SEi_M1 or at a time later than the switch SEi_M1. This is applied to the even frame current source block 6-2 in the same way. The first reason is to set the voltage of the holding capacitance to the voltage of the state in which the current is flowing. The second reason is to restrain the noise generated in response to an operation of another switch as less as possible, i.e., to remove the influence of the noise. The timing charts of this embodiment shown in
In the next even frame period, the output Io0 to Io5 of the whole current source circuit are respectively connected with the drains of the P-type transistors PTE5 to PTE0 of the current copier current sources 5E to 0E in the even frame current source block 6-2 by the switches SE of the current copier current sources 5E to 0E in the even frame current source block 6-2 in accordance with the control signals SE, and the reference current outputting operation is carried out, such that the current I0 to I5 are outputted.
On the other hand, in the even frame period, the current setting operation is carried out in the odd frame current source block 6-1 in the same way as the even frame current source block 6-2.
The above-mentioned operation is repeats for each frame, and the current source circuit can always output the current I0 to I5.
In this embodiment of the present invention, the transistor which sets the current and the transistor which outputs the current are same in the current copier circuit. In other words, in the current setting operation, by forming a short-circuit between the gate and drain of the P-type transistor in the current copier current source, and by applying through the P-type transistor the currents I5 to I0 based on the current setting resistance and the inversion input voltage of the operation amplifier OP of the V-I conversion section 4, the gate voltage of the P-type transistor PTEi or PTOi in the current copier current source iE or iO can be set to the voltage by which the current between the drain and the source in the saturated operation region of the transistor is set to either of the currents I5 to I0. On the other hand, in the current outputting operation, the P-type transistor PTEi or PTOi in the current copier current source iE or iO outputs the currents I5 to I0 in accordance with the set gate voltage. In this way, the gate voltage of the P-type transistor in the current copier current source is held in the state in which either of the current I5 to I0 flows actually between the drain and the source, and the either of the currents I5 to I0 is outputted from the same transistor. Thus, it is possible to output the currents I5 to I0 regardless of a deviation of the current characteristics between the P-type transistors Also, in the current copier current source, it is necessary that the period during which the current is set is provided separately from the period during which the current is outputted. Therefore, the current can not be always outputted. In order to solve the problem, the two current source blocks for the even frame and the odd frame are provided in the present invention. During the period during which the current is set in one of the two current source blocks, the other outputs the current. Thus, the current can be always outputted.
Also, in the present invention, the current value set to the current copier current source is determined based on the voltage which has a voltage ratio to the voltage Vcin and which is determined based on a resistance ratio in the resistance string section 2 and the resistance value of the current setting resistance Rc common to all the current copier current sources. The set current value does not depend on the resistances. Thus, the current ratio with higher precision can be realized.
Moreover, the current value can be simply adjusted while keeping the current ratio, by adjusting the voltage VCin applied to the resistance string.
Therefore, it is possible to simply adjust the output current value to a design value by adjusting the voltage Vcin, even if the value of the current setting resistance Rc is different from a design value.
The circuit structure of the current source circuit according to the second embodiment will be described with reference to
The offset cancellation block has a capacitance and switches. The resistance string section 2 and the current source section 6 in the second embodiment are the same as those of the first embodiment.
As shown in
The operation of the current source circuit 6 in the second embodiment will be described with reference to the timing charts of
It is in the odd frame period that the current setting operation is carried out by the even frame current source bloc 6-2. In the odd frame period, the control signal SE is set to the low level so that the switch SE in each of the current copier current sources 5E to 0E is turned off, resulting in the even frame current source block 6-2 being disconnected from the outputs Io5 to Io0.
Subsequently, in the odd frame period, the switch SW5 in the resistance string section 2, the switches OC1 and OC2 in the V-I conversion section 2A, and the switches SE5_M1 and SE5_M2 in the current copier current source 5E of the even frame current source block 6-2 are turned on in response to the control signals SW5, OC1, OC2, OC1B, SE5_M1 and SE5_M2, as shown in
In the offset voltage setting state, a voltage VC5 is applied to the inversion input of the operation amplifier OP in the V-I conversion section 4A from the resistances of the resistance string section 2. Also, an new operation amplifier is formed by the operation amplifier OP of the V-I conversion section 4A, the current setting resistance Rc, the current copier current source 5E in the even frame current source block 6-2 to have the inversion input of the operation amplifier OP in the V-I conversion section 4A as a non-inversion input, the non-inversion input thereof as an inversion input and a node between the current setting resistance Rc and the switch SE5_M2 as an output. The new operation amplifier is connected with a voltage follower. Therefore, supposing that a offset voltage of the new amplifier is Voff′, a voltage VC5+Voff′ is applied to one end of the S capacitance Coc on the side of the non-inversion input of the operation amplifier OP and the voltage VC5 is applied to the other end because of an imaginary short-circuit, as shown in
Subsequently, the switches OC1 and OC2 are turned off, the switch OC1B is turned on in the V-I conversion section 4A in response to the control signals OC1, OC2 and OC1B, respectively. The other switches maintain the previous states. This operation state is referred to as an offset voltage canceling state. A circuit diagram at that time is shown in
In the offset voltage canceling state, the voltage VC5+Voff′ is applied to the non-inversion input of the operation amplifier OP in the V-I conversion section 4A in the new amplifier. In this case, the voltages VC5+Voff′ and VC5 were applied across the capacitance Coc in the offset voltage setting state. Therefore, the output of the new operation amplifier is the voltage VC5 in the operating state from the principle of conservation of charge. Thus, in the offset voltage canceling state, the voltage VC5 is applied to the current setting resistance Rc even when the operation amplifier OP of the V-I conversion section 4A has the offset voltage. In this way, the current I5=(VC5−VSin)/Rc flows through the P-type transistor PTE5 of the current copier current source SE in the even frame current source block 6-2.
Next, the switches SE5_M1 and SE5_M2 are turned off in response to the control signals SE5_M1 and SE5_M2. At that time, the gate voltage of the P-type transistor PTE5 of the current copier current source 5E is held to the voltage by the capacitance CE5 in such a manner that the current I5 can flow through the P-type transistor PTE5. The current setting operation of the current copier current source 5E in the even frame current source block 6-2 ends through the above processes.
Subsequently, the current setting operation is carried out in order in the current copier current sources 4E to 0E of the even frame current source block 6-2 in the odd frame period, as shown in
In the next even frame period, the drains of the P-type transistors PTE4, PTE3, PTE2, PTE1 and PTE0 are connected with the outputs Io5 to Io0 of the current source circuit by the switches SE of the current copier current sources 5E to 0E in the even frame current source block 6-2 in response to the control signals SE. The current outputting operation of the current Io5 to Io0, i.e., a reference current outputting operation is carried out.
On the other hand, in the even frame period, the odd frame current source block 6-1 carries out the same current setting operation in the odd frame period as the even frame current source block 6-2. The above operations are repeated in every two frames and the current source circuit can always output the current of I5 to I0. Also, an attention as in the first embodiment is to be paid to for the control timing of the switches SWi, SEi_M1 and SEi_M2, SOi_M1 and SOi_M2 (0≦i≦5, i is an integer).
The second embodiment has an advantage that the offset voltage can be cancelled when the offset voltage exists in the operation amplifier OP of the V-I conversion section 4A, in addition to the advantage of the first embodiment. By adopting the structure, in the second embodiment, the reference currents can be outputted while which a current ratio is kept in a high precision.
The current source circuit according to the third embodiment can cancel an offset voltage of the operation amplifier OP even when the offset voltage of the operation amplifier OP in the V-I conversion section 4A of the second embodiment is large. The circuit structure in the third embodiment is shown in
The third embodiment basically has the same circuit structure and operation as those of the second embodiment. However, the switch OC1B is replaced by a switch/OC1. Also, one end of the current setting resistance Rc on the opposite side of the node NCCOM is connected with the voltage Vsin via a switch/OC1 and a voltage VL via a switch OC1. The switches OC1 are turned on in response to the control signal OC1 and the switches/OC1 are turned on in response to the control signal /OC1 which is an inverted signal of the control signal OC1.
In the third embodiment, the voltage VSin is not always applied to the current setting resistance Rc. A voltage VL is applied to the current setting resistance Rc in the offset voltage setting state of the current setting operation, and the voltage VSin is applied in the offset canceling state after that. The voltage VL is lower than the offset voltage of the operation amplifier OP in the V-I conversion section 4B.
In the third embodiment, the voltage VL is applied to one end of the current setting resistance Rc in the offset voltage setting state. Therefore, a voltage VC0+Voff can be applied to the non-inversion input of the operation amplifier OP in the V-I conversion section 4B to cancel the offset. For example, in the third embodiment, when the current setting operation is carried out in the current copier current source 0E of the even frame current source block 6-2, the voltage VSin is not applied to the one end of the current setting resistance Rc, even if the offset voltage Voff of the operation amplifier OP in the V-I conversion section 4B is negative and the voltage VC0+Voff is smaller than Vsin. Thus, the voltage VC0+Voff can be applied to the non-inversion input of the operation amplifier OP in the V-I conversion section 4B in the offset voltage setting state. Thus, the offset cancellation can be carried out.
In the fourth embodiment, the function to cancel the offset voltage of the operation amplifier OP in the V-I conversion section 4B according to the third embodiment can be made faster.
As described above, the resistance string section 2 and the current source section 6 in the fourth embodiment are the same as those of each of the first to third embodiment.
Next, an operation of the current source circuit according to the fourth embodiment will be described. The timing charts showing the operation of the current source circuit according to the fourth embodiment is the same as those of the second embodiment shown in
It is in the odd frame period that the current setting operation is carried out by the even frame current source block 6-2. The output currents Io5 to Io0 are disconnected from the switches SE in the current copier current sources 5E to 0E of the even frame current source block 6-2 in response to the control signal SE in the odd frame period.
In the odd frame period, the switch SW5 in the resistance string section 2, the current copier current source the switches OC1 and OC2 in the V-I conversion section 4C, and the switches SE5_M1 in 5E and SE5_M2 in the even frame current source block 6-2 are turned on in response to the control signals SW5, OC1, OC2, OC1B, SE5_M1 and SE5_M2. The switches OC1B(1) and OC1B(2) in the V-I conversion section 4C are turned off to set the offset voltage setting state.
As shown
Subsequently, the switches OC1 and OC2 in the V-I conversion section 4C are turn off and the switches OC1B(1) and OC1B(2) are turned on in response to the control signals OC1, OC2, and OC1B as the offset voltage canceling state. The other switches keep the previous states.
In this state, like the first to third embodiments, a new V-I conversion section is constituted by the operation amplifier OP in the V-I conversion section 4C, the P-type transistor in each current copier current source in the even frame current source block 6-2 and the current setting resistance Rc. However, as shown
Subsequently, the current setting operation is carried out from the current copier current sources 4E to 0E in the even frame current source block 6-2 in according with the timing charts of
Here, like the first embodiment, an attention should be paid to the timing of the switch control. In the fourth embodiment, it is needed that the switches SWi and SEi_M2 are turned off at the same time as or layer than the switch SEi_M1. This is true in the even frame period, too. The timing charts shown in
In the next even frame period, the drains of the P-type transistors PTE5 to PTE0 of SE in the current copier current sources 5E to 0E of the even frame current source block 6-2 are connected with the outputs Io5 to Io0 of the current source circuit by the switches SE of the current copier current sources 5E to 0E in response to the control signal SE. Thus, the current I5 to I0 are outputted. On the other hand, in the even frame period, the odd frame current source block 6-1 carries out t period, the current setting operation like the operation carried out by the even frame current source block 6-2 in the odd frame period. The above-mentioned operations are repeats a set of the odd and even frames and the current source circuit can always output the current I5 to I0.
The fourth embodiment has an advantage that the current with a higher current ratio precision can be outputted without undergoing influence by the offset voltage of the operation amplifier OP in the V-I conversion section 4C. In addition, the fourth embodiment has an advantage that the offset voltage setting operation can be reduced, by carrying out the offset voltage setting operation by only the operation amplifier OP. On the other hand, in the third embodiment, the offset voltage setting operation is carried out by a circuit of the operation amplifier, the current copier current source and the current setting resistance.
In the current source circuit in the fifth embodiment is adopted the current copier current source with a higher current ratio precision regardless of the characteristics of the power supply voltage and the current load, compared with the first embodiment. The current source circuit in the fifth embodiment is shown in
The output currents are examined through circuit simulation about the cascode-type current copier current source in the fifth embodiment and the current copier current source of the first embodiment. That is, a circuit simulation is carried out to examine the change of the output current due to the change of the current load voltage when the current is outputted after an input current is set to 1 μA.
Also, if the idea of the fifth embodiment is applied to any of the second to fourth embodiments, it is possible to output current in a further higher precision.
The circuit structure of such a cascode-type current copier can be applied to a more general current source, e.g., a pixel circuit of the organic EL display apparatus, in addition to the reference current source circuit.
The pixel circuit using the current copier is shown in
The pixel circuit of
In the second operation state, when the switches SW1-1 to SW1-3 are turned off in response to the control signal 1, and the switch SW2-l turned on in response to the control signal 2, the gate voltage of the drive transistor which is set in the first operation state is held by a capacitance. Thus, a current with the same value as the current flowing in the first operation state is supplied to the organic EL device from the drive transistor.
Through such an operation, the circuit can supply to the organic EL device in a high precision, the current with the same value as the current which flows in the first operation state, regardless of the current characteristic of the drive transistor.
In the pixel circuit using the cascode-type current copier of
In the current source circuit in the sixth embodiment, current mirror 25 current sources 5M to 0M are adopted instead of the current copier current sources in the first embodiment, as shown in
In the sixth embodiment, since the current mirror current sources 5M to 0M are used, it is not necessary to use the two current source blocks, i.e., the odd frame current source block 6-1 and the even frame current source block 6-2. Therefore, a single current source block 6-0 is only required so that the circuit scale can be made smaller than the first embodiment, and the operation can be simplified than the first embodiment.
In the sixth embodiment, six current mirror current sources 5M to 0M are provided. In each current mirror current source, a P-type transistor i and a P-type transistor PTi′ constitute a current mirror. A capacitance Ci is connected between the voltage VDDI and the gates of the transistors PTi and PTi′. A switch Si_M1 is connected between the gates of the transistors PTi and PTi′ and the output of the operation amplifier OP. A switch Si_M2 is connected between the drain of the transistor PTi and the node NCCOM swhich is connected with one end of the current setting resistance Rc. The drain of the transistor PTi′ is connected with the output Ioi. The switches SW5 to SW0, Si_M1 and Si_M2 are controlled as shown in
In the sixth embodiment, like the first embodiment, a current is set to the current mirror current source based on the voltage ratio which is determined based on the resistance ratio in the resistance string section 2 and the resistance value of the current setting resistance Rc common to all the current mirror current sources 5M to 0M. Therefore, it is possible to determine the current ratio in a high precision without depending on the absolute value of each resistance. Also, it is possible to simply adjust the current value while keeping the current ratio, by adjusting the voltage VCin applied to the resistance string. Therefore, even if the resistance value of the current setting resistance Rc is different from a design value, it is possible to simply adjust the current so as to output the current with a designed value by adjusting the voltage VCin
In the current source circuit of the first embodiment, the same voltage VSin is applied to the one end of the resistance string section 2 and the one end of the current setting resistance Rc. However, in the seventh embodiment, different voltages VSin1 and Vsin2 are applied to the one end of the resistance string section 2, and the one end of the current setting resistance Rc. The other structure and the operation are coincident with those of the first embodiment. In the seventh embodiment, by separating the voltage VSin into a voltage VSin1 and a voltage VSin2 and adjusting the value of the voltage VSin2, it is possible to accurately equalize the applied voltage applied to the one end of the resistance string section 2 and the voltage applied to the one end of the current setting resistance Rc. Therefore, the current source circuit can be simply arranged.
Moreover, in the seventh embodiment, when the operation amplifier OP of the V-I conversion section 4 has an offset voltage, it is possible to absorb the error due to the offset voltage by changing the voltage VSin2.
Oppositely, it is possible to add a offset component to the current output, by changing the voltage VSin2 in such a manner that the voltage applied to the one end of the resistance string section 2 and the voltage applied to the one end of the current setting resistance Rc are made different in the current setting state.
The dummy transistor SEi_M1B is connected between the capacitance CEi and the switch transistor SEi_M1 for disconnecting the capacitance from another wiring line in the current copier current source. The inversion signal SEi_M1B of the control signal SEi_M1 is applied to the gate of the transistor SEi_M1B and the source and the drain are short-circuited. Moreover, a product of the width W and the length L in the dummy transistor is ½ of a product of the width W and the length L in the switch transistor Sei_M1. Thus, when the switch transistor Sei_M1 is switched from an ON state to an OFF state, switching noise due to charge transferring from the transistor Sei_M1 to the capacitance CEi can be eliminated by the dummy transistor. Therefore, the eighth embodiment can output current in higher precision than in the first embodiment.
The idea of the eighth embodiment can be applied not only to the first embodiment, but also any of the second to sixth embodiments in the same way and the same effect can be achieved.
Also, in the eighth embodiment, the N-type transistor is used as the switch but a P-type transistor may be used. In this case, the control signal should be inverted.
In addition to the above description, it is not always necessary that the voltage applied to the source of the P-type transistor PTEi or PTi is equal to the voltage applied to one end of the capacitance CEi or Ci in the current 5 copier current source or current mirror current source of the current source circuit according to the first to eighth embodiments.
It is sufficient to provide a single reference current source circuit if a display section is driven by a single current driver or the display section and the current driver are mounted on a same glass substrate as in LTPS.
Therefore, the reference current source circuit according to any of the first to eighth embodiments can output reference currents with suitable values by adjusting the voltage VCin, even when all the components of the current source circuit are formed in the current driver IC and formed on the glass substrate.
On the other hand, as shown in
Here, as the reference current source circuit in the ninth embodiment, the current source circuit according to either of the first to eighth embodiments from the first embodiment can be used. It should be noted that in the current source circuit of the seventh embodiment, the three voltages applied to each IC such as VCin, VSin1, and VSin2 are necessary.
In the tenth embodiment, unlike ninth embodiment, the current setting resistance Rc in the reference current source circuit is provided outside the driver IC, as shown in
In the tenth embodiment, the current setting resistance Rc can be set in a higher precision, since the current setting resistance Rc is provided outside the driver IC. In this case, it is not necessary to provide the voltage independently for every driver IC. Unlike the current setting resistance, the resistance string section of resistances can be formed into the current driver IC by making each resistance large to an extent that a wiring line resistance can be ignored, because only the resistance ratio is a problem.
As shown in
In the current setting operation in the eleventh embodiment, the current setting operation is carried out to each current source of the current source section in the current driver IC IC_1, and then the current setting operation is carried out to each current source of the current source section in the current driver IC IC_2. Thus, the current setting operation is carried out to each current source of the current source section in all the current driver ICs IC_n during a predetermined period, e.g., during one frame in order. The current setting operation is the same as the operations of the first to eighth embodiments. Therefore, it is possible to set current values to the plurality of current driver ICs without decreasing the precision of the output current.
In the eleventh embodiment, the circuit scale can be made small, compared with the ninth and tenth embodiments, because the resistance string section and the current setting resistance can be made common. Moreover, as shown in
In the twelfth embodiment, the currents are directly supplied to the current source section. Therefore, the current source section according to any of the first to eighth embodiments must be changed. The change to the current source section is shown in
In the current source section shown in
In the current setting operation of the twelfth embodiment, during a predetermined period of one frame, all the switches Si_1 are turned on and all the switches Si_2 to Si_5 are turned off. The current setting operation is carried out at the same time to the six current copier current sources 5E to 0E of the even frame current source block 6-2D in the current driver IC IC_1. Then, during a next predetermined period of one frame, all the switches Si_2 are turned on and all the switches Si_1 and Si_3 to Si_5 are turned off. The current setting operation is carried out at the same time to the six current copier current sources 5E to 0E of the even frame current source block 6-2D in the current driver IC IC_2. This current setting operation is repeated to the current driver IC IC_n. In this frame, the odd frame current source block 6-1 is supplying the reference currents to the current driver IC. In the next frame, the odd frame current source block 6-1 in each current driver IC carries out the current setting operation and the even frame current source block 6-2 outputs the reference currents.
The current setting operation in the twelfth embodiment is the same as those of the current source sections in the first to eighth embodiments. Therefore, it is possible to set the current to the plurality of current driver Ics without decrease of precision of the output currents. Also, in the twelfth embodiment, each current driver IC is composed of only the current source section, and the circuit scale can be made small, compared with the ninth to eleventh embodiments.
As shown in
Referring to
The input current copier block is composed of an N-type transistor Ncs connected between the common node NSCOM and a voltage VS, a capacitance Ccs connected between the gate of the N-type transistor Ncs and the voltage VS and a switch S_n connected between the common node NSCOM and the gate of the N-type transistor Ncs.
An operation of the thirteenth embodiment is shown in the timing charts shown in
In the structure of the fourteenth embodiment, the circuit structures shown in the above embodiments are changed and used for the current driver circuit to output analog currents in accordance with the digital display data.
The operation of the reference current source circuit in the fourteenth embodiment is the same as that of the first embodiment except that the operation of the switches in the resistance string section 2C is determined based on the digital display data. However, in the fourteenth embodiment, a period for the current setting operation or the current outputting operation is one horizontal period, in spite of one frame in the first embodiment, as shown in
The fourteenth embodiment has six outputs Io0 to Io5, and can drive six loads at a time. The number of outputs can be increased to the number of current copier current sources in which the current setting operation can be carried out for one horizontal period. Also, by producing the current setting resistance Rc precisely, the precision of the output current can be improved. If a plurality of current source circuits in the fourteenth embodiment are provided, it is possible to increase the number of outputs.
It should be noted that the idea of the fourteenth embodiment can be applied to each of the second to eighth embodiments.
Also, the resistance values of R1 to R63 in the resistance string section of the fourteenth embodiment may be same, or may be set such that the output current has a function value shown in
It should be noted that the number of outputs and the number of the current sources in the above embodiments are only for the description, and the present invention is not basically limited to them.
As described above, according to the present invention, even if there is a deviation in the current characteristic of the transistors, the current source circuit can output a plurality of output currents with a higher precision.
Also, according to the current source circuit of the present invention, the values of elements of the current source circuit can be changed while a ratio of the plurality of output currents is kept.
Also, according to the current source circuit of the present invention, the value of the output current can be kept even if there is a deviation in the power supply voltage and the current load characteristic.
Also, a current source circuit with a higher precision is provided for the plurality of current driver ICs.
Also, the current driver IC is provided in which the gamma correction is possible.
| Number | Date | Country | Kind |
|---|---|---|---|
| 181901/2003 | Jun 2003 | JP | national |
This application is a continuation application of U.S. patent application Ser. No. 10/874,270, filed on Jun. 24, 2004, now U.S. Pat. No. ______.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10874270 | Jun 2004 | US |
| Child | 12149354 | US |
