A system for protecting a high-speed input/output pad of an integrated circuit. The system includes a preferably parasitic silicon controlled rectifier (SCR) and a triggering mechanism that preferably includes an NMOS triggering FET. The SCR includes an anode connected to the input/output pad and a trigger input. The anode and the trigger input form a reverse-biased junction that, during normal operation of the integrated circuit, isolates the triggering mechanism from the input/output pad when power is applied to the integrated circuit.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:
FIGS. 1 and 2 illustrate schematically a system for protecting an integrated circuit pad from an electrostatic discharge event, with the SCR shown in a plan view layout (not to scale) in FIG. 1 being represented in FIG. 2 by an equivalent circuit model.
Claims
1. A system for protecting an integrated circuit from an electrostatic discharge event at an input/output pad connected to the integrated circuit, the system comprising:
(a) a silicon controlled rectifier including:
(i) an anode operationally connected to the input/output pad, and(ii) a trigger input separate from said anode, and(b) a triggering mechanism operationally connected to said trigger input;
2. The system of claim 1, wherein said silicon controlled rectifier is operative to conduct at least a portion of a current caused by the electrostatic discharge event.
3. The system of claim 1, wherein said silicon controlled rectifier is parasitic.
4. The system of claim 1, wherein said anode includes a first p-type region; wherein said trigger input includes a first n-type region; wherein said silicon controlled rectifier further includes:
(iii) a cathode that includes a second n-type region, and(iv) a second p-type region;
5. The system of claim 1, wherein said triggering mechanism is operative, while power is not being applied to the integrated circuit, to trigger said silicon controlled rectifier to conduct at least a portion of a current caused by the electrostatic discharge event.
6. The system of claim 17 wherein said triggering mechanism includes:
(i) an inverter configured to be powered by the electrostatic discharge event,(ii) a resistor having a first terminal connected to said trigger input and a second terminal connected to an input of said inverter,(iii) a capacitor having a first terminal connected to said second terminal of said resistor and a second, grounded terminal, and(iv) a trigger transistor having a drain connected to said trigger input and also connected to a power supply line of the integrated circuit, a grounded source, and a gate connected to an output of said inverter;
7. The system of claim 1, wherein said triggering mechanism includes a transistor operative, when an electrostatic discharge event occurs, to conduct a triggering current so as to trigger said silicon controlled rectifier.
8. The system of claim 7, wherein said transistor is a field effect transistor.
9. The system of claim 1, wherein said silicon controlled rectifier has a trigger voltage of at most about 1.2V.
10. A method for protecting an integrated circuit from an electrostatic discharge event at an input/output pad connected to the integrated circuit, the method comprising the steps of:
(a) providing a silicon controlled rectifier including:
(i) an anode operationally connected to the input/output pad, and(ii) a trigger input separate from said anode; and(b) operationally connecting a triggering mechanism to said trigger input;
11. The method of claim 10, wherein said diode is reverse biased when power is applied to the integrated circuit.
12. The method of claim 10, wherein said triggering mechanism is operative to trigger said silicon controlled rectifier to conduct at least a portion of a current caused by the electrostatic discharge event while power is not being applied to the integrated circuit.
Patent Application
20070228410
