In order to synthesize output signal at 2nd Nyquist zone, a mixing Digital to Analog Converter (DAC) is provided to make an analog output signal be toggled between a positive value and a negative value. However, as data needed to be processed by the DAC becomes faster, design of mixing DAC will be more difficult.
It is therefore an objective of the present invention to provide a DAC device, to solve the above-mentioned problems.
According to one embodiment of the present invention, a DAC device comprising a positive DAC, a negative DAC and an output circuit is disclosed. The positive DAC is configured to perform a digital-to-analog converting operation on a digital input signal based on a first pulse signal to generate a first analog signal, wherein the first analog signal is a convolution result of the first pulse signal and the digital input signal. The negative DAC is configured to perform the digital-to-analog converting operation on the digital input signal based on a second pulse signal to generate a second analog signal, wherein the second analog signal is a convolution result of the second pulse signal and the digital input signal. The output circuit is configured to generate an output analog signal according to the first analog signal and the second analog signal.
According to another embodiment of the present invention, a DAC device comprising a first DAC, a delay and multiplier circuit, a second DAC and an output circuit is disclosed. The first DAC is configured to perform a digital-to-analog converting operation on a digital input signal to generate a first analog signal. The delay and multiplier circuit is configured to delay and multiply the digital input signal by a dedicated number. An embodiment of the present invention, this number is −1. It generates a delayed and complementary digital signal. The second DAC is configured to perform the digital-to-analog converting operation on the delayed and complementary digital signal to generate the second analog signal. The output circuit is configured to combines half of the first analog signal and half of the second analog signal to generate an output analog signal.
According to another embodiment of the present invention, digital-to-analog converting method comprises the steps of: performing a digital-to-analog converting operation on a digital input signal based on a first pulse signal to generate a first analog signal, wherein the first pulse signal comprises a positive value; performing the digital-to-analog converting operation on the digital input signal based on a second pulse signal to generate a first analog signal, wherein the second pulse signal comprises a negative value; and generating an output analog signal according to the first analog signal and the second analog signal.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ”. The terms “couple” and “couples” are intended to mean either an indirect or a direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
Specifically, referring to
In the embodiment shown in
In the operations of the DAC device 300, the first DAC 310 performs the digital-to-analog converting operation on the digital input signal x[n] based on a pulse signal (e.g. the first pulse signal shown in
The control signal generator 336 is configured to generate a first control signal Vc1 and a second control signal Vc2 to control the first switch 332 and the second switch 334, respectively. In one embodiment, the control signal generator 336 may generate the first control signal Vc1 and the second control signal Vc2 based on a clock signal CLK, the first control signal Vc1 may be equal to the clock signal CLK, and the second control signal Vc2 can be another clock signal generated by delaying the clock signal CLK with 180 degree, that is a phase difference between the first control signal Vc1 and the second control signal Vc2 is 180 degree. Then, the first switch 332 is controlled by the first control signal Vc1 to output the half period of the first analog signal V1 to the combiner 338, the second switch 334 is controlled by the first control signal Vc2 to output the half period of the second analog signal V2 to the combiner 338, and the combiner 338 combines the half period of the first analog signal V1 and the half period of the second analog signal V2 to generate the output analog signal Vout.
Step 400: the flow starts.
Step 402: perform a digital-to-analog converting operation on a digital input signal based on a first pulse signal having a positive step function to generate a first analog signal, wherein the first analog signal comprises a convolution result of the first pulse signal and the digital input value.
Step 404: perform the digital-to-analog converting operation on the digital input signal based on a second pulse signal having a negative step function to generate a second analog signal, wherein the second analog signal comprises a convolution result of the second pulse signal and the digital input value.
Step 406: generate an output analog signal according to the first analog signal and the second analog signal.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
This application claims the priority of U.S. Provisional Application No. 62/857,934, filed on Jun. 6, 2019, which is included herein by reference in its entirety.
Number | Date | Country | |
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62857934 | Jun 2019 | US |