Patent Application
20080008205
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principle of the invention. In the drawings:
Reference will now be made in detail to various embodiments of the present invention, examples of which are illustrated in the accompanying drawings. For easier understanding, like reference numerals denote like elements even in different drawings. Those typical technologies known in the art will not be described to clarify the sprit and scope of the present invention.
The I/O processor 105 is connected to a main PCI bus of an iSCSI storage system, and serves as a PCI bridge and a memory controller. In more detail, the I/O processor 105 performs an XOR operation using an XOR engine when calculating parity, and can reduce a load of a host CPU when implementing a redundant array of inexpensive disk (PAID) function so as to enhance stability and performance during disk storage. Also, instead of the host CPU, the I/O processor 105 rapidly performs a parity operation that is generally essential to process the iSCSI protocol. As a result, the I/O processor 105 allows the reduction in a load of the host CPU and accelerates the iSCSI processing speed.
The memory 106 serves as a buffer for processing the TCP/IP and IPsec protocols for inputted/outputted data, and stores the data.
The TOE controller 108 processes the Internet standard protocol (i.e., the TCP/IP) for the inputted/outputted data according to the control of the I/O processor 105. More specifically, the TOE controller 108 is a TCP/IP acceleration apparatus in which a TOE, which is a piece of NIC hardware, takes care of a load of the host CPU arising when processing the TCP/IP packets. The TOE controller 108, which is hardware, processes transport and network layers, which are usually processed by conventional software.
The IPsec controller 109 encodes and decodes the inputted/outputted data according to the control of the I/O processor 105. In detail, data inputted to the iSCSI storage system from an external network are decoded, while data transmitted through an IP network are encoded using a preset key. The IPsec controller 109 encodes and decodes the inputted/outputted data instead of the host CPU. As a result, the load of the host CPU of the iSCSI storage system can be reduced, and a high-speed iSCSI input/output function can be implemented.
Among the above-described elements of the data acceleration apparatus, the TOE controller 108 and the IPsec controller 109 are implemented in hardware.
In addition, the data acceleration apparatus is implemented in one personal computer, and the individual internal devices are connected with each other through the internal PCI bus 107.
The iSCSI storage system comprises a host CPU 101, a host memory 102, a bridge 103, a network controller 111, a disk controller 112, a main PCI bus 104, and the data acceleration apparatus 110. The host CPU 101 controls data reading and writing operations based on the iSCSI protocol. The host memory 102 is connected to the host CPU 101 to function as a buffer for the processing by the host CPU 101 and to provide a storage space. The bridge 103 provides an access to the host CPU 101 and the host memory 102. The network controller 111 connected to an external network, and transmits and receives data through the external network. The disk controller 112 reads data from a disk on which data are stored and write data on the disk. The main PCI bus 104 makes a connection between the bridge 103, the network controller 111 and the disk controller 112. The data acceleration apparatus 110 is connected to the main PCI bus 104 and processes the TCP/IP and IPsec protocols for the data that are read or written at the disk controller 112 according to read and write commands from the host CPU 101.
As described in
The bridge 103 allows data transmission by interconnecting the host CPU 101 that controls and manages the iSCSI storage system in overall, the host memory 102 that is connected to the host CPU 101, and other devices including the network controller 111 and the disk controller 112 with each other. The network controller 111 makes a connection with an external network, and supports a TCP checksum for data inputted to or outputted from the external network, and scatter/gather transmission. Also, the network controller 111 performs zero-copy transmission for data stored on the memory 106. The zero-copy transmission results in exclusion of inter-memory copies. This exclusion of the inter-memory copies contributes to an improvement on the network transmission performance. The disk controller 112 reads data from and write data on the disk, which is a data storage unit of the iSCSI storage system.
The data acceleration apparatus 110 is connected to the iSCSI storage system through the main PCI bus 104.
When the disk controller 112 reads data from the disk, the data acceleration apparatus 110 stores the read data on the memory 106, and processes the TCP/IP and IPsec protocols using the TOE controller 108 and the IPsec controller 109. Afterwards, the data are transferred to the network controller 111. On the other hand, when the data inputted to the network controller 111 are written on the disk, the inputted data are stored on the memory 106, and the TOE controller 108 and the IPsec controller 109 process the TCP/IP and IPsec protocols. Afterwards, the data are transferred to the disk controller 112.
In the above iSCSI storage system, the host CPU 101 does not need to process the TCP/IP and IPsec protocols. Thus, the host CPU 101 has a reduced load. Also, the bottleneck event, which may occur during the data transfer, can be eliminated by minimizing the number of transferring data through the bridge 103.
The data reading operation will be described with reference to
If the data reading from the disk in the iSCSI storage system is requested, a data reading command is transmitted from the host CPU 101 to the data acceleration apparatus 110. In this case, the data acceleration apparatus 110 reads data from the disk, which is a storage unit, and transfers the read data to an iSCSI initiator through a network.
At this time, the data processing for the high-speed data input/output proceeds as follows.
First, in operation of 201, the disk controller 112 reads the requested data on the disk, and stores the data on the memory 106 through the I/O processor 105 of the data acceleration apparatus 110. At this time, the stored data do not proceed with the processing of the TCP/IP and IPsec protocols.
Second, in operation of 202, the IPsec controller 109 receives the data stored on the memory 206 through the I/O processor 105, and encodes the corresponding data using a preset key. Afterwards, the encoded data are stored on the memory 106 through the I/O processor 105.
Third, in operation of 203, the TOE controller 108 reads the encoded data stored on the memory 106 through the I/O processor 105. The TOE controller 108 directly handles media access control (MAC) without interference from the host CPU 101, and offloads the entire stack of the TCP/IP and transfers the offloaded data to the network controller 111.
In the typical iSCSI storage system that does not comprise the data acceleration apparatus 110, for the data reading operation, data stored on the disk are read and transferred through the bridge. Then, the data are stored on the host memory, and the host CPU encodes the data and performs the TCP/IP processing. Afterwards, the data are transferred to the network controller through the bridge. As a result, the host CPU tends to have an increased load and a bottleneck event usually occurs at the bridge. In contrast, in the iSCSI storage system including the data acceleration apparatus 110 according to the embodiment of the present invention, once the host CPU 101 transfers the data read command to the data acceleration apparatus 110, the data acceleration apparatus 110, more particularly, interactions between the disk controller 112, the data acceleration apparatus 110 and the network controller 111 allows the processing of the TCP/IP and IPsec protocols and the execution of the data reading operation. Hence, the high-speed data processing can be realized. Since the data do not need to pass through the bridge 103, the bottleneck event does not occur at the bridge 103. Also, the load of the host CPU 101 can be reduced.
With reference to
When the data writing is requested to the iSCSI storage system, a write command is transferred from the host CPU 101 to the data acceleration apparatus 110. The data acceleration apparatus 110 receive data transferred from an iSCSI initiator through a network. Then, the data acceleration apparatus 110 processes the TCP/IP of the received data and decodes the data. The decoded data are stored on the disk.
In more detail, the iSCSI-based data writing operation for the high-speed data input/output proceeds as follows.
First, in operation of 301, data that are transferred from an external network to be written on the disk are inputted to the network controller 111, and stored on the host memory 102 through the bridge 103. This operation is to perform basic operations including checking whether the data inputted from the external network are insecure data, which may cause damage to the security (e.g., hacking data). The host CPU 101 performs the basic operations. If the checking result by the host CPU 101 is normal (i.e., the normal data), the data write command is transferred to the data acceleration apparatus 110. If the checking result is not normal, the data are discarded.
Second, in operation of 302, the TOE controller 108 reads the data that are inputted from the external network and then stored on the host memory 102 through the I/O processor 105. The TOE controller 108 offloads the entire stack of the TCP/IP without interference from the host CPU 101 and stores the data on the memory 106 through the I/O processor 105.
Third, in operation of 303, the IPsec controller 109 receives the data processed by the TOE controller 108 and then stored on the memory 106 and decodes the received data using a preset key. Afterwards, the IPsec controller 109 transfers the decoded data to the disk controller 112 and stores the data on the disk.
According to the data writing operation, the host CPU 101 performs an operation of checking the normal or abnormal data and transfers the write command for the normal data to the data acceleration apparatus 110. The data acceleration apparatus 110 and the disk controller 112 perform the data writing operation. As a result, the CPU host 101 can have a reduced load, and data can process at high speed.
According to various embodiments of the present invention, when implementing the data storage apparatus, the data acceleration apparatus replaces the host CPU of the iSCSI storage system by protecting data, performing the TCP/IP and/or IPsec protocol processing, which often causes a bottleneck event, supporting a RAID function, and performing a parity operation. Hence, the data input/output can be accelerated through using the hardware (e.g., the TOE controller). Also, a load of the host CPU can be reduced and high-speed data input/output can be achieved.
According to the data acceleration method described in the above embodiments of the present invention, the number of copies between the memories during the iSCSI protocol processing can be minimized to thereby optimize the performance. Also, the number of data transfer through the PCI bus is minimized to eliminate the bottleneck event at the PCI bus.
The above described method according to the present invention can be embodied as a program and stored on a computer readable recording medium. The computer readable recording medium is any data storage device that can store data which can be thereafter read by the computer system. The computer readable recording medium comprises a read-only memory (ROM), a random-access memory (RAM), a CD-ROM, a floppy disk, a hard disk, an optical magnetic disk, and carrier waves such as data transmission through the Internet. The computer-readable recording medium can also be distributed over network-coupled computer systems so that the computer-readable code is stored and executed in a distributed fashion. Also, functional programs, codes, and code segments for accomplishing the present invention can be easily construed by programmers skilled in the art to which the present invention pertains.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2006-0064072 | Jul 2006 | KR | national |
