Patent Application
20090177852
1. Field of the Invention
The invention relates to radio communications, and, more particularly, to techniques of decoding data blocks in a communication system.
Wireless telecommunication systems are well known in the art. In order to provide global connectivity for wireless systems, standards known as Global System for Mobile Telecommunications (GSM) have been developed. This is considered as a so-called Second Generation mobile radio system standard (2G) and was followed by its revision (2.5G). GPRS and EGPRS are examples of 2.5G technologies that offer relatively high speed data service on top of the (2G) GSM network. EGPRS can provide a data rate up to 384 kbps. In wireless communication, the signal may experience a multi-path channel. A signal passing through a multi-path channel has various amplitudes and phases, which decreases the rate of successful decoding. In a high speed data communication system like EGPRS, it is more difficult to decode the received data with an acceptably low error rate.
To guarantee data transmission quality in a wireless environment, some standards use the hybrid automatic repeat request (Hybrid-ARQ, or H-ARQ) scheme to prevent data loss or unsuccessful decoding. The hybrid-ARQ combines both ARQ (automatic repeat request) and FEC (forward error correction code) to achieve good data quality. The FEC uses convolution or turbo code to generate data in transmitter with more redundancy and can be correctly received by the receiver even if the wireless environment corrupts a portion of the received data. The ARQ is a scheme in which a receiver can continuously report data reception status to the transmitter and the transmitter can re-send data blocks lost by the receiver.
The hybrid ARQ combines both schemes and can further separate into type I H-ARQ, type II H-ARQ, and type III H-ARQ. Type I H-ARQ simply re-transmits the bad data packet and the receiver re-decodes the re-transmitted data packet. Both type II and III H-ARQs require large memory to store the previous unsuccessfully decoded data packet. The memory is usually called incremental redundancy (IR) memory.
In one aspect of the invention, a data block receiver for decoding a data block is provided. The data block has a block sequence number (BSN) and consists of N bursts. The data block receiver comprises a first and second de-interleavers, a memory circuitry, a first and a second scale unit, a combiner, a decoder, and an error detector. The first de-interleaver performs an interleaving process for rearranging a data block and obtaining a first de-interleaved data blocks. The memory circuitry determines whether the data block is the newest received data block according to the block sequence number (BSN) corresponding to the data block. A stored data block with the same BSN is retrieved from the memory circuitry when the data block is not the newest data block. The first scale unit performs a first scale process on the retrieved data block. The second de-interleaver performs the interleaving process for rearranging the first scaled data block and obtains a second de-interleaved data block. The combiner combines the second de-interleaved data block and the first de-interleaved data block to obtain a combined data block. The decoder decodes the combined data block. The error detector detects whether an error exists in the decoded data block. The second scale unit performs a second scale process on the data block to obtain a second scaled data block. The second scale process is a process that reverts the first scale process. The second scaled data block is delivered to the memory circuitry when the error in the decoded data block is detected.
A method for decoding a data block is also provided. The data block comprises N bursts, and each burst further comprises a plurality of symbols. The method comprises de-interleaving the data block to obtain a de-interleaved data block. The de-interleaved data block is de-punctured to obtain a first de-punctured data block. The block sequence number (BSN) of the data block is examined to determine whether the data block is the newest received data block. A data block with the same BSN from a memory circuitry is retrieved when the BSN of the data block is not the newest data block. N scale factors are obtained, where each scale factor corresponds to a burst of the data block. A first scale process is performed on the retrieved data block to obtain a first scaled data block. The first de-interleaved data block is combined with the corresponding second de-interleaved data block to form the combined data block. The combined data block is then decoded. If any error is detected in the decoded data block, a second scaled data block is stored in the memory circuit. The second scale data block is formed by scaling the received data block by a second scale process.
The invention will become more fully understood from the detailed description, and the accompanying drawings. The drawings and description are provided for purposes of illustration only, and, thus, are not intended to be limiting of the invention.
a and 7b show a flowchart of a method for decoding a data block; and
c and 7d show a flowchart of a method for decoding a data block.
The second scale process can compress the dynamic range of the stored data, thus the bit-width of the memory circuitry is reduced. In some embodiments, such as the hybrid ARQ data block receiver, the feature makes managing the memory circuitry easier. The second scaled data block is recovered from the received data block.
The memory circuitry, in some embodiments, further records the number of stored data blocks, and discards the oldest data block when the number of stored data blocks exceeds a predetermined data block number.
In some embodiments, the data block receiver further comprises a limiter 218. The limiter, coupling to the second scale unit 210, limits signal levels of the scaled data block to a predetermined signal level. The memory circuitry 206 in the embodiment stores the limited data block instead of the scaled data block to further decrease the bit-width of the memory circuitry.
The error detector 216 can a CRC check, and the decoder may vary, depending on which coding scheme the data block is encoded by. For example, the decoder may be a convolutional decoder or a turbo decoder.
In some embodiments, the data block is punctured before being transmitted. Thus, the data block receiver further comprises a first and a second de-puncturing unit 222 and 220 to recover the puncturing. The first and the second de-puncturing units 222 and 220 de-puncture the first interleaved data block and the second de-interleaved data block respectively to obtain a first de-punctured data block and a second de-punctured data block. The combiner 212 combines portions of the first de-punctured data block with corresponding portions of the second de-punctured data block.
In other embodiments, the data block is stored after de-interleaving, thus only one de-interleaver is required.
a and 7b show a flowchart of a method for decoding a data block, wherein a data block, comprising N bursts, is punctured before transmitting, and each burst further comprises a plurality of symbols. The method comprises de-interleaving the data block according to a first de-interleaving process to obtain a de-interleaved data block in step 701. The de-interleaved data block is de-punctured to obtain a first de-punctured data block. In step 702, the block sequence number (BSN) of the data block is examined to determine whether the data block is the newest received data block. When the BSN of the data block is not the newest data block, a previous received data block with the same BSN is obtained in step 704-708. If the data block is the newest received data block, step 704-708 is skipped. In step 704, a data block with the same BSN from a memory circuitry is retrieved. N scale factors are obtained in step 705, where each scale factor corresponds to a burst of the data block. A first scale process is performed on the retrieved data block to obtain a first scaled data block. In step 706, the first scaled data block is de-interleaved to obtain a second de-interleaved data block. In step 707, the first de-interleaved data block is de-punctured to obtain a second de-punctured data block. Portions of the first de-punctured data block are combined with corresponding portions of the second de-punctured data block to form the combined data block in step 708. The combined data block or the newest received data block is decoded in step 709. In step 710, the decoded data block is detected to check if any error exists in the decoded data block. If any error is detected in the decoded data block, a limited data block is stored in the memory circuit in step 712. Limiting the symbols of the second scaled data block into a predetermined signal level forms the limited data block. The second scale data block is formed in step 711 by scaling the data block with a second scale process. The second scale process is a reverse process of the first scale process. For example, if the first scale process comprises multiplying a multiplicand with a scale factor, the second scale process may comprises dividing the first scaled result with the scale factor. In step 713, the number of stored data blocks is recorded. If the number of stored data blocks exceeds a predetermined data block number, the oldest data block is discarded in step 715. If no error is detected in the decoded data block in step 710, the data block stored in the memory circuitry is cleared in step 716, and acknowledgement is sent to the transmitter that originally transmitted the data block in step 717.
In another embodiment of the invention, the stored data block is de-interleaved. Thus, retrieving this data block can eliminate a de-interleaving process. The scale process, however, requires modification.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
