The present invention relates generally to processing data in a data channel and, in particular, to a channel in which an analog signal is sampled at a rate which is less than the channel bit rate.
Sampled amplitude read channels have long been employed in communications devices. The term “communications devices” is used herein generically and refers to any device or process in which encoded information is transmitted/received through wired or wireless means. Such devices include, but are not limited to, wireless computer networks and storage channels, such as used in magnetic or optical storage devices. As is well known, information is encoded into a two-level (binary or digital) form which is easy to manipulate, transmit and store. Data is thus stored on magnetic media as flux changes and stored on optical media (such as a CD or DVD) as pits and lands or phase changes in a surface of the media. Data is transmitted wirelessly as changes in electromagnetic radiation.
To read data, a signal which contains the binary data is first received, such as by an RF receiver in a wireless communications environment or by a transducer in a storage environment. The receiver or transducer produce an analog electrical signal in which transitions of the data bits are represented by changes in the electrical waveform. After amplification and other pre-processing, components in the data channel periodically sample the analog waveform; a sequence of samples is processed into a digital data stream of channel bits which are decoded into the original user data bits.
In order to reduce the negative effects of noise, inter-symbol interference and other factors, and to thereby increase the density with which data can be stored and/or the speed at which data can be transmitted, the data may be encoded such that only certain predetermined sequences of transitions in the signal are allowed. A commonly used encoding scheme is a run-length-limited RLL(d,k) code. In such a scheme, there must be at least ‘d’ potential bit transitions between any two actual transitions in the bit stream in order to ensure that two successive transitions are detectable. Additionally, there must be no more than ‘k’ potential bit transitions between any two actual transitions in order to ensure that proper sampling timing may be maintained. Additionally, rather than attempt to detect each individual transition, a sequence detector, such as a Viterbi detector, is commonly used to detect whether, and which, one of the allowed transition sequences is present.
A sampled amplitude sequence detector 110 receives the samples (directly or indirectly) from the sampling device 102. The detector 110, again operating at a channel bit rate which is the same data rate as the sampling device 102, processes the samples and outputs a stream of channel bits 112 which are estimated to be the most likely sequence of the digital data. The channel bits 112 are then decoded by a decoder 114 to regenerate the original user data.
Additional components in the channel 100 typically include a pre-amp 116 to boost the received signal, a variable gain amplifier (“VGA”) 118 to adjust the analog signal's amplitude to a nominal value, a low pass filter (“LPF”) 120 to attenuate noise in the analog signal, an equalizer (“EQ”) 122 to shape the sample values from the sampling device 102 to a predetermined partial response target, and other components, such as a gain control 124 and an equalization (“EQ”) control 126. The details of conventional data encoding, sampling, sequence detection, decoding and error detection are well known.
Components in the prior art data channel 100 all process data at the same rate, the transmission baud rate, and, because the channel bit rate is the same as the transmission baud rate (and sampling rate), one channel bit is output from the detector 110 for each sample processed by the sampling device 102. When the RLL ‘d’ constraint equals 0, the sampling rate is twice highest frequency of the analog waveform and, therefore, conforms to the Nyquist sampling criterion. Even as channels have advanced, however, the sampling rate has continued to equal the bit rate which, for d>0, is greater than the minimum rate to conform to the Nyquist theorem.
Moreover, due to code constraints and pickup limitations of optical pickups, much of the signal energy, and therefore much of the information content, has dissipated at frequencies beyond about one-fourth of the sampling frequency fs.
The present invention provides a data channel in which the sampling rate fs is less than the channel bit rate fb. The data channel may be part of an optical storage drive in which data has been RLL encoded at d>0 and the sampling rate may be one-half the channel bit rate. Preferably, a sequence detector is employed which outputs two channel bits for each input sample.
In one embodiment, the data channel comprises a receiver, a sampling device coupled to the output of the receiver and a detector. As used herein, the term “couple” should not be interpreted as being limited only to direct connections between two components, devices or means (generically referred to as “elements”) but may also refer to an indirect relationship in which two elements are separated by one or more intermediary elements such that a path exists between the two elements which includes the intermediary element(s). The receiver processes a binary coded signal having potential transitions occurring at a first frequency and actual successive coded transitions being separated by at least one potential transition. The sampling device outputs digital samples at a second frequency which is less than the first frequency. The detector processes the digital samples and generates channels bits at the first frequency. The binary coded signals may be received from any of a variety of signal sources, such as, but not limited to, an optical disc (such as CD or DVD), magnetic media or a wireless data transmitter.
The channel 400 includes a sampling device 410 for sampling the input signal and a clock 412 or other means for establishing the rate fs at which the input signal is sampled. Any method of retiming or timing recovery may be used with the present invention, such as by varying an ADC clock (such as by using a variable controlled oscillator) or by taking the samples and processing them digitally (such as by using interpolated timing recovery (ITR)). Thus, the functions of the sampling device 410 and clock 412 may be provided by any suitable component or set of components, including a complex digital retiming unit. An optional signal processor 420 may be employed to shape the sample waveform to a desired target waveform. The processor 420 may be an equalizer, ITR (as part of the sampling device 410 and clock 412), equalization with ITR, or some other appropriate device. A detector 430, operating at the rate fb established by a second clock 432 processes the samples and generates a series of channel bits 440. Additional processing (not shown) is then performed on the channel bits 440 to generate data which represents the original user data. It will be appreciated that, for clarity, numerous other processing blocks are not included in
In accordance with the present invention, the sampling rate fs is less than the transmitted bit rate fb and, preferably, about one-half the bit rate fb as illustrated in the plots of
A data channel in which read signals are processed in parallel and in which the present invention may be implemented is described in commonly-assigned U.S. Pat. No. 5,867,331, entitled “Synchronous Read Channel Processing More than One Channel Sample at a Time to Increase Throughput” and incorporated herein by reference in its entirety.
Commonly assigned U.S. Pat. No. 5,291,499, entitled “Method and Apparatus for Reduced-Complexity Viterbi-Type Sequence Detector”, which is also incorporated herein in its entirety, discloses a detector configured to output two channel bits substantially in parallel for each input sample.
The objects of the invention have been fully realized through the embodiments disclosed herein. Those skilled in the art will appreciate that the various aspects of the invention may be achieved through different embodiments without departing from the essential function of the invention. The particular embodiments are illustrative and not meant to limit the scope of the invention as set forth in the following claims. Moreover, although described above with respect to apparatuses for processing a binary coded signal, the need in the art may also be met by a method for processing a binary coded signal.