DATA COMMUNICATION CIRCUIT AND ARBITRATION METHOD

Abstract

A statistical-information generating unit monitors packet data output from a transaction layer that constitutes architecture of a PCI Express. The result of the monitored is feedback-controlled to a weight-information updating unit in real time, and is reflected in an arbitration table. A priority is set to the packet data corresponding to a quantity of the packet data actually transferred on a serial communication path.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a configuration example of an existing PCI block;

FIG. 2 is a block diagram of a configuration example of a PCI Express system;

FIG. 3 is a block diagram of a configuration example of a PCI Express platform in a desktop/mobile unit;

FIG. 4 is a schematic of a configuration example of a physical layer of x4;

FIG. 5 is a schematic of a connection example of a lane between devices;

FIG. 6 is a block diagram of a logical configuration example of a switch;

FIG. 7A is a block diagram of architecture of an existing PCI;

FIG. 7B is a block diagram of architecture of a PCI Express;

FIG. 8 is a block diagram of a hierarchical structure of a PCI Express;

FIG. 9 is a schematic for explaining an example of a format of a transaction layer packet;

FIG. 10 is a schematic for explaining a configuration space of a PCI Express;

FIG. 11 is a schematic for explaining a concept of a virtual channel;

FIG. 12 is a schematic for explaining an example of a format of a data link layer packet;

FIG. 13 is a schematic for explaining an example of a byte striping in an x4 link;

FIG. 14 is a schematic for explaining a definition of a link state called L0/L0s/L1/L2;

FIG. 15 is a timing chart of a control example of power supply management of an active state;

FIG. 16 is a block diagram of an outline of a data communication apparatus according to a first embodiment of the present invention;

FIG. 17 is a block diagram of an outline of a data communication apparatus according to a second embodiment of the present invention; and

FIG. 18 is a block diagram of an outline of a data communication apparatus according to a third embodiment of the present invention.

Claims

1. A data communication circuit that receives data as a master of a plurality of communications via one virtual channel in a high-speed serial bus, and that arbitrates the data with an arbiter by using an arbitration table to obtain arbitrated data, and outputs the arbitrated data to the high-speed serial bus, the data communication circuit comprising: a statistical-information generating unit that is provided on a serial communication path via a transaction layer constituting architecture of the high-speed serial bus, and that generates statistical information about a traffic based on a quantity of packet data transferred on the serial communication path; anda weight-information updating unit that updates weight information of the arbitration table based on the statistical information generated by the statistical-information generating unit.

2. The data communication circuit according to claim 1, wherein the arbitration table stores therein weight information of an Weighted Round Robin (WRR) algorithm.

3. The data communication circuit according to claim 1, wherein the statistical-information generating unit counts number of times when packet data is issued for each traffic class allocated to packet data output from the transaction layer, and sets a count value of each traffic class as the statistical information.

4. The data communication circuit according to claim 1, wherein the statistical-information generating unit calculates an integrated value of a length field value of a data transfer request packet output from the transaction layer, and sets a ratio of data size of the request packet as the statistical information.

5. The data communication circuit according to claim 1, wherein the weight-information updating unit compares reference information as a ratio of data transfer rates required by communication masters with a ratio of statistical information from the statistical-information generating unit, and updates values in the arbitration table.

6. The data communication circuit according to claim 1, further comprising a second statistical-information generating unit that is provided in the output of the arbiter, and that generates statistical information about a traffic based on a quantity of packet data transferred on the serial communication path, wherein the weight-information updating unit updates values of the arbitration table so as not to interrupt the communications of a low-priority device due to an excessively high priority placed on a high-priority device, based on the statistical information of the traffic generated by the second statistical-information generating unit.

7. The data communication circuit according to claim 6, wherein the second statistical-information generating unit counts number of times when packet data is issued for each traffic class allocated to the packet data output from the arbiter, and sets a count value of each traffic class as the statistical information.

8. The data communication circuit according to claim 6, wherein the second statistical-information generating unit calculates an integrated value of a length field value of a data transfer request packet output from the arbiter, and sets a ratio of data size of the request packet as the statistical information.

9. The data communication circuit according to claim 1, further comprising a buffer monitoring unit that is provided on a serial communication path via a transaction layer constituting architecture of the high-speed serial bus, and that monitors idle capacity of a posted request buffer and a non-posted request buffer of the transaction layer, wherein the weight-information updating unit that updates weight information of the arbitration table based on the idle capacity monitored by the buffer monitoring unit such that read requests and write requests are not over issued.

10. The data communication circuit according to claim 1, wherein the high-speed serial bus is of PCI Express standard.

11. An arbitration method to be realized on a data communication circuit that receives data as a master of a plurality of communications via one virtual channel in a high-speed serial bus, and that arbitrates the data with an arbiter by using an arbitration table to obtain arbitrated data, and outputs the arbitrated data to the high-speed serial bus, the arbitration method comprising: generating statistical information about a traffic based on a quantity of packet data transferred on a serial communication path via a transaction layer constituting architecture of the high-speed serial bus; andupdating weight information of the arbitration table based on the statistical information generated at the generating.

12. The arbitration method according to claim 11, wherein the arbitration table stores therein weight information of an Weighted Round Robin (WRR) algorithm.

13. The arbitration method according to claim 11, wherein the generating includes counting number of times when packet data is issued for each traffic class allocated to packet data output from the transaction layer, and setting a count value of each traffic class as the statistical information.

14. The arbitration method according to claim 11, wherein the generating includes calculating an integrated value of a length field value of a data transfer request packet output from the transaction layer, and setting a ratio of data size of the request packet as the statistical information.

15. The arbitration method according to claim 11, wherein the updating includes comparing reference information as a ratio of data transfer rates required by communication masters with a ratio of statistical information obtained at the generating, and updating values in the arbitration table.

16. The arbitration method according to claim 11, further comprising second generating including generating statistical information of traffics based on a quantity of packet data output from the arbiter and transferred on the serial communication path, whereinthe updating includes updating values of the arbitration table so as not to interrupt the communications of a low-priority device due to an excessively high priority placed on a high-priority device, based on the statistical information of the traffic generated at the second generating.

17. The arbitration method according to claim 16, wherein the second generating includes counting number of times when packet data is issued for each traffic class allocated to the packet data output from the arbiter, and setting a count value of each traffic class as statistical information.

18. The arbitration method according to claim 16, wherein the second generating includes calculating an integration value of a length field value of a data transfer request packet output from the arbiter.

19. The arbitration method according to claim 11, further comprising monitoring an idle capacity of each of a posted request buffer and a non-posted request buffer in a transaction layer constituting architecture of the high-speed serial bus, whereinthe updating includes updating values of the arbitration table to prevent a read request and a write request from being excessively issued in bias, based on the idle capacities of the posted request buffer and the non-posted request buffer respectively input at the monitoring.