This application is a Continuation, of application Ser. No. 07/590,107, filed Sep. 28, 1990, now abandoned.
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4604682 | Schwan et al. | Aug 1986 | |
4730268 | Marin | Mar 1988 | |
4933840 | Sera et al. | Jun 1990 | |
4954983 | Klingman | Sep 1990 | |
4959782 | Tulpule et al. | Sep 1990 | |
4989135 | Miki | Jan 1991 | |
4998198 | Chan | Mar 1991 | |
5072420 | Conley et al. | Dec 1991 | |
5151999 | Marzuco et al. | Sep 1992 | |
5163132 | Dulal et al. | Oct 1992 | |
5179662 | Corrigan et al. | Jan 1993 | |
5261064 | Wyland | Nov 1993 |
Entry |
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Dally and Song, Design of a Self-Timed VLSI Multicomputer Communication Controller; pp. 230-234; Rye Brook, N.Y. Oct. 5, 1987. |
Charles H. Ng; FIFO Buffering Transceiver: A Communication Chip Set for Multiporcessor Systems; pp. 1-60; Oct. 5, 1987; California Institute of Technology. |
Hillman, "Intelligent Buffer Reconciles Fast Processor & Slow Peripherals," Electronics, Sep. 11, 1980 pp. 131-135. |
Andrews, "ASIC Memories: Bigger, Faster & Customized", Computer Design, Oct. 1, 1988, pp. 44-62. |
"Rich with Logic, Memory ICs Hone Their Specialties", Electronic Design, Jun. 11, 1987 pp. 77-86. |
Number | Date | Country | |
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Parent | 590107 | Sep 1990 |