Claims
- 1. A data converter for converting an input signal to a digital signal, the data converter comprising:
n comparison units for respectively comparing the input signal with n reference signals to generate the corresponding digital signal, each of the comparison units including a positive output end and a negative output end, the digital signal being generated according to a positive output and a negative output of the comparison units in a differential manner; and n switch circuits respectively electrically connected to the positive output end and the negative output end of the n comparison units; wherein for a kth comparison unit, the corresponding kth switch circuit is further electrically connected to the positive output end of the kth−1 comparison unit and the negative output end of the kth+1 comparison unit; wherein when the kth comparison unit performs an auto-zeroing process, the kth switch circuit generates a digital signal corresponding to an interpolated value of the kth comparison unit from a positive output of the kth−1 comparison unit and a negative output of the kth+1 comparison unit.
- 2. The data converter of claim 1 wherein each of the comparison units comprises a latching circuit for outputting the digital signal.
- 3. The data converter of claim 1 wherein each of the comparison units comprises an amplifier for amplifying a voltage difference between the input signal and the corresponding reference signal so as to generate a corresponding positive output and a corresponding negative output.
- 4. The data converter of claim 3 wherein each of the comparison units further comprises a feedback circuit electrically connected between an output end and an input end of the amplifier, and when the comparison unit performs the auto-zeroing process, the feedback circuit conducts.
- 5. The data converter of claim 1 wherein the data converter further comprises a voltage dividing circuit for generating the n reference signals.
- 6. A method for a data conversion circuit for converting an input signal to a corresponding digital signal, the data conversion circuit comprising:
n comparison units for respectively comparing the input signal with n reference signals to generate the corresponding digital signal, each of the comparison units including a positive output end and a negative output end, the digital signal being generated according to a positive output and a negative output of the comparison units in a differential manner, the method comprising: when a kth comparison unit is performing an auto zeroing process, substituting the digital signal of the kth comparison unit with a replacement signal generated according to outputs of the positive output of the kth1 comparison unit and the negative output of the kth+1 comparison unit, such that when the output of the positive output of the kth1 comparison unit is less than the output of the negative output of the kth+1 comparison unit, the replacement signal is a first digital value, and when the output of the positive output of the kth1 comparison unit is greater than the output of the negative output of the kth+1 comparison unit, the replacement signal is a second digital value.
- 7. The method of claim 6 wherein the first digital value is a high logical value, and the second digital value is a low digital value.
- 8. A data converter for converting an analog signal to a plurality of digital bits, the data converter comprising:
n first comparison units for respectively comparing the input signal with n reference signals, each of the comparison units including a positive output end for outputting a first positive output and a negative output end for outputting a first negative output; n second comparison units for respectively comparing the input signal with the n reference signals, each of the second comparison units including a positive output end for outputting a second positive output and a negative output end for outputting a second negative output; and an output unit electrically connected to the n first comparison units and the n second comparison units for generating digital bits corresponding to the n first comparison units and the n second comparison units, the output unit comprising: n−1 interpolating units electrically connected to the n first comparison units and the n second comparison units, a kth interpolating unit being electrically connected to a kth and a kth+1 first comparison units and a kth and a kth+1 second comparison units for adding a third positive output to the first and second positive output of the n first comparison units and the n second comparison units and adding a third negative output to the first and second negative output of the n first comparison units and the n second comparison units; wherein when the kth and the kth+1 first comparison units perform an auto-zeroing process, the interpolating unit is capable of utilizing the second positive output of the kth and the kth+1 second comparison units for generating the third positive output and utilizing the second negative output of the kth and the kth+1 second comparison units for generating the third negative output; wherein the output unit generates a digital bit interpolated between a digital bit corresponding to the kth second comparison unit and a digital bit corresponding to the kth+1 second comparison unit according to the third positive output and the third negative output in a differential manner.
- 9. The data converter of claim 8 wherein the output unit further comprises a plurality of latches electrically connected to the first comparison units, the second comparison units, and the interpolating unit for outputting the digital bits.
- 10. The data converter of claim 8 wherein each of the first and second comparison units comprises an amplifier for amplifying a voltage difference between the input signal and the corresponding reference signal so as to generate a corresponding positive output and a corresponding negative output.
- 11. The data converter of claim 10 wherein each of the first and second comparison units further comprises a feedback circuit electrically connected between an output end and an input end of the amplifier, and when the comparison unit performs the auto-zeroing process, the feedback circuit conducts.
- 12. The data converter of claim 8 wherein the data converter further comprises a voltage dividing circuit for generating the n reference signals.
- 13. The data converter of claim 8 wherein the third positive output is interpolated between the second positive output of the kth and the kth+1 second comparison units, and the third negative output is interpolated between the second negative output of the kth and the kth+1 second comparison units.
- 14. A method for a data converter for converting an analog signal to a plurality of digital bits, the data converter comprising:
n first comparison units for respectively comparing the input signal with n reference signals, each of the comparison units including a positive output end for outputting a first positive output and a negative output end for outputting a first negative output, a digital bit corresponding to a first comparison unit being generated from the first positive output and the first negative output in a differential manner; n second comparison units for respectively comparing the input signal with the n reference signals, each of the second comparison units including a positive output end for outputting a second positive output and a negative output end for outputting a second negative output, a digital bit corresponding to a second comparison unit being generated from the second positive output and the second negative output in a differential manner, the method comprising: when a kth and a kth+1 first comparison units perform an auto-zeroing process, utilizing the second positive output of a kth and a kth+1 second comparison units for generating a third positive output, utilizing the second negative output of the kth and the kth+1 second comparison units for generating a third negative output, and generating a digital bit interpolated between a digital bit corresponding to the kth second comparison unit and a digital bit corresponding to the kth+1 second comparison unit according to the third positive output and the third negative output in the differential manner.
- 15. The method of claim 14 wherein the third positive output is interpolated between the second positive output of the kth and the kth+1 second comparison units, and the third negative output is interpolated between the second negative output of the kth and the kth+1 second comparison units.
- 16. A data converter for converting an analog signal to a plurality of digital bits, the data converter comprising:
n first comparison units for respectively comparing the input signal with n reference signals, each of the comparison units including a positive output end for outputting a first positive output and a negative output end for outputting a first negative output; n second comparison units for respectively comparing the input signal with the n reference signals, each of the second comparison units including a positive output end for outputting a second positive output and a negative output end for outputting a second negative output; and an output unit electrically connected to the n first comparison units and the n second comparison units for generating digital bits corresponding to the n first comparison units and the n second comparison units, the output unit comprising: n−1 interpolating units electrically connected to the n first comparison units and the n second comparison units, a kth interpolating unit being electrically connected to a plurality of (kth to kth+P) first comparison units and a plurality of (kth to kth+p) second comparison units for adding a plurality of positive output to the first and second positive output of the n first comparison units and the n second comparison units and adding a plurality of negative output to the first and second negative output of the n first comparison units and the n second comparison units; wherein when some first comparison units perform an auto-zeroing process, the interpolating unit is capable of utilizing the second positive outputs of the plurality of second comparison units for generating a plurality positive output and utilizing the second negative output of some second comparison units for generating some negative outputs; wherein the output unit generates a digital bit interpolated between a digital bit corresponding to the kth second comparison unit and a digital bit corresponding to the kth +p second comparison unit according to the positive outputs and the negative outputs in a differential manner.
- 17. The data converter of claim 16 wherein the output unit further comprises a plurality of latches electrically connected to the first comparison units, the second comparison units, and the interpolating unit for outputting the digital bits.
- 18. The data converter of claim 16 wherein each of the first and second comparison units comprises an amplifier for amplifying a voltage difference between the input signal and the corresponding reference signal so as to generate a corresponding positive output and a corresponding negative output.
- 19. The data converter of claim 18 wherein each of the first and second comparison units further comprises a feedback circuit electrically connected between an output end and an input end of the amplifier, and when the comparison unit performs the auto-zeroing process, the feedback circuit conducts.
- 20. The data converter of claim 16 wherein each of the positive outputs is interpolated between the second positive output of the kth to the kth +p second comparison units, and the each of the negative output is interpolated between the second negative output of the kth and the kth +p second comparison units.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] The following is a continuation-in-part of co-pending application 10/063,204, filed Mar. 28, 2002.
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
10063204 |
Mar 2002 |
US |
Child |
10604527 |
Jul 2003 |
US |