DATA DERATE MATCHER FOR SUPPORTING HARQ AND METHOD THEREOF

Abstract

A data derate matcher for supporting hybrid automatic repeat request (HARQ), includes a control parameter generation unit for generating control parameters to separate bits of an input bit stream ek; and a bit separation unit for separating the bits of the input bit stream ek into three types of bits streams v(0)k, v(1)k, and v(2)k by modulus operation of each of the bits of the input bit stream and the control parameters. Further, the data derate matcher for supporting the HARQ includes address generators for generating addresses (j) of valid data to be used in deinterleavers with respect to data of each of the bit streams output from the bit separation unit; and subblock deinterleavers for sequentially inputting data corresponding to the addresses generated by the address generators to output decoded data.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

The present invention claims priority to Korean Patent Application No. 10-2009-0124941 filed on Dec. 15, 2009, which is incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to the transmission of hybrid automatic repeat request (HARQ) in 3rd generation partnership project (3GPP) long term evolution (LTE) and 3GPP LTE advanced systems, and more particularly, to a data derate matcher that supports HARQ to perform more efficient derate matching in channel decoding of received data for the transmission of HARQ, and a method of the same.

BACKGROUND OF THE INVENTION

Generally, at a transmitting end of a 3GPP LTE system, a data coding process involves turbo coding HARQ data to be transmitted and performing data rate matching by a rate matcher to match the length of turbo coded data with the length of data required for wireless transmission. At a receiving end, a data decoding process involves executing data derate matching by a derate matcher to match the length of received data in wireless transmission with the length of input data to a turbo decoder.

FIG. 1 shows the configuration of a rate matcher for turbo coded data in a 3GPP LTE system of related art.

As shown in FIG. 1, a turbo coding rate matcher 100 performs a function of matching the number of input bits to a channel encoder with a total number of bits mapped to a physical channel (e.g., PUSCH or PDSCH). The function of the rate matcher 100 is controlled by a redundancy version (rv) parameter of HARQ, where rv has one of 0, 1, 2, and 3.

Referring to FIG. 1, the rate matcher 100 for turbo coded data includes subblock interleavers 102, 104, and 106 for three information bit streams d⁽⁰⁾k, d⁽¹⁾k, and d⁽²⁾k, a buffer unit 108, and a bit selection unit 110.

Input bit streams d⁽ⁱ⁾k are passed to the subblock interleavers 102, 104, and 106 to create v⁽ⁱ⁾k (where k=0, 1, . . . , k_Π), and interleaved data streams are temporarily stored in the buffer unit 108 and then certain bits are selected depending on the size of output bits by the bit selection unit 110 and output as a turbo coded bit stream e_k (where i=0, 1, 2).

Hereinafter, the operation of each component will be described in more detail.

First, the operation of the subblock interleavers 102, 104, and 106 will be discussed in detail.

• • Input bits of the subblock interleavers 102, 104, and 106: d⁽ⁱ⁾0, d⁽ⁱ⁾1, d⁽ⁱ⁾2, . . . , d⁽ⁱ⁾D−1 where D is the number of input bits and i=0, 1, and 2.
  • Output bits of the subblock interleavers: v⁽ⁱ⁾0, v⁽ⁱ⁾1, v⁽ⁱ⁾2, . . . v⁽ⁱ⁾K_Π−1, where K_Π will be defined below and i=0, 1, and 2.
  • Output bit sequences of the subblock interleavers are derived as follows.

(1) Number of matrix columns to be assigned: C_subblock=32, and the number of matrix columns: 0, 1, 2, . . . , C_subblock-1 from left to right.

(2) Calculation of minimum integer R_subblock satisfying the following condition: D≦(R_subblock×C_subblock), and rectangular matrix row number: 0, 1, 2, . . . , R_subblock-1 from top to bottom.

(3) If (R_subblock×C_subblock)>D, then dummy bits, N_D=(R_subblock×C_subblock−D), are added. That is, Y_k=<NULL>(where k=0, 1, . . . , N_D−1) and the input bit sequence is written in the (R_subblock×C_subblock) matrix as in the following Eq. (1).

In other words, y_ND+k=d⁽ⁱ⁾k (where k=0, 1, . . . , D−1). At this point, bit y₀ in 0th row and 0th column starts and then it continues row by row.

$\left[\mathrm{Equation}1\right]\left[\begin{array}{ccccc}{y}_0& y_1& y_2& \dots & y_{\mathrm{Csubblock}-1}\\ y_{\mathrm{Csubblock}}& y_{\mathrm{Csubblock}+1}& y_{\mathrm{Csubblock}+2}& \dots & y_{2\mathrm{Csubblock}-1}\\ ⋮& ⋮& ⋮& ⋮& ⋮\\ y_{\begin{array}{c}\left(\mathrm{Rsubblock}-1\right)\times \\ \mathrm{Csubblock}\end{array}}& y_{\begin{array}{c}\left(\mathrm{Rsubblock}-1\right)\times \\ \mathrm{Csubblock}+1\end{array}}& y_{\begin{array}{c}\left(\mathrm{Rsubblock}-1\right)\times \\ \mathrm{Csubblock}+2\end{array}}& \dots & y_{\left(\begin{array}{c}\mathrm{Rsubblock}\times \\ \mathrm{Csubblock}-1\end{array}\right)}\end{array}\right]$

In case of d⁽⁰⁾k and d⁽¹⁾k:

(4) Based on <P(j)>_{jε{0, 1, . . . ,} C_subbock-1} in Table 1 below, the inter-column permutation of the matrix is carried out.

Here, P(j) represents the original column position of a j-th permutated column. After column permutation, inter-column permutated (R_subblock×C_subblock) matrix is as follows:

$\left[\mathrm{Equation}2\right]\left[\begin{array}{ccccc}{y}_{P\left(0\right)}& y_{P\left(1\right)}& y_{P\left(2\right)}& \dots & y_{p\left(\mathrm{Csubblock}-1\right)}\\ y_{P\left(0\right)+\mathrm{Csubblock}}& y_{P\left(1\right)+\mathrm{Csubblock}}& y_{P\left(2\right)+\mathrm{Csubblock}}& \dots & y_{\begin{array}{c}P\left(\mathrm{Csubblock}-1\right)+\\ \mathrm{Csubblock}\end{array}}\\ ⋮& ⋮& ⋮& ⋮& ⋮\\ y_{\begin{array}{c}\begin{array}{c}P\left(0\right)+\\ \left(\mathrm{Rsubblock}-1\right)\times \end{array}\\ \mathrm{Csubblock}\end{array}}& y_{\begin{array}{c}\begin{array}{c}P\left(1\right)+\\ \left(\mathrm{Rsubblock}-1\right)\times \end{array}\\ \mathrm{Csubblock}\end{array}}& y_{\begin{array}{c}\begin{array}{c}P\left(2\right)+\\ \left(\mathrm{Rsubblock}-1\right)\times \end{array}\\ \mathrm{Csubblock}\end{array}}& \dots & y_{\begin{array}{c}\begin{array}{c}P\left(\mathrm{Csubblock}-1\right)+\\ \left(\mathrm{Rsubblock}-1\right)\times \end{array}\\ \mathrm{Csubblock}\end{array}}\end{array}\right]$

(5) Outputs of the subblock interleavers are created by reading the inter-column permutated (R_subblock×C_subblock) matrix column by column. Bits after the subblock interleaving are v⁽ⁱ⁾0, v⁽ⁱ⁾1, v⁽ⁱ⁾2, . . . , v⁽ⁱ⁾K_Π−1. Here, v⁽ⁱ⁾0 is y_p(0), v⁽ⁱ⁾1 is y_{p(0)+Csubblock . . .} , and K_Π=(R_subblock×C_subblock).

In case of d⁽²⁾k:

(6) Outputs of the subblock interleavers are v⁽ⁱ⁾0, v⁽ⁱ⁾1, v⁽ⁱ⁾2, . . . , v⁽ⁱ⁾K_Π−1. Here, V⁽²⁾k=y_Π(k), and

$\pi \left(k\right)=\left[p\left[\frac{k}{R_{\mathrm{subblock}}}\right]+C_{\mathrm{subblock}}\times \left(k\mathrm{mod}R_{\mathrm{subblock}}\right)+1\right]\mathrm{mod}K_{\prod }.$

TABLE 1
Inter-column permutation pattern of the subblock interleavers
Number of columns Inter-column permutation pattern
Csubblock         <P(0), P(1), . . . , P(Csubblock − 1)>
32                <0, 16, 8, 24, 4, 20, 12, 28, 2,
                  18, 10, 26, 6, 22, 14, 30, 1, 17,
                  9, 25, 5, 21, 13, 29, 3, 19, 11,
                  27, 7, 23, 15, 31>

Next, the operation of the buffer unit 108 and the bit selection unit 110 will be described in detail.

• • Generation of circular buffer having the length of K_W=3K_Π:

w _k =v _k ⁽⁰⁾fork=0, . . . ,K_Π−1

w _KΠ+2k =v _k ⁽¹⁾fork=0, . . . ,K_Π−1

w _KΠ+2k+1 =V _k ⁽²⁾fork=0, . . . ,K_Π−1

• • Rate matching output sequence length: E
  • Soft buffer size: N_cb (e.g., N_cb=Kw)
  • Rate matching output bit sequence: e_k (where k=0, 1, . . . , E−1)
  • HARQ redundancy version number: rv_idx (where rv_idx=0, 1, 2 or 3)

A start position K₀ of rate matcher bit selection is calculated as the following Equation 3:

$\begin{array}{cc}{k}_0=R_{\mathrm{subblock}}·\left[2·\left[\frac{N_{\mathrm{Cb}}}{8R_{\mathrm{subblock}}}\right]·{\mathrm{rv}}_{\mathrm{idx}}+2\right]& \left[\mathrm{Equation}3\right]\end{array}$

where R_subblock is the number of rows.

In this manner, the transmission of output data from the rate matcher 100 for the selected bit data is made as the following Equation 4:

$\begin{array}{cc}\mathrm{Setk}=0\mathrm{and}j=0\mathrm{while}\left\{k<E\right\}{\mathrm{ifw}}_{\left(k0+j\right)\mathrm{mod}\mathrm{Ncb}}\ne 〈\mathrm{NULL}〉e_k=w_{j\mathrm{mod}\mathrm{Ncb}}k=k+1\mathrm{endif}j=j+1\mathrm{endwhile}& \left[\mathrm{Equation}4\right]\end{array}$

As mentioned above, in the conventional rate matching process of the turbo coded data that supports HARQ, the dummy bits for an input data length D needs to be considered and the start position K₀ of the rate matcher for an HARQ redundancy version number rv needs also to be considered. Also, the transmission positions of a systematic data sequence S and parity data sequences P1 and P2 need to be considered.

However, the factors, such as the dummy bits and the redundancy version number rv start position K₀ considered in the conventional rate matching process of the turbo coded data that supports HARQ, also need to be taken into consideration in the derate matcher of the decoder of the receiving end. Therefore, the operation of the derate matcher is complicated, thus making the hardware configuration of the derate matcher complicated.

SUMMARY OF THE INVENTION

In view of the above, the present invention provides an efficient data derate matcher, which is adapted to input wirelessly received data to a turbo decoder in a data decoder, in the transmission and reception of turbo coded data that supports the HARQ function of the 3GPP LTE system, and a method of the same.

Further, the present invention provides a data derate matcher, which facilitates hardware implementation by simplifying a data processor based on a value of HARQ redundancy version number rv, without needing additional processing time taken for dummy bits required for operating the subblock interleaver of the derate matcher, and a method of the same.

In accordance with a first aspect of the present invention, there is provided a data derate matcher for supporting hybrid automatic repeat request (HARQ), including: a control parameter generation unit for generating control parameters to separate bits of an input bit stream e_k; a bit separation unit for separating the bits of the input bit stream e_k into three types of bits streams v⁽⁰⁾k, v⁽¹⁾k, and v⁽²⁾k by modulus operation of each of the bits of the input bit stream and the control parameters; address generators for generating addresses (j) of valid data to be used in deinterleavers with respect to data of each of the bit streams output from the bit separation unit; and subblock deinterleavers for sequentially inputting data corresponding to the addresses generated by the address generators to output decoded data.

In accordance with a second aspect of the present invention, there is provided a data derate matching method in a data derate matcher for supporting hybrid automatic repeat request (HARQ), including: generating control parameters to separate bits of an input bit stream e_k; separating the bits of the input bit stream e_k into three types of bits streams v⁽⁰⁾k, v⁽¹⁾k, and v⁽²⁾k by modulus operation of each of the bits of the input bit stream and the control parameters; generating addresses (j) of valid data to be used in deinterleavers with respect to data of each of the separated bit streams v⁽⁰⁾k, v⁽¹⁾k, and v⁽²⁾k; and

sequentially inputting data corresponding to the generated addresses among the respective bit stream data to output decoded data.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects and features of the present invention will become apparent from the following description of embodiments, given in conjunction with the accompanying drawings, in which:

FIG. 1 shows a block diagram of a rate matcher for turbo coded data in a 3GPP LTE system of related art;

FIG. 2 illustrates a block diagram of a derate matcher for turbo coded data in accordance with an embodiment of the present invention; and

FIG. 3 provides a flow chart for controlling the operation of bit separation in the derate matcher in accordance with the embodiment of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 illustrates a detailed block diagram of a derate matcher in accordance with an embodiment of the present invention. As illustrated therein, the derate matcher 200 includes a control parameter generation unit 201 for generating control parameters to separate bits of an input bit stream e_k, a bit separation unit 204 for separating the bits of the input bit stream e_k into three types of bit streams v⁽⁰⁾k, v⁽¹⁾k, and v⁽²⁾k by modulus operation of each of the bits of the input bit stream and the control parameters, address generators 220, 222, and 224 for generating addresses (j) of valid data to be used in a deinterleaver for each of the bit stream data v⁽⁰⁾k, v⁽¹⁾k, and v⁽²⁾k output from the bit separation unit 204, a buffer unit 206 for separating the respective bit stream data v⁽⁰⁾k, v⁽¹⁾k, and v⁽²⁾k to store same output from the bit separation unit 204, and subblock deinterleavers 214, 216, and 218 for sequentially inputting data corresponding to the addresses generated by the address generators 220, 222, and 224 to output decoded data.

Hereinafter, the operation of each component in the derate matcher 200 in accordance with the present invention will be described in detail with reference to FIG. 2.

First, the bit separation unit 204 performs bit separation on an input bit stream e_k having E bits input to the derate matcher 200.

In accordance with the embodiment of the present invention, in the bit separation process of the bit separation unit 204, the number of dummy bits is not calculated, but a bit stream having E bits is bit-separated to provide separated bit streams v⁽⁰⁾k, v⁽¹⁾k, and v⁽²⁾k, each having D bits, and then deinterleaved by the subblock deinterleavers 214, 216, and 218 to output d⁽⁰⁾k, d⁽¹⁾k, and d⁽²⁾k, respectively. That is, the dummy bits are considered by the subblock deinterleavers 214, 216, and 218, and thus, no additional data bit processing time is required for processing the dummy bits.

The bit separation unit 204 performs bit separation using Kstart and Kswitch inputted from the control parameter generation unit 201.

The number N_D of dummy bits used in the turbo coding rate matcher of the 3GPP LTE system has one of {4, 12, 20, 28} and the redundancy version number rv value has one of {0, 1, 2, 3}. Therefore, the control parameter generation unit 201 generates parameter values Kstart and Kswitch based on the dummy bit number N_D and the redundancy version number rv value, as in Tables 2 and 3 below, and then provides them to the bit separation unit 204. Here, R used in Tables 2 and 3 indicates a row value of the subblock deinterleavers 214, 216, and 218.

	TABLE 2
	rv
ND	0	1	2	3
4	2R-1	26R-4	50R-8	74R-10
12	2R-1	26R-10	50R-20	74R-30
20	2R-2	26R-17	50R-32	74R-48
28	2R-2	26R-23	50R-44	74R-66

TABLE 3
ND Kswitch
4  3D-16R+2
12 3D-12R+4
20 3D-14R+8
28 3D-10R+8

FIG. 3 illustrates an operation control flow for separating the input bit stream by the bit separation unit 204 in accordance with the embodiment of the present invention.

Referring to FIG. 3, the bit separation unit 204 receives parameter values, such as the number D of data bits in each bit stream, a row value R of the subblock deinterleavers 214, 216, and 218, Kstart and Kswitch values provided by the control parameter generation unit 201, a number E of data bits in an input bit stream, and the like, sets parameters for bit separation in step S300, and performs a bit separation process on the input bit stream e_k from k=0 to E−1 in step S302.

That is, if the setting of the parameters has been completed in this manner, the bit separation unit 204 first compares a (k+Kstart) % 3D value with a D value in step S304. If the (k+Kstart) % 3D value is less than the D value, the bit separation unit 204 stores the input data e_k in an address of (k+Kstart) % 3D of a 0th data memory 208 within the buffer unit 206 in step S306. Here, the operator ‘%’ indicates a modulus operation.

However, if the (k+Kstart) % 3D value is greater than or equal to the D value, the bit separation unit 204 proceeds to step S308 from step S304, which compares the (k+Kstart) % 3D value with a Kswitch value. If the (k+Kstart) % 3D value is less than the Kswitch value, a control process goes to step S310, and, if the (k+Kstart) % 3D value is greater than or equal to the Kswitch value, the control process goes to step S316.

As described above, if the (k+Kstart) % 3D value is less than the Kswitch value, the bit separation unit 204 checks whether a ((k+Kstart) % 3D−D) %2 value is 0 or 1 in step S310. If the ((k+Kstart) % 3D−D) %2 value is 0, the bit separation unit 204 stores the input data e_k in an address of ((k+Kstart) % 3D−D)/2 of a 1st data memory 210 within the buffer unit 206 in step S312.

However, if the ((k+Kstart) % 3D−D) %2 value is 1, the bit separation unit 204 stores the input data e_k in the address of ((k+Kstart) % 3D−D)/2 of a 2nd data memory 212 within the buffer unit 206 in step S314.

On the other hand, as a result of comparison in step S308, if the (k+Kstart) % 3D value is greater than or equal to the Kswitch value, the bit separation unit 204 proceeds to step S316 to check whether the ((k+Kstart) % 3D−D) %2 value is 0 or 1. As a result of checking, if the ((k+Kstart) % 3D−D) %2 value is 1, the control process goes to step S318 and the bit separation unit 204 stores the input data e_k in an address of ((k+Kstart) % 3D−D)/2 of the 1st data memory 210 within the buffer unit 206.

However, otherwise, if the ((k+Kstart) % 3D−D) %2 value is 0, the control process goes to step S320 and the bit separation unit 204 stores the input data e_k in the address of ((k+Kstart) % 3D−D)/2 of the 2nd data memory 212 within the buffer unit 206.

By such bit separation as shown in FIG. 3, the data of the input bit stream e_k is separated into three types of data v⁽⁰⁾k, v⁽¹⁾k, and v⁽²⁾k and then stored in the 0th to 2nd data memories 208, 210, and 210 within the buffer unit 206, respectively.

Then, the subblock deinterleavers 214, 216, and 218 generate addresses (j) of valid data to be used in a deinterleaver for each bit stream data outputted from the bit separation unit 204 by using the address generators 220, 222, and 224 implemented therein, and then sequentially read out data corresponding to the addresses generated by the address generation units 220, 222, and 224 from the data stored in the corresponding 0th to 2nd data memories 208, 210, and 212 within the buffer unit 206 to output the data which is sequentially read out as decoded data, thereby simply completing the deinterleaving operation.

Hereinafter, the deinterleaving operation of the data stored in the buffer unit 206, which is executed by the subblock deinterleavers 214, 216, and 218 will be described in detail.

The subblock deinterleavers 214, 216, and 218 deinterleave the bit stream data v⁽⁰⁾k, v⁽¹⁾k, and v⁽²⁾k, each having D bits, stored in the 0th to 2nd data memories 208, 210 and 212, respectively, to output d⁽⁰⁾k, d⁽¹⁾k, and d⁽²⁾k, each having D bits, by following equations.

First, for i=0 and 1, d⁽ⁱ⁾k=v⁽ⁱ⁾k where the output after the bit separation is in the form of a bit stream and k=0 to D−1. For N_D=4, 12, 20, and 28, N_D—idx is 0, 1, 2, and 3, respectively. In this condition, the addresses (j) are generated by the address generators 220, 222, and 224 as follows:

$\begin{array}{cc}j=R*P1\left[k+N_D\right)\%32]+\hspace{1em}\left[\frac{k+N_D}{32}\right]-\mathrm{Deint\_Perm}1\left[N_{D\_\mathrm{idx}}\right]\left[k\mathrm{\%32}\right]& \left[\mathrm{Equation}5\right]\end{array}$

wherein N_D=(R_subblock×C_subblock−D), R is a row value of the subblock deinterleavers 214, 216, and 218, and a%b indicates a residue obtained by dividing a by b. Further, P1[32]={0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30, 1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11, 27, 7, 23, 15, 31}.

Deint_Perm1[4][32]={1, 3, 2, 4, 1, 3, 2, 4, 1, 3, 2, 4, 1, 3, 2, 4, 1, 3, 2, 4, 1, 3, 2, 4, 1, 3, 2, 4, 1, 3, 2, 4, 3, 9, 6, 12, 1, 7, 4, 10, 3, 9, 6, 12, 2, 8, 5, 11, 3, 9, 6, 12, 1, 7, 4, 10, 3, 9, 6, 12, 2, 8, 5, 11, 4, 14, 9, 19, 3, 13, 8, 18, 5, 15, 10, 20, 1, 11, 6, 16, 4, 14, 9, 19, 3, 13, 8, 18, 5, 15, 10, 20, 2, 12, 7, 17, 7, 21, 14, 28, 1, 15, 8, 22, 5, 19, 12, 26, 3, 17, 10, 24, 7, 21, 14, 28, 2, 16, 9, 23, 6, 20, 13, 27, 4, 18, 11, 25}

Next, for i=2, d⁽ⁱ⁾k=v⁽ⁱ⁾k where the output after the bit separation is in the form of a bit stream and k=0 to D−1. For N_D=4, 12, 20, and 28, N_D—idx is 0, 1, 2, and 3, respectively. In this condition, the addresses (j) generated by the address generation units 220, 222, and 224 are obtained as follows:

$\begin{array}{cc}j=R*P1\left[k+N_D-1\right)\%32]+\hspace{1em}\left[\frac{k+N_D-1}{32}\right]-\mathrm{Deint\_Perm}2\left[N_{D\_\mathrm{idx}}\right]\left[k\mathrm{\%32}\right]& \left[\mathrm{Equation}6\right]\end{array}$

wherein N_D=(R_subblock×C_subblock−D), and R is a row value of the subblock deinterleavers 214, 216. Further, P1 [32]={0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30, 1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11, 27, 7, 23, 15, 31}.

Deint_Perm1[4][32]={3, 1, 3, 2, 3, 1, 3, 2, 3, 1, 3, 2, 3, 1, 3, 2, 3, 1, 3, 2, 3, 1, 3, 2, 3, 1, 3, 2, 3, 1, 3, 2, 10, 3, 9, 6, 11, 1, 7, 4, 10, 3, 9, 6, 11, 2, 8, 5, 10, 3, 9, 6, 11, 1, 7, 4, 10, 3, 9, 6, 11, 2, 8, 5, 16, 4, 14, 9, 18, 3, 13, 8, 17, 5, 15, 10, 19, 1, 11, 6, 16, 4, 14, 9, 18, 3, 13, 8, 17, 5, 15, 10, 19, 2, 12, 7, 24, 7, 21, 14, 27, 1, 15, 8, 22, 5, 19, 12, 25, 3, 17, 10, 24, 7, 21, 14, 27, 2, 16, 9, 23, 6, 20, 13, 26, 4, 18, 11}

As described above, in the derate matcher and method for processing data that is turbo coded and transmitted in the 3GPP LTE and LTE Advance systems, the present invention performs signal processing on a redundancy version number rv, resulting from the transmission of the dummy bits and HARQ created by the subblock interleavers based on the length of transmitted data, by a bit separation process using the memory address generators by having the parameters simplified by the decoder of the receiving end, and implements subblock deinterleavers to perform decoding without passing through the complex deinterleaving process, thereby reducing hardware processing time taken by the derate matcher of the receiving end and simplifying hardware implementation and control signal structure.

While the invention has been shown and described with respect to the embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.

Claims

1. A data derate matcher for supporting hybrid automatic repeat request (HARQ), comprising: a control parameter generation unit for generating control parameters to separate bits of an input bit stream ek;a bit separation unit for separating the bits of the input bit stream ek into three types of bits streams v(0)k, v(1)k, and v(2)k by modulus operation of each of the bits of the input bit stream and the control parameters;address generators for generating addresses (j) of valid data to be used in deinterleavers with respect to data of each of the bit streams output from the bit separation unit; andsubblock deinterleavers for sequentially inputting data corresponding to the addresses generated by the address generators to output decoded data.

2. The data derate matcher of claim 1, wherein, for the bit stream data of v(0)k and v(1)k, the address generators generate addresses (j) to specify the respective bit stream data using the following equation:

3. The data derate matcher of claim 2, wherein the matrix value of P1[32] for a dummy bit number of 32 is {0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30, 1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11, 27, 7, 23, 15, 31}.

4. The data derate matcher of claim 2, wherein the matrix value of Deint_Perm1[4][32] for a row value of 4 and a dummy bit number of 32 is {1, 3, 2, 4, 1, 3, 2, 4, 1, 3, 2, 4, 1, 3, 2, 4, 1, 3, 2, 4, 1, 3, 2, 4, 1, 3, 2, 4, 1, 3, 2, 4, 3, 9, 6, 12, 1, 7, 4, 10, 3, 9, 6, 12, 2, 8, 5, 11, 3, 9, 6, 12, 1, 7, 4, 10, 3, 9, 6, 12, 2, 8, 5, 11, 4, 14, 9, 19, 3, 13, 8, 18, 5, 15, 10, 20, 1, 11, 6, 16, 4, 14, 9, 19, 3, 13, 8, 18, 5, 15, 10, 20, 2, 12, 7, 17, 7, 21, 14, 28, 1, 15, 8, 22, 5, 19, 12, 26, 3, 17, 10, 24, 7, 21, 14, 28, 2, 16, 9, 23, 6, 20, 13, 27, 4, 18, 11, 25}.

5. The data derate matcher of claim 1, wherein, for the bit stream data of v(2)k, the corresponding address generator generates an address (j) to specify the bit stream data using the following equation:

6. The data derate matcher of claim 5, wherein the matrix value of P1[32] for a dummy bit number of 32 is {0, 16, 8, 24, 4, 20, 12, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30, 1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11, 27, 7, 23, 15, 31}.

7. The data derate matcher of claim 5, wherein the matrix value of Deint_Perm1[4][32] for a row value of 4 and a dummy bit number of 32 is {3, 1, 3, 2, 3, 1, 3, 2, 3, 1, 3, 2, 3, 1, 3, 2, 3, 1, 3, 2, 3, 1, 3, 2, 3, 1, 3, 2, 3, 1, 3, 2, 10, 3, 9, 6, 11, 1, 7, 4, 10, 3, 9, 6, 11, 2, 8, 5, 10, 3, 9, 6, 11, 1, 7, 4, 10, 3, 9, 6, 11, 2, 8, 5, 16, 4, 14, 9, 18, 3, 13, 8, 17, 5, 15, 10, 19, 1, 11, 6, 16, 4, 14, 9, 18, 3, 13, 8, 17, 5, 15, 10, 19, 2, 12, 7, 24, 7, 21, 14, 27, 1, 15, 8, 22, 5, 19, 12, 25, 3, 17, 10, 24, 7, 21, 14, 27, 2, 16, 9, 23, 6, 20, 13, 26, 4, 18, 11}.

8. The data derate matcher of claim 1, further including a buffer unit for storing each bit stream data output from the bit separation unit, the buffer unit being connected between the subblock deinterleavers and the bit separation unit.

9. The data derate matcher of claim 1, wherein the control parameter generation unit generates the control parameters including Kstart specifying a start position of the input bit stream and Kswitch specifying a switching point of the input bit stream.

10. The data derate matcher of claim 9, wherein, if the dummy bit number ND of the input bit stream has one of (4, 12, 20, 28) and a redundancy version (rv) value has one of (0, 1, 2, 3), the Kstart supports HARQ set in the following table:

11. The data derate matcher of claim 9, wherein, if the dummy bit number ND of the input bit stream has one of (4, 12, 20, 28), the Kswitch supports HARQ set in the following table:

12. The data derate matcher of claim 1, wherein the dummy bit number included in the input bit stream supports HARQ set as one of 4, 12, 20, and 28.

13. The data derate matcher of claim 1, wherein the input bit stream supports HARQ that is turbo coded data.

14. A data derate matching method in a data derate matcher for supporting hybrid automatic repeat request (HARQ), comprising: generating control parameters to separate bits of an input bit stream ek;separating the bits of the input bit stream ek into three types of bits streams v(0)k, v(1)k, and v(2)k by modulus operation of each of the bits of the input bit stream and the control parameters;generating addresses (j) of valid data to be used in deinterleavers with respect to data of each of the separated bit streams v(0)k, v(1)k, and v(2)k; andsequentially inputting data corresponding to the generated addresses among the respective bit stream data to output decoded data.

15. The data derate matching method of claim 14, wherein, for the bit stream data of v(0)k and v(1)k, said generating addresses (j) generates addresses (j) to specify the respective bit stream data using the following equation:

16. The data derate matching method of claim 14, wherein, for the bit stream data of v(2)k, said generating addresses (j) generates an address (j) to specify the bit stream data using the following equation:

17. The data derate matching method of claim 14, wherein the control parameters include Kstart specifying a start position of the input bit stream and Kswitch specifying a switching point of the input bit stream.

18. The data derate matching method of claim 17, wherein, if the dummy bit number ND of the input bit stream has one of (4, 12, 20, 28) and a redundancy version (rv) value has one of (0, 1, 2, 3), the Kstart supports HARQ set in the following table:

19. The data derate matching method of claim 17, wherein, if the dummy bit number ND of the input bit stream has one of (4, 12, 20, 28), the Kswitch supports HARQ set in the following table:

20. The data derate matching method of claim 14, wherein the input bit stream is turbo coded data.