Claims
- 1. A data distribution system for a network of multi-processors, wherein each of the multi-processors includes, a memory for storage of data, the data being accessed by an address, the system comprising:
- (a) an address/data bus interconnected to the memories of the multi-processors; and
- (b) data distribution means for routing data to one or more of the memories of the multi-processors without the multi-processors requesting data, said address/data bus being interconnected to said data distribution means, said data distribution means including:
- (1) means for generating address information along said address/data bus for simultaneous transmission to each of the memories for data access;
- (2) means for generating a memory select signal to each of the memories for selecting one of the memories for data access at a selected address; and
- (3) means for generating a read/write signal to each of the memories for selecting one or more memories to which data is to be transferred from said address/data bus selected by said address generating means and said memory select means to thereby write data simultaneously to one or more memories of the multi-processors at a selected address.
- 2. A multi-processor apparatus comprising:
- (a) a plurality of processors;
- (b) each of said processors including a memory having an address means, read/write activation means, and memory activation means;
- (c) address bus means connecting said address means of each of said memories;
- (d) multi-processor data distribution means for routing data to one or more of said memories of said processors without said processors requesting data including:
- (1) address output means connected to said address bus means for simultaneously sending addresses to all of said plurality of processors;
- (2) a plurality of memory select signal output means, one of said plurality of memory select signal output means being connected to one of said plurality of processors; and
- (3) a plurality of read/write signal output means, one of said plurality of read/write signal output means being connected to one of said plurality of processors; and
- (e) interconnection means for connecting said read/write activation means and said memory activation means of each of said memories to selected ones of said read/write signal output means and said memory select signal output means, such that activation signals can be applied simultaneously to a plurality of said memories.
- 3. A method of re-distributing data between a memory section of one processor of a commonly addressed group of N processors, each having a memory section, and a selectable subgroup of M processors each having a memory section comprising, the steps of:
- (a) selectively addressing a given memory section of a given processor in the group of N processors by supplying individual read activation and memory activation signals to only the given memory section while supplying a common address set of signals to all memory sections of the N processors to retrieve given data; and
- (b) addressing memory sections of the plurality of M processors by supplying individual write activation and memory activation signals to only the memory sections of the M processors while supplying a common address set of signals to all memory sections of the N processors to simultaneously write the given data previously retrieved from the memory sections of the N processors to all memory sections of the M processors without the M processors requesting data.
Parent Case Info
This application is a continuation of application Ser. No. 08/234,658, filed Apr. 28, 1994, now abandoned.
US Referenced Citations (10)
Continuations (1)
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Number |
Date |
Country |
Parent |
234658 |
Apr 1994 |
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