Patent Application
20060176812
This nonprovisional application is based on Japanese Patent Application No. 2005-031427 filed with the Japan Patent Office on Feb. 8, 2005, the entire contents of which are hereby incorporated by reference.
The present invention relates to a data-driven-type information processor capable of parallel processing by performing operational processing along with input/output of a data packet, and more particularly to a data-driven-type information processor capable of efficient and high-speed operational processing by outputting a data packet to be processed at a constant interval or at a designated interval as well as to a method of controlling the same.
Recently, improvement in processor performance has increasingly been demanded in various fields, such as multimedia processing or high-definition image processing in which high-speed processing of a large amount of data is demanded. In current LSI (Large Scale Integrated circuit) manufacturing technology, however, a speed of a device is limited. Under such circumstances, parallel processing has attracted attention, and research and development for the same has vigorously been conducted.
In particular, a data-driven-type architecture has attracted attention among computer architectures suitable for parallel processing. In a data-driven-type processing scheme, the processing proceeds in parallel under the rule that “the processing is performed when all input data necessary for certain processing are available and resources such as an operation unit necessary for that processing are allocated.”
Merge unit 116 rearranges data packets input through a data packet input portion 118 in a prescribed order and sends them to program storage unit 111. Program storage unit 111 adds a necessary operation instruction and a node number to the data packet received from merge unit 116, generates a data packet constituted of prescribed bit fields, and sends the data packet to queue unit 112.
Upon receiving the data packet from program storage unit 111, queue unit 112 waits until two data packets to be operated are ready. As soon as the data packets are ready, the data packets are sent to operational processing unit 113.
Operational processing unit 113 performs operation such as arithmetic operation or logical operation on data included in the two data packets, in response to an operation instruction included in the data packet received from queue unit 112. Thereafter, operational processing unit 113 causes a result of operation to be stored in the data packet provided with a destination node number, and sends the data packet to branch unit 114.
Branch unit 114 determines the destination in accordance with the destination node number added to the data packet received from operational processing unit 113, and distributes the data packets. Specifically, if the data packet is directed to another data-driven-type information processor, the data packet is sent through a data packet output portion 119. Alternatively, the data packet is directed to its own data-driven-type information processor, the data packet is sent to merge unit 116 through a pipeline 115.
The invention disclosed in Japanese Patent Laying-Open No. 2002-189710 relates to the above-described technique.
Delay instruction processing block 127 is connected to go-around pipeline 117 coming from merge unit 116 shown in
Upon receiving a data packet containing a delay instruction, instruction fetch unit 122 sends delay time data representing a parameter of the delay instruction to delay instruction processing unit 125, along with a data packet containing an instruction that is fetched subsequent to the delay instruction.
Memory 123 for delay token storage stores the instruction fetched subsequent to the delay instruction. In addition, timer 124 for delay processing counts a delay time based on the delay time data. Delay instruction processing unit 125 takes out the instruction from memory 123 for delay token storage after the delay time counted by timer 124 for delay processing has elapsed, and sends the instruction to go-around pipeline 117. In this manner, the data packet containing the instruction that is fetched subsequent to the delay instruction is delayed by a prescribed time, so that the number of data packets transmitted simultaneously to go-around pipeline 117 can be reduced and overflow on go-around pipeline 117 can be avoided.
The static analysis in the flow graph described above assumes that the data packet goes around the data-driven-type information processor at a constant interval. On the other hand, variation due to various factors takes place, with regard to an actual interval of output of data packets within the data-driven-type information processor. The factors in variation in the output interval include deviation in timing of output due to micro time difference during waiting of data packets, disturbance in the flow of the data packets caused by change in an operation of the data packet due to conditional branching in the data flow graph, variation in the interval of output of the data packets caused by duplication or disappearance of the data packet, and the like.
Variation in the output interval in terms of time causes no problem, provided that it can be accommodated in processing capability of the data-driven-type information processor. In many cases, however, the data-driven-type information processor is operated around its processing performance limit. In such a case, if variation is significant, the number of data packets on the pipeline instantaneously increases and the processing capability of the data-driven-type information processor is exceeded, which results in suspension of the data-driven-type information processor.
In order to avoid such a situation, software is generally designed such that some margin is secured for maximum processing performance of the data-driven-type information processor in static analysis of the flow graph. With such design, however, the processing performance of the data-driven-type information processor cannot sufficiently be utilized, and performance has been made poorer.
An object of the present invention is to provide a data-driven-type information processor allowing software design in which margin is reduced almost to the limit of processing performance.
According to one aspect of the present invention, a data-driven-type information processor performing operational processing along with input/output of a data packet includes: a control unit determining a waiting time required for the data packet when the data packet is included in a data packet group of which output at a prescribed interval is demanded and outputting the data packet when the waiting time has elapsed; and an operational processing unit performing operational processing in response to an operation instruction included in the data packet.
Accordingly, variation in an amount of processing of the data packet within the data-driven-type information processor is reduced, and software design in which margin is reduced almost to the limit of processing performance can be made.
Preferably, the control unit includes a branch unit determining whether the data packet is included in the data packet group of which output at the prescribed interval is demanded and distributing the data packet in accordance with a result of determination, an acquiring unit acquiring historical information of another data packet included in the data packet group when the data packet is included in the data packet group of which output at the prescribed interval is demanded and determining a waiting time of the data packet, a storage unit storing the waiting time determined by the acquiring unit, an output portion outputting the data packet when the waiting time stored in the storage unit has elapsed, and a merge unit causing the data packet that has been determined by the branch unit as not included in the data packet group of which output at the prescribed interval is demanded, the data packet that has been determined by the acquiring unit as not having to wait, and the data packet output from the output portion, to merge.
When the data packet is included in the data packet group of which output at the prescribed interval is demanded, the acquiring unit acquires the historical information of another data packet included in the data packet group and determines a waiting time of the data packet. Therefore, the data packet included in the data packet group can accurately be output at a prescribed interval.
Preferably, the data packet group refers to a plurality of data packets containing identical destination information.
Accordingly, whether or not the data packet is included in the data packet group can readily be determined by referring to the destination information of the data packet.
Preferably, the branch unit holds in a register, the destination information included in a data packet containing a prescribed instruction, and determines whether the data packet is included in the data packet group, based on whether the destination information of the data packet is identical to the destination information held in the register.
Accordingly, setting of the data packet group can readily be made.
Preferably, the prescribed interval is included in the data packet containing the prescribed instruction.
Therefore, the interval can readily be changed.
Preferably, the prescribed interval is a constant interval.
Therefore, an effort for setting the interval can be obviated.
Preferably, if there are a plurality of data packet groups, the output portion outputs the plurality of data packet groups in a prescribed order.
Therefore, execution of the instruction, for which the order of arrival of the data has been determined, can readily be performed.
Preferably, the output portion outputs data packets included in the data packet group sequentially from a data packet having a smaller generation number.
Therefore, the order of execution of the instruction can readily be controlled.
Preferably, the data packet includes a flag indicative of whether the data packet is included in the data packet group of which output at the prescribed interval is demanded. The acquiring unit determines whether the data packet is included in the data packet group of which output at the prescribed interval is demanded, by referring to the flag.
Therefore, determination can readily be made.
According to another aspect of the present invention, a method of controlling a data-driven-type information processor performing operational processing along with input/output of a data packet includes the steps of: determining a waiting time required for the data packet when the data packet is included in a data packet group of which output at a prescribed interval is demanded and outputting the data packet when the waiting time has elapsed; and performing operational processing in response to an operation instruction included in the data packet.
Preferably, the step of determining a waiting time and outputting the data packet includes the steps of: determining whether the data packet is included in the data packet group of which output at the prescribed interval is demanded and distributing the data packet in accordance with a result of determination, acquiring historical information of another data packet included in the data packet group when the data packet is included in the data packet group of which output at the prescribed interval is demanded and determining a waiting time of the data packet, storing the determined waiting time, outputting the data packet when the stored waiting time has elapsed, and causing the data packet that has been determined as not included in the data packet group of which output at the prescribed interval is demanded, the data packet that has been determined as not having to wait, and the output data packet, to merge.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
Merge unit 16 rearranges data packets input through a data packet input portion 18 in a prescribed order and sends them to program storage unit 11. Program storage unit 11 adds a necessary operation instruction and a node number to the data packet received from merge unit 16, generates a data packet constituted of prescribed bit fields, and sends the data packet to packet control unit 20.
Packet control unit 20 changes an interval of output of the data packet, and sends the data packet to queue unit 12. Upon receiving the data packet from packet control unit 20, queue unit 12 waits until two data packets to be operated are ready. As soon as the data packets are ready, the data packets are sent to operational processing unit 13.
Operational processing unit 13 performs operation such as arithmetic operation or logical operation on data included in the two data packets, in response to an operation instruction included in the data packet received from queue unit 12. Thereafter, operational processing unit 13 causes a result of operation to be stored in the data packet provided with a destination node number, and sends the data packet to branch unit 14.
Branch unit 14 determines the destination in accordance with the destination node number added to the data packet received from operational processing unit 13 and distributes the data packets. Specifically, if the data packet is directed to another data-driven-type information processor, the data packet is sent through a data packet output portion 19. Alternatively, if the data packet is directed to its own data-driven-type information processor, the data packet is sent to merge unit 16 through a pipeline 15.
Though packet control unit 20 is provided between program storage unit 11 and queue unit 12 in
Instruction code 31 represents a field in which an instruction executed in operational processing unit 13 of the data-driven-type information processor shown in
Generation number 33 is provided for each set of data packets for which operation is performed, and it is provided for distinction between different operations even though the destination is the same. In data 34, a data value that actually goes around is stored.
Now consider a flow graph shown in
Accordingly, if the data packets, of which generation number 33 is incremented one by one, are input, the data packets are output alternately to the TRUE side and the FALSE side for each data packet. The data packet output to the FALSE side disappears, while the data packet output to the TRUE side flows to NOP 42. Namely, every other data packet among the input data packets flows to NOP 42.
Thereafter, at the output of NOP 42, the data packet is duplicated. Of these data packets resulted from duplication, with regard to the data packet that flows to ADDGEN (right input data value=0) 43, 0 is added to the value for generation number 33, that is, the data packet is output as it is. Meanwhile, with regard to the data packet that flows to ADDGEN (right input data value=1) 44, the data packet in which 1 is added to the value for generation number 33 is output. These data packets merge at NOP 45, and ultimately, the data packets are output as the data packet group in which respective data packets have generation numbers 33 incremented one by one, as in the case at the time of input.
In
If the output interval of the data packet is set as shown in
In the embodiment of the present invention, the node number of NOP instruction node 45 shown in
Data packet branch unit 21 determines whether the data packet output from program storage unit 11 includes register set instruction 46 or not. If the data packet includes the register set instruction, data packet branch unit 21 stores in an internal register, destination information of the data packet, that is, the value for node number 32, as well as the data output interval value, that is, the value for data 34.
In actual processing, data packets flow from an input Q at a constant interval. When the data packets that flow through an output E of ADDGEN 43 and through an output F of ADDGEN 44 are input to data packet branch unit 21, data packet branch unit 21 compares the value in the internal register with node number 32 of the data packet. If these packets are directed to NOP instruction 45, the data packets are allowed to flow to data packet status acquiring unit 22. Data packet branch unit 21 causes other data packets to flow to data packet merge unit 27 and outputs the data packets to the outside.
Upon receiving the data packet through output E of ADDGEN 43, data packet branch unit 21 causes the data packet to flow to data packet status acquiring unit 22. Data packet status acquiring unit 22 acquires information on whether a data packet having the node number the same as that data packet has been stored in data memory 23, or had been stored or had passed several clocks before.
Data memory 23 includes a data packet waiting time table and a data packet queue.
Data packet status acquiring unit 22 acquires the data packet waiting time to be stored in the data packet waiting time table, using the node number of the data packet as the address. The data packet waiting time indicates how long the data packet having that node number should wait in data memory 23. Though clock is used as a unit herein, any unit of time may be employed.
For example, if the data packet waiting time is set to 0, it is not necessary to store the data packet in data memory 23. Therefore, data packet status acquiring unit 22 outputs the data packet as it is to data packet merge unit 27. In addition, data packet status acquiring unit 22 acquires the data packet waiting time from the data packet waiting time table, using the node number of the data packet output to data packet merge unit 27 as the address, and adds the value of the data output interval to the data packet waiting time, so as to rewrite the value in the data packet waiting time table.
If the data packet waiting time is not set to 0, data packet status acquiring unit 22 stores the data packet content in the data packet queue, along with the data packet waiting time at that time. As the data packet is stored in the data packet queue, the value of the data packet waiting time is acquired by using the node number of that data packet as the address, and the data packet waiting time is rewritten with the value obtained by adding the data output interval value stored in the register.
Immediately after the data packet of output E of ADDGEN 43 in
Upon receiving the data packet of output F of ADDGEN 44, data packet branch unit 21 outputs the data packet to data packet status acquiring unit 22, because this data packet is directed to NOP instruction node 45. Data packet status acquiring unit 22 acquires information on whether a data packet having the node number the same as the data packet is currently stored, or has been stored or has passed several clocks before, by referring to data memory 23.
Specifically, data packet status acquiring unit 22 acquires the data packet waiting time from the data packet waiting time table within data memory 23, using the node number of the data packet as the address. In this case, the data packet of output E of ADDGEN 43 has passed immediately before, which means that the data packet waiting time for a period of n clocks has passed, namely, it is set to (data output interval value−n). The data packet and this value flow to data memory 23. Here, n clocks indicate the minimum interval resulted from the duplication operation.
Thereafter, data packet status acquiring unit 22 stores the value of (data output interval value−n) as the data packet waiting time in the data packet queue within data memory 23, and simultaneously also stores the data packet content.
Clock generation unit 24 constantly generates clocks, and supplies the clocks to waiting time decrementer 25. Here, any clock width may be set.
Waiting time decrementer 25 decrements all values in the data packet waiting time table in data memory 23, using the clock supplied from clock generation unit 24 as a trigger.
Similarly, waiting time decrementer 25 also decrements all values in the data packet waiting time in the data packet queue. In the data packet queue, if the value obtained as a result of decrement is 0, that address is transferred to output data packet generation unit 26.
Output data packet generation unit 26 reads the data packet content from the data packet queue, in accordance with the address transferred from the data packet queue. Then, output data packet generation unit 26 transfers the data packet content to data packet merge unit 27 as well as erases the data packet waiting time and the data packet content from the data packet queue.
Data packet merge unit 27 causes the data packets from data packet branch unit 21, data packet status acquiring unit 22 and output data packet generation unit 26 to merge, and outputs the resultant data packet.
In
Similarly, the interval between the data packet of output F of ADDGEN 44 and the data packet of output E of ADDGEN 43 having next generation number 33 is also set to the data output interval value. In this manner, the output interval of the data packet becomes constant.
The description above has been directed to an example in which a single register set instruction is used, however, the register set instruction may be used at a plurality of locations. In such a case, a plurality of node numbers are designated by a plurality of register set instructions. Here, the plurality of register set instructions may be ordered, so that the data packets having the same generation number can be output in a prescribed order. For example, even if data packet waiting time in the data packet queue is set to 0, output of the data packet is withheld until the data packet having a prescribed node number arrives. After the data packet having the prescribed node number arrives and a prescribed time has elapsed since output thereof, the data packet that has been waiting is output.
It is naturally permitted to output the data packet, regardless of the node number, at a time point when the data packet waiting time in the data packet queue attains to 0, without ordering the plurality of register set instructions.
Alternatively, if there is another data packet having the same destination information as a result of search in the data packet queue at a time point when the data packet waiting time in the data packet queue attains to 0, the data packet having the smallest generation number among the data packets having the same destination information may be replaced with the data packet of which data packet waiting time attains to 0, whereby the data packet having the smallest generation number is output. In this case, the value for the data packet waiting time of the data packet having the smallest generation number is set as the waiting time of the data packet of which data packet waiting time has attained to 0.
As the data output interval value is set in data 34 of the data packet input to the register set instruction, the data output interval value may be set to a different value, so as to output the data packet at a different output interval.
Alternatively, the lowest order bit of instruction code 31 may be set as a flag field for determination of a condition, so that data packet branch unit 21 outputs the data packet to data packet status acquiring unit 22 only when the flag is set to 1.
Alternatively, data packet branch unit 21 shown in
Packet control unit 20 may be provided within operational processing unit 13. In this case, data packet branch unit 21 decodes instruction code 31, and if the instruction is an instruction to remain for a certain period of time, data packet branch unit 21 outputs the data packet to data packet status acquiring unit 22.
As described above, in the data-driven-type information processor in the embodiment of the present invention, the data packet waiting time is determined such that the data packet group having the same destination information is output at a prescribed interval, the data packet waiting time is stored in the data packet queue along with the data packet content, and output data packet generation unit 26 outputs the data packet content when the data packet waiting time is decremented to 0. Therefore, variation in the amount of processing of the data packet within the data-driven-type information processor is reduced, software design in which margin is reduced almost to the limit of processing performance of the data-driven-type information processor even in static analysis can be made, and the processing performance of the data-driven-type information processor can be improved.
Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2005-031427 | Feb 2005 | JP | national |
