Patent Grant
10600369
This application claims the benefit of Korea Patent Application No. 10-2017-0083711 filed on Jun. 30, 2017, the entire contents of which is incorporated herein by reference for all purposes as if fully set forth herein.
The present disclosure relates to an active-matrix organic light emitting display device.
An active matrix-type electroluminescent display device includes a self-emitting Organic Light Emitting Diode (OLED), and has advantages of a fast response time, a high light emitting efficiency, high luminance, and a wide viewing angle.
An OLED serving as a self-emitting element includes an anode electrode, a cathode electrode, and an organic compound layer formed between the anode electrode and the cathode electrode. The organic compound layer includes a hole injection layer HIL, a hole transport layer HTL, a light emitting layer EML, an electron transport layer ETL, and an electron injection layer EIL. When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the light emitting layer EML and form excitons. As a result, the light emitting layer EML generates visible light.
The organic light emitting display device includes a driving Thin Film Transistor (TFT) to control a driving current flowing in an OLED. It is desirable that the driving TFT is designed to have the same electrical characteristics, such as a threshold voltage and mobility, at each pixel. However, the electrical characteristics are not uniform at each pixel due to process condition and driving environment. For this reason, a driving current according to the same data voltage is different at each pixel, and this leads to differences in brightness between pixels. To solve this problem, there is an image quality compensation technology for sensing a characteristic parameter (threshold, mobility) of a driving TFT in each pixel and properly compensating for input data based on a sensing result in order to reduce non-uniformness of brightness.
An internal compensation method of the image quality compensation technology is to control a pixel structure and an operational timing in order to eliminate the influence of the electronic characteristics of a driving TFT while an organic light emitting diode emits light. Basically, the internal compensation method is to perform a sampling in which a gate voltage of a driving TFT is increased in a source follower method to be saturated at a predetermined level. To saturate the gate voltage of a driving TFT at the predetermined level, a sufficiently long time is required. However, as display panels tends to have a large screen and a high resolution, a time for sampling one pixel line is reduced, and thus, the sampling operation cannot be performed smoothly.
According to an embodiment, a data driver for an OLED is provided. The data driver includes: an input unit configured to receive an input data; a compensation data generator configured to generate a compensation data by applying a compensation value to the input data; a converter unit configured to convert the input data into an image data voltage and to convert the compensation data into a compensation data voltage; and an output unit configured to separately output the image data voltage and the compensation data voltage to a data line of the organic light emitting display.
According to another embodiment, an OLED device including the data driver according to the embodiment of the disclosure is provided.
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure. In the drawings:
Reference will now be made in detail to embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. Detailed description of known arts will be omitted if it is determined that the arts can mislead the embodiments of the disclosure.
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.
Referring to
A plurality of data lines 14 and a plurality of gate lines 15 are intersecting one another on the display panel 10, and pixels P are arranged at the intersections in a matrix form. Each of the pixels P are supplied with a high-potential driving voltage VDD and a low-potential driving voltage VSS from a power generator that is not shown in the drawings.
Based on timing signals, such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE, the timing controller 11 generates a data control signal DDC for controlling an operation timing of the data driver 12 and a gate control signal GDC for controlling an operation timing of the gate driver 13.
In addition, the timing controller 11 includes a compensation value setting unit 100. The compensation value setting unit 100 calculates a magnification of a compensation data voltage output from the data driver 12. The compensation data voltage is for over driving in a procedure of sensing a threshold voltage of a driving Thin Film Transistor (TFT) during a sensing period, and detailed description thereof will be provided later.
During a compensation period, the data driver 12 supplies a sensing data voltage to the pixels P, converts a sensing voltage received from the display panel 10 through the data lines 14 into a digital value, and supplies the digital value to the timing controller 11. During an image display period, the data driver 12 supplies an image display data voltage to the data lines 14.
The gate driver 13 may generate a gate signal based on a gate control signal GDC from the timing controller 11, and the gate signal may include scan signals and an emission signal. Depending on a pixel structure, the gate signal may different and timings of a gate signal applied during the compensation period and a gate signal applied during the image display period are different. The gate driver 13 may be formed directly on the display panel 10 through a Gate-driver In Panel (GIP) process.
Referring to
In response to a gate signal supplied through a first gate line GL, the switching transistor SW performs a switching operation so that a data signal supplied through a first data line DL is stored as a data voltage in a capacitor. Dependent upon the data voltage stored in the capacitor, the driving TFT DT operates to cause a driving current to flow between a high-potential power line VDD and a low-potential power line GND. The compensation circuit CC is a circuit for compensation of a threshold voltage of the driving TFT DT. In addition, the capacitor connected to the switching transistor SW or the driving TFT DT may be located inside of the compensation circuit CC.
The compensation circuit CC includes one or more thin film transistors (TFTs) and a capacitor. Configuration of the compensation circuit CC may vary depending on a compensation method, and detailed examples and description thereof are herein omitted.
In addition, as illustrated in
Referring to
Based on its source-gate voltage Vsg, the driving TFT DT controls a driving current which is to be applied to the OLED. The driving TFT DT includes a gate electrode connected to a first node N1, a source electrode connected to a third node N3, and a drain electrode connected to a second node N2. In response to the n-th scan signal SCAN(n), the first transistor T1 connects the first node N1 and the second node N2. In response to the n-th scan signal SCAN(n), the second transistor T2 connects a data line 14 and the third node N3. In response to the n-th emission signal EM(n), the third transistor T3 connects the third node N3 and an input terminal of the high-potential driving voltage VDD. In response to the n-th emission signal EM(n), the fourth transistor T4 connects the second node N2 and the fourth node N4. In response to a (n−1)-th scan signal SCAN(n−1), the fifth transistor T5 connects the first node N1 and an input terminal of the initialization voltage Vinit. In response to the n-th scan signal SCAN(n), the sixth transistor T6 connects the input terminal of the initialization voltage Vinit and the fourth node N4. In addition, the storage capacitor Cst is connected between the first node N1 and the input terminal of the high-potential driving voltage VDD.
In an initialization period Ti, the fifth transistor T5 connects the first node N1 and the input terminal of the initialization voltage Vinit in response to the (n−1)-th scan signal SCAN(n−1). As a result, the first node N1 is initialized to the initialization voltage Vinit. The initialization voltage Vinit may be selected within a voltage range lower than an operation voltage of the OLED, and may be set equal to or lower than the low-potential driving voltage VSS.
In a sampling period Ts, the first transistor T1, the second transistor T2, and the sixth transistor T6 are turned on in response to the n-th scan signal SCAN(n). As a result, the first transistor T1 establishes diode-connection between the first node N1 and the second node N2. The second transistor T2 charges the third node N3 to a data voltage Vdata supplied through the data line DL. The sixth transistor T6 charges the fourth node N4 to the initialization voltage Vinit.
In the sampling period Ts, a current is flowing between the source electrode and the drain electrode of the driving TFT DT, and accordingly, a voltage of the second node N2 becomes Vdata(n)−|Vth| which indicates a value obtained by subtracting an absolute value of a threshold voltage Vth of the driving TFT DT from the data voltage Vdata. The first node N1 becomes to have the same voltage as that of the second node N2.
In an emission period Te, the third transistor T3 supplies the high-potential driving voltage VDD to the third node N3 in response to the n-th emission signal EM(n). The fourth transistor T4 is turned on to connect the second node N2 and the fourth node N4. In the emission period Te, a current bypassing from the third node N3 to the second node N2 is generated due to a set gate-source voltage of the driving TFT DT.
The current IOLED flowing in the OLED in the emission period Te may be represented by Equation 1, as below.
IOLED=k/2(Vgs−Vth)2=k/2(Vg−Vs−Vth)2=k/2{(Vdata−|Vth|)−VDD−Vth)}2 Equation 1
At this point, Vth<0, and thus, Equation 1 can be summarized in “k/2(Vdata−VDD)2”.
In Equation 1, k/2 denotes a proportionality constant which is determined by electron mobility of the driving TFT DT, a parasitic capacitance, and a channel capacity. During the emission period Te, the driving current flowing in the OLED is not affected by the threshold voltage Vth of the driving TFT DT.
To rule out any possibility of influence by the threshold voltage Vth of the driving TFT DT in operation of an internal compensation circuit during the emission period Te, the first node should be sufficiently saturated at a value of Vdata−|Vth|.
However, as resolution of the display panel 10 increases, one horizontal period 1H for driving one pixel line is reduced and accordingly, even a sampling period Ts is reduced as well. As illustrated in
The compensation value setting unit 100 and the data driver 12 according to the present disclosure are capable of more accurately sampling a threshold voltage of a driving TFT within a short sampling period. Description thereof is provided in the following.
The timing controller 11 sets a compensation value a which is used to generate a compensation data voltage. The compensation value a may be calculated as a value that is a ratio of a voltage Vsam charged to the first node N1 in a sampling period of one horizontal period 1H relative to a voltage value Vsat at which the first node N1 is saturated when a long enough sampling period Ts is given. That is, the compensation value a is calculated into “Vsat/Vsam”. The voltage Vsam changed in the first node N1 during the first horizontal period 1H is equal to or smaller than the voltage value Vsat at which the first node N1 is saturated, and thus, the compensation value a is greater than 1. The compensation value a may be set identical or different for each gray level.
Referring to
The first latch Latch1 samples and latches digital image data Data received from the timing controller 11, and simultaneously outputs all the latched data. The second latch Latch2 latches image data Data received from the first latch Latch1, and simultaneously output all the latched image data in sync with second latches Latch2 of other source drivers.
In response to a first control signal S1, the first switch SW1 connects the second Latch2 and the first digital-to-analog converter DAC1.
The first digital-to-analog converter DAC1 converts the image data Data received from the second latch Latch2 into an analog data voltage Vdata.
The compensation data generator 120 generates compensation data Mdata by applying a compensation value a to the data received from the first latch Latch1. The compensation data Mdata may be generated as data is multiplied by the compensation value a. The compensation data generator 120 outputs the compensation data Mdata to the first compensation latch MLatch1.
The first compensation latch MLatch1 samples and latches the compensation data Mdata received from the compensation data generator 120, and simultaneously outputs all the latched data.
The second compensation latch MLatch2 latches the compensation data Mdata received from the first compensation latch MLatch1, and simultaneously outputs all the latched compensation data in sync with second compensation latches MLatch2 of other source drivers.
In response to a second control signal S2, the second switch SW2 may connect the second compensation latch MLatch2 and the second digital-to-analog converter DAC2.
The second digital-to-analog converter DAC2 converts the compensation data Mdata received from the second compensation latch MLatch2 into an analog compensation data voltage MVdata.
An output buffer BF provides the data line DL with the data voltage Vdata from the first digital-to-analog converter DAC1 or the compensation data voltage MVdata from the second digital-to-analog converter DAC2.
With reference to
In an initialization period Ti, the fifth transistor T5 connects the first node N1 and the input terminal of the initialization voltage Vinit in response to the (n−1)-th scan signal SCAN(n−1). As a result, the first node N1 is initialized to the initialization voltage Vinit. The initialization voltage Vinit may be selected within a voltage range lower than an operation voltage of the OLED, and may be set equal to or lower than the low-potential driving voltage VSS.
In first and second sampling periods Ts1 and Ts2, the first transistor T1, the second transistor T2, and the sixth transistor T6 are turned on in response to the n-th scan signal SCAN(n). As a result, the first transistor T1 establishes diode-connection between the first node N1 and the second node N2.
During the first sampling period Ts1, the second control signal S2 becomes a turn-on voltage. As a result, the second digital-to-analog converter DAC2 receives compensation data Mdata from the second compensation latch MLatch2, and generates a compensation data voltage MVdata. During the first sampling period Ts1, the output buffer BF outputs the compensation data voltage MVdata to the data line DL.
The second transistor T2 charges the third node N3 to a data voltage Vdata supplied through the data line DL. The compensation data voltage MVdata has a value greater than the data voltage VData, and thus, the third node N3 is charged to a value greater than the data voltage Vdata during the first sampling period Ts1. As a result, due to over driving effects, the voltage of the first node N1 in the first sampling period Ts1 has a value greater than the data voltage Vdata charged to the third node N3.
During the second sampling period Ts2, the second control signal S2 becomes a turn-off voltage and the first control signal S1 becomes a turn-on voltage. As a result, the first digital-to-analog converter DAC1 receives image data from the first latch Latch1, and generates an image data voltage VData. During the second sampling period Ts2, the output unit BF outputs the image data voltage VData to the data line.
The second transistor T2 charges the third node N3 to the data voltage supplied through the data line DL. The image data voltage VData has a value smaller than the compensation data voltage MVdata, and thus, the speed of charging the first node N1 to a voltage is reduced during the second sampling period Ts2. In particular, as the image data voltage VData is a voltage corresponding to the image data Data received by the timing controller 11, the first node N1 may be accurately sampled after the second sampling period Ts2 to a voltage having a value Vdata−|Vth| which corresponds to a desired gray level.
In the emission period Te, a current bypassing from the third node N3 to the second node N2 is generated due to a set gate-source voltage of the driving TFT DT, and the OLED emits light of a desired gray level.
As described above, the data driver 12 according to the present disclosure performs a sampling operation during a first sampling period Ts1 by using a compensation data voltage MVdata to which a compensation value a is applied, and therefore, the sampling operation may be performed fast. Accordingly, although one horizontal period 1H is reduced, a gate-source voltage of the driving TFT DT may be sampled during a sampling period to the voltage Vsat having an accurate value which reflects a threshold voltage. That is, if one horizontal period 1H is reduced, the first node N1 is charged to a voltage level of Vsam during the sampling period Ts1 and Ts2, and thus, the sampling operation may be performed inaccurately. However, according to the present disclosure, due to over driving of the first sampling period Ts1, it is possible to sample a voltage of the first node N1 to a voltage Vsat having an accurate value which reflects the threshold voltage of the driving TFT DT
In particular, the present disclosure is expected to have an over-driving effect without increasing a driving frequency. Thus, if sampling is performed simply by increasing a data voltage, a voltage value to be sampled may exceed a desired level. To prevent this problem, a data voltage to be applied in a sampling period needs to be controlled at a level corresponding to input image data. However, a pulse width length of a scan signal which determines a sampling period in an organic light emitting display device corresponds to one horizontal period at minimum, and thus, it is necessary to increase a driving frequency in order to perform sampling twice.
On contrary, the present disclosure is implemented such that the data driver 12 separately output, within one horizontal period 1H, an image data voltage Vdata of image data Data, and a compensation data voltage MVdata in which a compensation value a is reflected. Accordingly, it is possible to perform overdriving without increasing a driving frequency and varying a timing of a scan signal.
Referring to
Referring to
As such, in the third embodiment, it is possible to selectively generate between an image data voltage Vdata or a compensation data voltage MVdata and output the selected voltage by using one digital-to-analog converter DAC.
Each of the latch unit and the compensation latch unit shown in
Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2017-0083711 | Jun 2017 | KR | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 7339511 | Son | Mar 2008 | B2 |
| 20070030192 | Son | Feb 2007 | A1 |
| 20070120780 | Park | May 2007 | A1 |
| 20070263121 | Take et al. | Nov 2007 | A1 |
| 20080238953 | Ogura | Oct 2008 | A1 |
| 20080252568 | Kwon | Oct 2008 | A1 |
| 20080252569 | Kwon | Oct 2008 | A1 |
| 20090027423 | Kwon | Jan 2009 | A1 |
| 20090051628 | Kwon | Feb 2009 | A1 |
| 20090058772 | Lee | Mar 2009 | A1 |
| 20090184901 | Kwon | Jul 2009 | A1 |
| 20090184903 | Kwon | Jul 2009 | A1 |
| 20100182349 | Miyazaki | Jul 2010 | A1 |
| 20100253608 | Kim | Oct 2010 | A1 |
| 20100321367 | Shona | Dec 2010 | A1 |
| 20110007067 | Ryu | Jan 2011 | A1 |
| 20110018858 | Ryu | Jan 2011 | A1 |
| 20110032281 | Ietomi | Feb 2011 | A1 |
| 20110063283 | Ryu | Mar 2011 | A1 |
| 20110157134 | Ogura | Jun 2011 | A1 |
| 20110205250 | Yoo | Aug 2011 | A1 |
| 20110210958 | Yoo | Sep 2011 | A1 |
| 20110221727 | Kim et al. | Sep 2011 | A1 |
| 20130083087 | Byun et al. | Apr 2013 | A1 |
| 20130321497 | Kang | Dec 2013 | A1 |
| 20140118410 | Oh | May 2014 | A1 |
| 20140347253 | Lee | Nov 2014 | A1 |
| 20150002502 | Kim | Jan 2015 | A1 |
| 20160042695 | Park | Feb 2016 | A1 |
| 20160098959 | Moon | Apr 2016 | A1 |
| 20160247451 | Kim | Aug 2016 | A1 |
| 20170092200 | Park et al. | Mar 2017 | A1 |
| 20180012543 | Lee | Jan 2018 | A1 |
| 20180013085 | Shin | Jan 2018 | A1 |
| Number | Date | Country |
|---|---|---|
| 105989803 | Oct 2016 | CN |
| 2009-288767 | Dec 2009 | JP |
| 2013-33228 | Feb 2013 | JP |
| 2013-210407 | Oct 2013 | JP |
| 2014-123129 | Jul 2014 | JP |
| 201430804 | Aug 2014 | TW |
| 201434025 | Sep 2014 | TW |
| 201445541 | Dec 2014 | TW |
| 201523564 | Jun 2015 | TW |
| I614738 | Feb 2018 | TW |
| 2013065596 | May 2013 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 20190005888 A1 | Jan 2019 | US |
