Patent Application
20070083685
1. Field of the Invention
This invention relates to a data management method and module for a USB device, more particularly to a data management method and module for processing digital sample data generated by a USB device.
2. Description of the Related Art
Universal serial bus (USB) devices for multi-media applications are well known in the art. Conventionally, as illustrated in
The aforementioned conventional USB device 9 is disadvantageous in that, since the personal computer 7 and the ADC 911 of the USB device 9 may not be synchronized, either a deficient number of the digital sample data is stored in the buffer of the controller 912 in the case of data underflow, or desired ones of the digital sample data stored in the buffer of the controller 912 are overwritten by excess ones of the digital sample data in the case of data overflow. In either case, an undesirable popping noise is generated when the audio input signal is reproduced by the personal computer 7.
Therefore, the object of the present invention is to provide a data management method and module for processing digital sample data generated by a USB device prior to transmission so as to overcome the aforesaid drawbacks of the prior art.
According to one aspect of the present invention, a data management method for a USB device includes the steps of: sampling an analog input signal at a sampling frequency, and generating digital sample data corresponding to samples of the analog input signal; monitoring the number of the digital sample data generated within a predefined time interval; if the number of the digital sample data generated at the end of the predefined time interval matches a predetermined value, providing the digital sample data to a USB host; and if the number of the digital sample data generated at the end of the predefined time interval does not match the predetermined value, processing the digital sample data such that the number of the processed digital sample data matches the predetermined value, and providing the processed digital sample data to the USB host.
According to another aspect of the present invention, a data management module for a USB device comprises a data processing unit. The USB device includes an analog-to-digital converter that samples an analog input signal at a sampling frequency and that generates digital sample data corresponding to samples of the analog input signal. The data processing unit is adapted to be coupled between the analog-to-digital converter and a USB host. The data processing unit is operable so as to monitor the number of the digital sample data generated within a predefined time interval, so as to provide the digital sample data to the USB host if the number of the digital sample data generated at the end of the predefined time interval matches a predetermined value, and so as to process the digital sample data such that the number of the processed digital sample data matches the predetermined value and so as to provide the processed digital sample data to the USB host if the number of the digital sample data generated at the end of the predefined time interval does not match the predetermined value.
Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiments with reference to the accompanying drawings, of which:
Before the present invention is described in greater detail, it should be noted that like elements are denoted by the same reference numerals throughout the disclosure.
Referring to
The USB device, which is embodied in a composite USB device suitable for multi-media applications, includes an analog-to-digital converter (ADC) 2 and a USB interface 3. The ADC 2 receives an analog input signal, such as an audio signal, samples the analog input signal at a sampling frequency, such as 8 KHz or 16 KHz, and generates digital sample data that correspond to samples of the analog input signal and that are provided to a USB host 300, such as a personal computer. The USB interface 3 is coupled to the USB host 300, and converts the digital sample data from the data processing unit 100 into a USB signal that complies with a USB specification for subsequent receipt by the USB host 300.
The data processing unit 100 is coupled between the ADC 2 and the USB interface 3. In this embodiment, the data processing unit 100 is operable so as to monitor the number of the digital sample data generated within a predefined time interval, so as to provide the digital sample data to the USB interface 3 if the number of the digital sample data generated at the end of the predefined time interval matches a predetermined value, and so as to process the digital sample data such that the number of the processed digital sample data matches the predetermined value and so as to provide the processed digital sample data to the USB interface 3 if the number of the digital sample data generated at the end of the predefined time interval does not match the predetermined value, in a manner that will be described hereinafter.
It is noted herein that the USB host 300 periodically generates start-of-frame (SOF) signals at intervals of approximately 1 millisecond. Moreover, the predefined time interval is defined as the interval between two consecutive SOF signals. Further, the ADC 2 generates an AD_ready pulse for every digital sample data generated thereby.
In this embodiment, the data processing unit 100 includes a counter 11, a reset circuit 16, a buffer 15, a data latch 19, a write enable circuit 13, a controller 12, write and read address generators 14, 17, and a configuring circuit 18.
The counter 11 is connected electrically to the ADC 2 for receiving the AD_ready pulse, monitors the number of digital sample data generated by the ADC 2 by counting the number of AD_ready pulses received from the ADC 2, and is reset at the start of the predefined time interval through the reset circuit 16. In particular, the reset circuit 16 is connected electrically to the counter 11 and the USB interface 3, receives the SOF signals from the USB host 300 through the USB interface 3, and generates a reset signal, in response to the SOF signal, for resetting the counter 11.
The buffer 15 temporarily stores the digital sample data that are to be provided to the USB host 300 through the USB interface 3, and has a number of addressable storage locations equal to the predetermined value. In this embodiment, the buffer 15 is a 32-byte first-in first-out buffer memory that has sixteen addressable storage locations.
The data latch 19 is connected electrically to the ADC 2 and the buffer 15, and is operable so as to latch a latest one of the digital sample data from the ADC 2.
The write enable circuit 13 is connected electrically to and controls write operation of the buffer 15. It is noted that the write enable circuit 13 is further connected electrically to the ADC 2 for receiving the AD_ready pulse, and the reset circuit 16 for receiving the reset signal.
The controller 12 is connected electrically to counter 11 and the write enable circuit 13, and is configured with the predetermined value. The controller 12 regularly compares the number of digital sample data monitored by the counter 11 with the predetermined value configured therein.
The write address generator 14 is connected electrically to the buffer 15 and the controller 12, and is controlled by the controller 12 to generate an address location at which the digital sample data is written to the buffer 15.
If the controller 12 determines that the number of the digital sample data monitored by the counter 11 within the predefined time interval is less than the predetermined value configured therein, the controller 12 controls the write enable circuit 13, as well as the write address generator 14, to enable write operation of the buffer 15 within the predefined time interval. As such, when the write enable circuit 13 receives the AD_ready pulse from the ADC 2, the digital sample data latched in the data latch 19 is stored in the buffer 15 at the address location generated by the write address generator 14.
If the controller 12 determines that the number of the digital sample data monitored by the counter 11 at the end of the predefined time interval is less than the predetermined value configured therein, the controller 12 controls the write enable circuit 13 to enable write operation of the buffer 15 at the end of the predefined time interval. As such, when the write enable circuit 13 receives the reset signal from the reset circuit 16, the digital sample data latched in the data latch 19 is stored in the buffer 15. As illustrated in
On the other hand, if the controller 12 determines that the number of the digital sample data monitored by the counter 11 by the end of the predefined time interval is greater than the predetermined value configured therein, i.e., the monitored number of the digital sample data has exceeded the predetermined value before the expiry of the predefined time interval, the controller 12 controls the write enable circuit 13 to disable further write operation of the buffer 15. In other words, when the write enable circuit 13 receives the AD_ready pulse from the ADC 2 or the reset signal from the reset circuit 16, the latest one of the digital sample data latched in the data latch 19 is not stored in the buffer 15. As such, the desired ones of the digital sample data stored in the buffer 15 are not overwritten by the excess ones of the digital sample data, and the excess ones of the digital sample data are simply discarded.
The read address generator 17 is connected electrically to the buffer 15, and is operable so as to generate an address location at which the digital sample data is read from the buffer 15.
The configuring circuit 18 is connected electrically to the read address generator 17 and the USB interface 3, and is operable so as to set a maximum number (or isochronous number) of the digital sample data to be read from the buffer 15 without interruption and within the predefined time interval.
The preferred embodiment of a data management method, which is implemented using the aforementioned USB device, according to this invention includes the steps shown in
With further reference to
In step 42, the controller 12 controls the write enable circuit 13 to enable write operation of the buffer 15.
In step 43, the reset circuit 16 generates a reset signal.
In step 44, the counter 11 receives the reset signal and is reset. The write enable circuit 13 also receives the reset signal. Since, at this time, write operation of the buffer 15 is enabled, the digital sample data latched in the data latch 19 is stored in the buffer 15 at an address location generated by the write address generator 14.
In step 45, the ADC 2 samples the analog input signal at the sampling frequency, and generates digital sample data that corresponds to the samples of the analog input signal.
In step 46, the digital sample data is latched in the data latch 19.
In step 47, if the ADC 2 generates the AD_ready pulse, the flow proceeds to step 48. Otherwise, the flow goes back to step 45.
In step 48, the digital sample data latched in the data latch 19 is stored in the buffer 15.
In step 49, the counter 11 increments the number of the digital sample data monitored thereby.
In step 50, if the controller 12 determines that the number of the digital sample data is less than the predetermined value, the flow goes back to step 41. Otherwise, the flow proceeds to step 51.
In step 51, if the controller 12 determines that the number of the digital sample data is equal to the predetermined value, the flow goes back to step 41. Otherwise, the flow proceeds to step 52.
In step 52, the controller 12 controls the write enable circuit 13 to disable write operation of the buffer 15. Thereafter, the flow goes back to step 41.
The buffers 251, 252 are selected alternately and respectively during consecutive ones of the predefined time intervals for writing of the digital sample data generated by the ADC 2.
Each of the write enable circuits 231, 232 is connected electrically to the ADC 2 and the reset circuit 16, and is connected electrically between the controller 12 and a respective one of the buffers 251, 252. In this embodiment, the write enable circuits 231, 232 are selected alternately and respectively during the consecutive ones of the predefined time intervals.
The controller 12 controls the selected one of the write enable circuits 231, 232 so as to control in turn write operation of the selected one of the buffers 251, 252.
Each of the data latches 291, 292 is connected to a respective one of the buffers 251, 253.
The first data switch 201 is connected electrically to the ADC 2, and to the buffers 251, 252 through a respective one of the data latches 291, 292, and is operable so as to direct the digital sample data from the ADC 2 to the selected one of the buffers 251, 252. In this embodiment, the first data switch 201 is a demultiplexer.
The second data switch 202 is connected electrically between the buffers 251, 252 and the USB interface 3, and is operable so as to direct the digital sample data from the non-selected one of the buffers 251, 252 to the USB host 300. In this embodiment, the second data switch 202 is a multiplexer.
The buffer selector 203 is coupled to the reset circuit 16, the write enable circuits 231, 232, and the first and second data switches 201, 202. In this embodiment, the buffer selector 203 selects one of the buffers 251, 252 and one of the write enable circuits 231, 232 within the predefined time interval. Furthermore, the buffer selector 203 controls the operation of the first and second data switches 201, 202.
While the present invention has been described in connection with what is considered the most practical and preferred embodiments, it is understood that this invention is not limited to the disclosed embodiments but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.
