Patent Application
20190034118
The disclosure relates in general to a data management method and system for a memory device.
As improvement on semiconductor technology, a variety of semiconductor memories are developed. For example, flash memory, magnetic core memory and PCM (phase change memory) may be widely used in electronic devices.
PCM is a non-volatile memory. The material of PCM may be transited between crystalline state and amorphous state, for storing digital data. In reading PCM, resistance of the memory cells of PCM is determined to determine whether the memory cell stores logic 0 or logic 1.
However, resistance of memory cells may be shifted after time elapses, for example, shifting from high resistance state into low resistance state or vice versa. Thus, data reading may be error. In order to prevent error data reading, one of possible implementation is to refresh the memory cells or the memory pages after a time of period, for solving resistance shifting.
The application discloses a data management method and system for a memory device, for managing retention time and refresh time of the memory device.
According to one embodiment, provided is a data management system for a memory device. The memory device includes a plurality of blocks. The data management system includes: a processor, coupled to the memory device, the processor having a system time counter for counting a system time; and a retention time memory unit, coupled to the processor, the retention time memory unit including a retention mode parameter storage section, a remaining retention time storage section and a block number storage section. The retention mode parameter storage section stores a first retention mode, the remaining retention time storage section stores a first maximum remaining retention time, a first minimum remaining retention time and a first intermediate remaining retention time corresponding to the first retention mode, the block number storage section at least stores a first block number of a first block of the plurality of blocks of the memory device. When at least a part of the first block of the memory device is accessed or refreshed or programmed at first time or each time when the whole first block of the memory device is accessed or refreshed or programmed, the processor assigns the first block number of the first block to point to the first maximum remaining retention time of the first retention mode. When a first downgrade trigger time of the first maximum remaining retention time reaches and when the first block number of the first block currently points to the first maximum remaining retention time, the processor changes pointing of the first block number of the first block from the first maximum remaining retention time to the first intermediate remaining retention time. When a second downgrade trigger time of the first intermediate remaining retention time reaches and when the first block number of the first block currently points to the first intermediate remaining retention time, the processor changes pointing of the first block number of the first block from the first intermediate remaining retention time to the first minimum remaining retention time. Once the first block number of the first block currently points to the first minimum remaining retention time, the processor triggers the memory device to refresh the first block and changes pointing of the first block number of the first block from the first minimum remaining retention time to the first maximum remaining retention time.
According to another embodiment, provided is a data management method for a memory device. The memory device includes a plurality of blocks. The data management method includes: counting a system time; when at least a part of a first block of the memory device is accessed or refreshed or programmed at first time or each time when the whole first block of the memory device is accessed or refreshed or programmed, assigning a first block number of the first block to point to a first maximum remaining retention time of a first retention mode, the first retention mode including the first maximum remaining retention time, a first minimum remaining retention time and a first intermediate remaining retention time; when a first downgrade trigger time of the first maximum remaining retention time reaches and when the first block number of the first block currently points to the first maximum remaining retention time, changing pointing of the first block number of the first block from the first maximum remaining retention time to the first intermediate remaining retention time; when a second downgrade trigger time of the first intermediate remaining retention time reaches and when the first block number of the first block currently points to the first intermediate remaining retention time, changing pointing of the first block number of the first block from the first intermediate remaining retention time to the first minimum remaining retention time; and once the first block number of the first block currently points to the first minimum remaining retention time, triggering the memory device to refresh the first block and changing pointing of the first block number of the first block from the first minimum remaining retention time to the first maximum remaining retention time.
In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.
Technical terms of the disclosure are based on general definition in the technical field of the disclosure. If the disclosure describes or explains one or some terms, definition of the terms is based on the description or explanation of the disclosure. Each of the disclosed embodiments has one or more technical features. In possible implementation, one skilled person in the art would selectively implement part or all technical features of any embodiment of the disclosure or selectively combine part or all technical features of the embodiments of the disclosure.
The data management system 100 includes a processor 110 and a retention time memory unit 120. The processor 110 includes a system time counter 115. The processor 110 is coupled to the memory device 150 and the retention time memory unit 120. The processor 110 manages the remaining retention time and the refresh time of the memory device 150. The operation details of the processor 110 will be described later. The system time counter 115 is for counting system time.
The retention mode parameter storage section 122 is for storing at least one retention mode parameter. The retention mode parameter is for indicating the retention mode of the corresponding blocks. In here, the term “block” refers to the storage blocks of the memory device 150, for example, the memory pages. The memory device 150 includes a plurality of blocks. In the following embodiments, for explanation, all blocks of the memory device 150 is assigned by the same retention mode. However, the application is not limited by this. When a part of a block of the memory device 150 (or even the whole block) is accessed or refreshed or programmed at first time, the processor 110 predicts a default retention time of the block and assigns a retention mode to the block. In the embodiment of the application, when a part of a block of the memory device 150 (or even the whole block) is accessed or refreshed or programmed at first time, this may be the worst case. This is because the corresponding memory cell(s) (which is/are accessed or refreshed or programmed at first time) may reach the retention time earliest. In here, the term “accessed or refreshed or programmed at first time” refers to that after the memory device 150 is manufactured, the block of the memory device 150 is accessed or refreshed or programmed at first time.
In other possible embodiment of the application, each time when the whole block of the memory device 150 is accessed or refreshed or programmed, the CPU 110 predicts a default retention time of the block and assigns a retention mode to the block. Because the whole block is accessed or refreshed or programmed, it is suitable to assign the same retention time to all memory cells of the whole block.
When the retention mode is 10000 seconds, the maximum remaining retention time of the block is 10000 seconds. In other words, in an embodiment of the application, when the block is accessed or refreshed, before the retention time is expired, the embodiment of the application refreshes the block. Similarly, if the retention mode is 107 seconds, when the block is accessed or refreshed, the embodiment of the application refreshes the block before expiration of the retention time (107 seconds).
The remaining retention time storage section 124 indicates the respective remaining retention time of each of the blocks. Taking the retention mode is 10000 seconds as an example, in an embodiment of the application, 10000 seconds is divided into 10 groups, the first group is 10000 seconds, and the second group is 9000 seconds, and so on. Of course, the application is not limited by this. In other possible embodiments of the application, the maximum remaining retention time may be divided into a plurality of groups by other ways. For example, the maximum remaining retention time may be divided into several groups based on log or exponential.
In an embodiment of the application, all blocks of the memory device 150 are grouped based on their remaining retention time and the blocks having the same remaining retention time are in the same group.
For example, at a time point, if the remaining retention time of the block P9 is 10000 second, the processor 110 groups the block number PP9 of the block P9 into the first group; if the remaining retention time of the block P8 is 9000 second, the processor 110 groups the block number PP8 of the block P8 into the second group; and if the remaining retention time of the block P0 is 1000 second, the processor 110 groups the block number PP0 of the block P0 into the tenth group, and so on. “10000-second” is defined as the maximum remaining retention time, “1000-second” is defined as the minimum remaining retention time while “2000-second”-“9000-second” may be defined as the intermediate remaining retention time.
The block number storage section 126 is for storing block number of the blocks of the memory device 150. When a block is refreshed or accessed or programmed, the processor 110 assigns the block number of the block to be pointed to the maximum remaining retention time. When the downgrade trigger condition of the block is met, the processor 110 downgrades the block number of the block which meets the downgrade trigger condition and accordingly, the block number of the block points to the next remaining retention time. In an embodiment of the application, each group has its own downgrade trigger condition.
As shown in
In an embodiment of the application, the processor 110 may predict the retention time of the block based on the programming or accessing or refreshing condition(s) (for example but not limited by, the pulse voltages) or the chip temperature of the memory device 150. For example, the processor 110 may predict retention time of a worst case of the memory cells of the same block (i.e. the same memory page) as the retention time of the block. How to predict the retention time is not specified in the embodiment of the application.
Thus, in an embodiment of the application, each block is assigned by a retention mode. The embodiment of the application may have a plurality of retention modes. For simplicity, all blocks are assigned by the same retention mode but the application is not limited by.
As shown in
In the above example, the “group remaining retention time gaps” for each of the groups are the same, but in other possible embodiment of the application, the “group remaining retention time gaps” for the groups may be different, which is still within the spirit and scope of the application. For example, in other possible embodiment of the application which having five groups, the remaining retention time of the first group is 10000 seconds, the remaining retention time of the second group is 9000 seconds, the remaining retention time of the third group is 7500 seconds, the remaining retention time of the fourth group is 5500 seconds, and the remaining retention time of the fifth group is 1000 seconds. When to downgrade is based on the difference between the remaining retention time of two groups. In this case, the remaining retention time of the first group and the second group are 10000 seconds and 9000 seconds, respectively, and thus the difference between the remaining retention time of the first group and the second group is 1000 seconds. Thus, the CPU 110 downgrades the first group every 1000 seconds. The CPU 110 downgrades the second group every 1500 seconds. The CPU 110 downgrades the third group every 2000 seconds. The CPU 110 downgrades the fourth group every 4500 seconds.
As shown in
As shown in
Then, when the system time is at 3000 seconds (ST=3000) (not shown), the processor 110 downgrades the second group and the third group. The processor 110 downgrades the block number PP0 of the block P0 from the third group into the fourth group (whose remaining retention time is 7000 seconds) and downgrades the block number PP1 of the block P1 from the second group into the third group (whose remaining retention time is 8000 seconds). Similarly, when the system time is at 7000 seconds (ST=7000) (not shown), the processor 110 performs downgrade. The processor 110 downgrades the block number PP0 of the block P0 from the seventh group into the eighth group (whose remaining retention time is 3000 seconds) and downgrades the block number PP1 of the block P1 from the sixth group into the seventh group (whose remaining retention time is 4000 seconds).
As shown in
When the system time is at 8000 seconds (ST=8000) (not shown), the processor 110 downgrades the block number PP0-PP4 of the blocks P0-P4. The processor 110 downgrades the block number PP2-PP4 of the blocks P2-P4 from the first group into the second group (whose remaining retention time is 9000 seconds). The processor 110 downgrades the block number PP0 of the block P0 from the eighth group into the ninth group (whose remaining retention time is 2000 seconds). The processor 110 downgrades the block number PP1 of the block P1 from the seventh group into the eighth group (whose remaining retention time is 3000 seconds).
As shown in
As shown in
In an embodiment of the application, when a block number is downgraded into the lowest group (for example, the tenth group (whose remaining retention time is 1000 seconds) in the above example), the processor 110 upgrades the block number from the lowest-group into the first group and also the processor 110 informs the memory device 150 to refresh the block whose block number is upgraded from the lowest-group into the first group. As shown in
Further, in an embodiment of the application, because the block number in the same group are pointed to each other, in block refresh, it is easy to determine which block(s) is/are to be refreshed. For example, when the block number PP2-PP4 are in the same group, if the processor 110 downgrades the block number PP2-PP4 into the lowest group, the processor 110 informs the memory device 150 to refresh the blocks P2-P4. In details, because the block number PP2 is pointed to the lowest remaining retention time, the block number PP3 is pointed to the block number PP2, and the block number PP4 is pointed to the block number PP3 (via the point relationship of the block number PP2-PP4), the processor 110 determines that the group having lowest remaining retention time includes the block number PP2-PP4. Thus, the processor 110 determines that the block number PP2-PP4 should be ungraded and the blocks P2-P4 (which is corresponded to the block number PP2-PP4) should be refreshed. In the disclosure, among one or more block number which is/are pointed to the same remaining retention time, one block number (for example but not limited to, the block number PP2 in
In an embodiment of the application, if a block is accessed or refreshed, the processor 110 upgrades the block number of the accessed or refreshed block into the first group (regardless of which group the block number belongs). In other words, if a block is accessed or refreshed, the processor 110 sets the remaining retention time of the block as the maximum remaining retention time (for example 10000 seconds). Further, when the block is accessed or refreshed, the block number of the block is currently pointed to the first group, and then the block number of the block is still in the first group.
Still further, in an embodiment of the application, after downgrade, when there are several block number concurrently pointing to the lowest remaining retention time, the processor 110 sequentially triggers refresh of the blocks, that is, the blocks may be refreshed at different timing. For example, after downgrade, the block number PP0 and PP1 concurrently point to the lowest remaining retention time (1000 seconds). When the system time is at 9000 seconds, the processor 110 informs the memory device 150 to refresh the block P0. When the system time is at 9050 seconds, the processor 110 informs the memory device 150 to refresh the block P1. By so, before the remaining retention time of the blocks P0 and P1 are expired, the blocks P0 and P1 are refreshed, in order to prevent data reading error caused by resistance shift of the blocks P0 and/or P1.
In brief, in an embodiment of the application, when a block is accessed or refreshed, the processor 110 upgrades the block number of the block to the first group to point to the maximum remaining retention time. Besides, the processor 110 determines one or more block number concurrently pointing to the same remaining retention time as the same group. In the same group, one of the block number points to the corresponding remaining retention time and other block number points to each other. For example, in
When the processor 110 determines that downgrade trigger condition of a group is met, the processor 110 downgrades all block number of the group into the next group. In practice, under control of the processor 110, pointing of the first block number of the group (for example, the block number PP2 of the second group in
In
In an embodiment of the application, by managing the remaining retention time of the blocks of the memory device in groups, the blocks may be refreshed before the respective remaining retention time of the blocks is expired. Thus, data reading error caused by resistance shift of the blocks may be prevented. Further, in an embodiment of the application, because the remaining retention time of the blocks is/are managed in groups, the management is simplified.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.
