Claims
- 1. A data output circuit for providing a signal corresponding in logic level to an internal signal on an internal node to an output node, comprising:
- a drive transistor coupled between said output node and an output power supply node and responsive to said internal signal for transmitting a voltage on said output power supply node to said output node, said output power supply node providing the voltage of a logic level of the signal to be provided to said output node,
- a first current supply element having a first current driving capability, coupled between a voltage supply source and said output power supply node, and rendered conductive in response to an output permission signal providing a timing for outputting the signal to said output node, and
- a second current supply element having a second current driving capability greater than the first current driving capability, coupled between said voltage supply source and said output power supply node, and responsive to said output permission signal for attaining a conductive state after said first current supply element is rendered conductive.
- 2. The data output circuit according to claim 1, further comprising precharge means coupled between said output power supply node and a reference node supplying a reference potential intermediate between a voltage of said voltage supply source and a voltage different in logic level from said voltage on said voltage supply source, and responsive to inactivation of said output permission signal for transmitting said reference potential onto said output power supply node.
- 3. The data output circuit according to claim 1, wherein said voltage supply source is operatively coupled to receive a boosted operating power supply voltage.
- 4. The data output circuit according to claim 1, wherein said output power supply node supplies a voltage at a first logic level, and said drive transistor drives said output node to said first logic level, and wherein said data output circuit further includes a second drive transistor coupled between said output node and a second output power supply node supplying a voltage at a second logic level different from said first logic level, for driving said output node to said second logic level in response to said internal signal.
- 5. The data output circuit according to claim 4, further comprising a precharge means coupled between said output power supply node and said second output power supply node, and to receive a reference potential intermediate between the voltages at said first and second logic levels on a reference node, for transmitting the reference potential onto said output and second output power supply nodes in response to inactivation of said first and second drive transistors,
- a third current supply element coupled between a second voltage supply source supplying a voltage at said second logic level and said second output power supply node and in response to activation of said output permission signal for transmitting said voltage on said second voltage supply source onto said second output power supply node with a third current driving capability, and
- a fourth current supply element coupled between said second output power supply node and said second voltage supply source and having a fourth current driving capability greater than said third current driving capability, and responsive to said output permission signal for attaining a conductive state after said third current supply element is rendered conductive.
- 6. The data output circuit according claim 4, further comprising a switching element for electrically connecting the output power supply node with the second output power supply node when made conductive.
- 7. The data output circuit according to claim 4, further comprising:
- a third current supply element coupled between a second voltage supply source supplying a third voltage at said second logic level and said second output power supply node and in response to activation of said output permission signal for transmitting said voltage on said second voltage supply source onto said second output power supply node with a third current driving capability, and
- a fourth current supply element coupled between said second output power supply node and said second voltage supply source and having a fourth current driving capability greater than said third current driving capability, and responsive to said output permission signal for attaining a conductive state after said third current supply element is rendered conductive.
- 8. A data output circuit for providing a signal corresponding in logic level to an internal signal on an internal node to an output node, comprising:
- a drive transistor coupled between said output node and an output power supply node and responsive to said internal signal for transmitting a voltage on said output power supply node to said output node, said output power supply node providing the voltage of a logic level of the signal to be provided to said output node,
- a first current supply element coupled between a first voltage supply source and said output power supply node, and rendered conductive in response to an output permission signal providing a timing for outputting the signal to said output node, and
- a second current supply element coupled between a second voltage supply source and said output power supply node, and responsive to said output permission signal for attaining a conductive state after said first current supply element is rendered conductive,
- said second voltage supply source supplying a voltage at one of first and second logic levels, and said first voltage supply source supplying a voltage between voltages at said first and second logic levels, and said one of first and second logic levels corresponding to the logic level of the signal to be provided to said output node.
- 9. The data output circuit according to claim 8, wherein the voltage supplied from said first voltage supply source is at a level between the voltage from said second voltage supply source and a voltage intermediate between voltages at said first and second logic levels.
- 10. The data output circuit according to claim 8, further comprising precharge means coupled between said output power supply node and a reference node supplying a reference potential intermediate between the voltage on said first voltage supply source and a voltage different in logic level from said voltage on said first voltage supply source, and responsive to inactivation of said output permission signal for transmitting said reference potential onto said output power supply node.
- 11. The data output circuit according to claim 8, wherein said second voltage supply source is operatively coupled to receive a boosted operating power supply voltage.
- 12. The data output circuit according to claim 8, wherein said output power supply node supplies a voltage at the first logic level, and said drive transistor drives said output node to said first logic level, and wherein said data output circuit further includes:
- a second drive transistor coupled between said output node and a second output power supply node supplying a voltage for driving said output node to said second logic level in response to said internal signal, said second drive transistor made conductive complementarily to said drive transistor,
- a third current supply element coupled between a third voltage supply source and said second output power supply node and responsive to activation of said output permission signal for transmitting a voltage on said third voltage supply source onto said second output power supply node and
- a fourth current supply element coupled between said second output power supply node and a fourth voltage supply source and responsive to activation of a delayed output permission signal for transmitting a voltage on said fourth voltage supply source onto said second output power supply node,
- said fourth voltage supply source supplying a voltage at the second logic level, and said third voltage supply source supplying a voltage intermediate between voltages at said first and second logic levels.
- 13. The data output circuit according to claim 12, further comprising a precharge means coupled between said output power supply node and said second output power supply node, and to receive a reference potential intermediate between the voltages at said first and second logic levels on a reference node, for transmitting said reference potential onto said output power supply node and said second output power supply node in response to inactivation of said output permission signal.
- 14. The data output circuit according to claim 13, wherein said reference potential is at a potential level intermediate between the voltages at the first and second logic levels.
- 15. The data output circuit according to claim 8, wherein said output power supply node supplies a voltage at the first logic level, and said drive transistor drives said output node to said first logic level, and wherein said data output circuit further includes:
- a second drive transistor coupled between said output node and a second output power supply node supplying a voltage for driving said output node to said second logic level in response to said internal signal, said second drive transistor being made conductive complementarily to said drive transistor, and
- a switching element for electrically connecting said output power supply node and said second output power supply node with each other in response to inactivation of the output permission signal.
Priority Claims (1)
Number |
Date |
Country |
Kind |
6-280958 |
Nov 1994 |
JPX |
|
Parent Case Info
This application is a division of application Ser. No. 08/559,746 filed Nov. 15, 1995, allowed Apr. 10, 1997 now U.S. Pat. No. 5,701,090.
US Referenced Citations (6)
Divisions (1)
|
Number |
Date |
Country |
Parent |
559746 |
Nov 1995 |
|