Claims
- 1. A processing apparatus, comprising:a memory to store first image data arranged in a tile-type address and second image data arranged in an array-type address; a first processor to output said tile-type address and to access said first image data stored in said memory; and a second processor to output said array-type address and to access said second image data stored in said memory; wherein said memory, said first processor and said second processor are connected; and wherein a memory accessing portion is provided for controlling access from said first processor or said second processor to said memory, and for converting said array-type address output by said second processor into said tile-type address corresponding to said first image data to output to said memory, when said second processor accesses said first image data.
- 2. A processing apparatus as claimed in claim 1, wherein said memory accessing portion converts said tile-type address output by said first processor into said array-type address corresponding to said second image data to output to said memory, when said first processor accesses said second image data.
- 3. A processing apparatus, comprising:a memory to store first image data arranged in a tile-type address and second image data arranged in an array-type address; a first processor coupled to said memory, to access said first image data stored in said memory; a second processor coupled to said memory, to access said second image data stored in said memory; and a memory accessing portion provided to control data access from one of said first processor and said second processor to said memory.
- 4. A processing apparatus as claimed in claim 3, wherein said first processor outputs said tile-type address and accesses said first image data stored in said memory in accordance with said tile-type address.
- 5. A processing apparatus as claimed in claim 4, wherein said second processor outputs said array-type address and accesses said second image data stored in said memory in accordance with said array-type address.
- 6. A processing apparatus as claimed in claim 5, wherein said memory accessing portion converts said array-type address output by said second processor into said tile-type address corresponding to said first image data to output to said memory, when said second processor accesses said first image data.
- 7. A processing apparatus as claimed in claim 5, wherein said memory accessing portion converts said tile-type address output by said first processor into said array-type address corresponding to said second image data to output to said memory, when said first processor accesses said second image data.
- 8. A processing apparatus as claimed in claim 5, wherein the size of a region for said first image data stored in accordance with said tile-type address is first determined before data access is selected.
- 9. A processing apparatus, comprising:a memory to store first image data arranged in a tile-type address and second image data arranged in an array-type address; and processor means connected to said memory, to access said first image data and said second image data stored in said memory, said processor means including a memory accessing portion for controlling access to said memory using one of said tile-type address and said array-type address and for converting between said array-type address and said tile-type address when accessing one of said first image data and said second image data.
- 10. A processing apparatus as claimed in claim 9, wherein said memory access portion converts said array-type address output from said processor means into said tile-type address corresponding to said first image data to output to said memory, when said first image data is accessed.
- 11. A processing apparatus as claimed in claim 9, wherein said memory accessing portion converts said tile-type address output from said processor means into said array-type address corresponding to said second image data to output to said memory, when said second image data is accessed.
- 12. A processing apparatus as claimed in claim 9, wherein said processor means outputs said tile-type address and accesses said first image data stored in said memory in accordance with said tile-type address.
- 13. A processing apparatus as claimed in claim 9, wherein said processor means outputs said array-type address and accesses said second image data stored in said memory in accordance with said array-type address.
- 14. A processing apparatus as claimed in claim 12, wherein the size of a region for said first image data stored in accordance with said tile-type address is first determined before data access is selected.
- 15. A processing apparatus as claimed in claim 1, further comprising shading means for adding shading to one of said first image data and said second image data processed by said processor means, by calculating luminance for a small region in a graphic pattern defined by data parameters, said shading means comprising:defining means for defining plural geometrical vectors as parameters each defining luminance at an individual pixel forming said graphic pattern at an individual vertex at said graphic pattern; interpolation means for interpolating said plural geometrical vectors in said graphic pattern; and calculation means for calculating luminance for said small region in a graphic pattern by using plural geometrical vectors generated by interpolation.
- 16. A processing apparatus as claimed in claim 3, further comprising shading means for adding shading to one of said first image data and said second image data processed by said processor means, by calculating luminance for a small region in a graphic pattern defined by data parameters, said shading means comprising:defining means for defining plural geometrical vectors as parameters each defining luminance at an individual pixel forming said graphic pattern at an individual vertex at said graphic pattern; interpolation means for interpolating said plural geometrical vectors in said graphic pattern; and calculation means for calculating luminance for said small region in a graphic pattern by using plural geometrical vectors generated by interpolation.
- 17. A processing apparatus as claimed in claim 9, further comprising shading means for adding shading to one of said first image data and said second image data processed by said processor means, by calculating luminance for a small region in a graphic pattern defined by data parameters, said shading means comprising:defining means for defining plural geometrical vectors as parameters each defining luminance at an individual pixel forming said graphic pattern at an individual vertex at said graphic pattern; interpolation means for interpolating said plural geometrical vectors in said graphic pattern; and calculation means for calculating luminance for said small region in a graphic pattern by using plural geometrical vectors generated by interpolation.
CLAIM OF PRIORITY
This is a continuation application of a parent application entitled “DATA PROCESSING APPARATUS AND SHADING APPARATUS”, Ser. No. 08/894,786, filed on Aug. 28, 1997, now U.S. Pat. No. 6,433,782, which is a 371 of PCT/JP96/00446, filed on Feb. 27, 1996, all of which are incorporated herein.
US Referenced Citations (16)
Foreign Referenced Citations (4)
Number |
Date |
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59-186057 |
Oct 1984 |
JP |
60-221848 |
Nov 1985 |
JP |
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6-124201 |
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Continuations (1)
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Number |
Date |
Country |
Parent |
08/894786 |
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US |
Child |
10/175805 |
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US |