Data processing apparatus

Abstract

A DMA-mode data processing apparatus is provided which enables high-speed data processing and efficient use of a memory bus. For DMA circuits that perform at least one of data write into a memory and data read from a memory, a switch SW is disposed which is operated in accordance with an instruction of a CPU, and memory data lines and command signal lines of a first DMA circuit and a second DMA circuit can be connected through lines based on the instruction of the CPU. As a result, while one DMA circuit performs the data write into the memory or the data read from the memory, the other DMA circuit can acquire the data and can transfer the data to another address of the memory or transfer the data to input/output apparatuses.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a configuration of a data processing apparatus of a conventional art;

FIG. 2 is a flowchart of DMA-related operation of a CPU in a conventional art;

FIG. 3 is a simplified block diagram of a data processing apparatus in a prior art of the present invention;

FIG. 4 is an explanatory diagram of an example of data write into a memory and data read from a memory by a DMA circuit;

FIG. 5 is a block diagram of an overall configuration of the data processing apparatus in the prior art of the present invention;

FIG. 6 is a block diagram of an internal block configuration of the data processing apparatus in the prior art of the present invention;

FIG. 7 is an explanatory flowchart of DMA-related operation of a CPU of the data processing apparatus in the prior art of the present invention;

FIG. 8 is a simplified block diagram of a data processing apparatus according to one embodiment of the present invention;

FIG. 9 is a block diagram of an overall configuration of the data processing apparatus;

FIG. 10 depicts a configuration of a relevant part of the data processing apparatus;

FIG. 11 is an explanatory flowchart of DMA-related operation of a CPU and operation of a DMA; and

FIG. 12 depicts a configuration of a relevant part of a data processing apparatus according to another embodiment of the present invention.

Claims

1. A data processing apparatus comprising: a memory that allows data write and data read;a main controlling unit that outputs start instructions of the data write into the memory and the data read from the memory;a plurality of DMA circuits that performs at least one of the data write into the memory and the data read from the memory to output an end notification when completing at least one of the data write into the memory and the data read from the memory; anda plurality of activation instructing units that outputs an activation instruction for activating each of the DMA circuits, the activation instructing units outputting the activation instructions in response to the start instruction from the main controlling unit or the end notifications from the DMA circuits, the DMA circuits being activated in response to the activation instructions from the activation instructing units,the data processing apparatus having a parallel-group forming circuit for forming a parallel group of any two or more DMA circuits of the DMA circuits based on the instruction from the main controlling unit, the parallel-group forming circuit allowing data processed in a write process or read process of one DMA circuit to be acquired by the other DMA circuit.

2. The data processing apparatus as defined in claim 1, wherein one of the DMA circuits formed into the parallel group by the parallel-group forming circuit is set to be a master and the other is set to be a slave and wherein a signal line is disabled in the DMA circuit set to be the slave.

3. The data processing apparatus as defined in claim 2, wherein a DMA group is formed and serially coordinated by integrating the activation/end signals output by the DMA circuits and wherein interruption requests are disabled except that of the last DMA circuit.

4. The data processing apparatus as defined in claim 2 or 3, wherein the other DMA circuit provides the end notification for one DMA circuit every time the data process is completed and wherein one DMA circuit is set so as not to perform the next burst access operation unless the end notification is provided by the other DMA circuit.

5. The data processing apparatus as defined in claim 2 or 3, wherein a predetermined DMA circuit among the DMA circuits is set to select one requiring the longest data process time in a data process block.

6. The data processing apparatus as defined in claim 1 or 2, wherein the parallel-group forming circuit connects memory data lines and command signal lines of one DMA circuit and the other DMA circuit based on the instruction from the main controlling unit.

7. The data processing apparatus as defined in claim 1 or 2, wherein the parallel-group forming circuit disposes selectors on the DMA circuits and allows a data bus to be used in common to make a necessary DMA circuit active based on the instruction from the main controlling unit.

8. The data processing apparatus as defined in claim 1, wherein the parallel-group forming circuit connects control signal lines on the input/output apparatus side corresponding to the DMA circuits.