DATA PROCESSING APPARATUS

Abstract

A data processing apparatus includes a plurality of CPU modules each including a CPU. Each of the plurality of CPU module includes a clock source, a clock counter, an I/O module, a first data adder, and a timing adjuster. The first data adder reads a value of the clock counter, adds a predetermined offset value to the read value to generate a timing value, and adds the generated timing value to the packet designated to the CPU. The timing adjuster adjusts timing of transmitting the packet to the CPU, based on the timing value of the packet received from the first data adder and the value of the clock counter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings wherein:

FIG. 1 shows an example of a control block diagram of a data processing apparatus according to a first embodiment of the present invention;

FIG. 2 shows an example of a sequence diagram for illustrating an operation of resetting a CPU and a clock counter of each CPU module in the data processing apparatus shown in FIG. 1;

FIG. 3 shows an example of a sequence diagram for illustrating an operation performed in the data processing apparatus shown in FIG. 1, in which the CPU transmits a request packet to an I/O module and receives a response packet for the request packet from the I/O module;

FIG. 4 shows an example of a sequence diagram illustrating an operation performed in the data processing apparatus shown in FIG. 1, in which the I/O module transmits a request packet to the CPU and receives a response packet for the request packet from the CPU;

FIG. 5 shows an example of a sequence diagram illustrating an operation performed in the data processing apparatus shown in FIG. 1, the CPU receives an interruption packet periodically transmitted from the I/O module and resets the clock counter in response to the interruption packet;

FIG. 6 is a graph explicitly showing a fact that a clock counter deviation amount between the CPU modules fall in a certain range by the periodical resetting process explained with reference to FIG. 5; and

FIG. 7 shows an example of a control block diagram of a data processing apparatus according to a second embodiment of the present invention.

Claims

1. A data processing apparatus comprising a plurality of CPU modules each including a CPU, the plurality of CPU modules being connected to each other through a cross link; wherein each of the plurality of CPU module comprises:a clock source which supplies a clock to the CPU of its own;a clock counter which counts the clocks from the clock source;an I/O module which transmits and receives a predetermined packet to and from the CPU;a first data adder which, when a packet designated to the CPU is received from the I/O module, reads a value of the clock counter, adds a predetermined offset value to the read value to generate a timing value, and adds the generated timing value to the packet designated to the CPU; anda timing adjuster which adjusts timing of transmitting the packet to the CPU, based on the timing value of the packet received from the first data adder and the value of the clock counter.

2. The data processing apparatus according to claim 1, wherein each of the CPU module further comprises a comparator which compares the packet designated to the I/O module received from the CPU of its own with the packet designated to the I/O module received from the CPU of another CPU module through the cross link, and transmits one of the packets to the I/O module, when both the packets are coincident with each other.

3. The data processing apparatus according to claim 2, wherein each of the CPU module further comprises a second data adder which adds the value of the clock counter to the packet designated to the I/O module received from the CPU of its own, and transmits the packet to the comparator of one of the CPU modules of its own and another.

4. The data processing apparatus according to claim 3, wherein the comparator compares each of the values of the clock counters to be added to the respective packets when comparing the packets received from the second data adders of the CPU modules of its own and another.

5. The data processing apparatus according to claim 1, wherein the I/O module comprises a reset packet generator which generates a reset packet for resetting the clock counter, and transmits the reset packet to the timing adjuster.

6. The data processing apparatus according to claim 5, wherein the timing adjuster judges whether or not the received reset packet is received through the cross link, and determines timing of resetting the clock counter based on the judgement result.

7. The data processing apparatus according to claim 6, wherein the timing adjuster immediately resets the clock counter when the received reset packet is received through the cross link, and resets the clock counter after an elapse of a predetermined time when the received reset packet is not received through the cross link.

8. The data processing apparatus according to claim 6, wherein the reset packet is assigned an authentication code to specify the CPU module of a transmission source.

9. The data processing apparatus according to claim 5, wherein the reset packet generator generates and transmits the reset packet in response to a reset packet request from the CPU.

10. The data processing apparatus according to claim 5, wherein the I/O module transmits an interruption packet to the CPU for each elapse of a predetermined time.

11. The data processing apparatus according to claim 10, wherein the CPU requests the reset packet generator to transmit the reset packet for each reception of the interruption packet.

12. The data processing apparatus according to claim 7, wherein the timing adjuster resets the CPU when receiving the reset packet.