The invention relates to a digital television, and more particularly to a multiplexing process and a bit de-interleaving process of a digital television.
A multiplexing processing unit 120 re-arranges the data bits of the OFDM symbol symbolq by controlling orders of writing and reading the data bits of the OFDM symbol symbolq into/from a memory. Taking a code rate of 256 QAM equal to ⅗ for example, the multiplexing processing unit 120 includes a 16-bit memory. The order for reading and writing the memory is as shown by the bit sorting rule shown in
Because the multiplexing processing unit 120 and the bit de-interleaving unit 130 use different memories, a waste in memory is resulted. Further, multiple read and write operations performed by respective processing processes of the multiplexing processing unit 120 and the bit de-interleaving unit 130 degrade the overall circuit performance.
It is an object of the present invention to provide a data processing circuit and a data processing method of a digital television so as to enhance performance of multiplexing and bit de-interleaving processes and save hardware resources.
The present invention discloses a data processing circuit applied to a multiplexing process and a bit de-interleaving process of a digital television. A de-mapping circuit of the digital television generates a plurality of orthogonal frequency division multiplexing (OFDM) symbols. The data processing circuit includes a buffer, a write address generating circuit, a read address generating circuit and a memory controller. The buffer is coupled to the de-mapping circuit, and stores a target OFDM symbol. The target OFDM symbol is one of the OFDM symbols. The write address generating circuit generates a write address for each data bit of the target OFDM symbol according to a sequence number of the OFDM symbol. The read address generating circuit generates a read address for each data bit of the target OFDM symbol according to a counter value. The memory controller writes each data bit of the target OFDM symbol into a memory according to the write addresses, and reads each data bit of the target OFDM symbol from the memory according to the read addresses. Each data bit of the target OFDM symbol is subjected to one write operation and one read operation, and the target OFDM symbol read from the memory has undergone the multiplexing process and the bit de-interleaving process.
The present invention further discloses a data processing method applied to a multiplexing process and a bit de-interleaving process of a digital television. A de-mapping circuit of the digital television generates a plurality of orthogonal frequency division multiplexing (OFDM) symbols. The data processing method includes: storing a target OFDM symbol, which is one of the OFDM symbols; generating a write address for each data bit of the target OFDM symbol according to a sequence number of the target OFDM symbol; generating a read address for each data bit of the target OFDM symbol according to a counter value; and writing each data bit of the OFDM symbol into a memory according to the write addresses and reading each data bit of the target OFDM symbol from the memory according to the read addresses. Each data bit of the target OFDM symbol is subjected to one write operation and one read operation, and the target OFDM symbol read from the memory has undergone the multiplexing process and the bit de-interleaving process.
The data processing circuit and data processing method for a digital television of the present invention are capable of completing a multiplexing process and a bit de-interleaving process after performing one write operation and one read operation. Compared to conventional solutions, the data processing circuit and the data processing method of the present invention enhance the performance of a digital television and save hardware resources. In certain operations, successive memory addresses are used for write operations or read operations, further enhancing access efficiency of the memory as well as the overall circuit performance.
The above and other aspects of the invention will become better understood with regard to the following detailed description of the embodiments. The following description is made with reference to the accompanying drawings.
The disclosure of the application includes a data processing circuit and a data processing method for a digital television. The data processing circuit and the data processing method are capable of enhancing the performance of the digital television and saving hardware resources, and are applicable to a receiving end of the digital television. In possible implementation, one person skilled in the art can choose equivalent elements or steps to realize the present invention based on the disclosure of the application; that is, the implementation of the present invention is not limited to the embodiments below.
The row index calculating circuit 406 generates a row index rd,q (0≤rd,q<Nr) according to the sequence number q of the OFDM symbol and the counter value d of the bit counter 408. More specifically, the row index calculating circuit 406 generates the row index rd,q according to the rule below:
r
d,q
=div(d+q×ηmod, Nc) . . . (1)
The address mapping circuit 402 eventually generates the write address W_addr according to an equation below:
W_addrd,q=cd,q×Nr+rd,q . . . (2)
In the read address generating circuit 450, an offset compensation circuit 454 generates a column index ci and a row index ri according to a counter value i outputted by a counter 452 as well as equation (3), and an address mapping circuit 456 then generates the read address R_addr according to the column index ci, the row index ri and equation (4):
In the above, tc
The memory controller 220 writes data into the memory 230 according to the write address W_addr, and reads the data from the memory 230 according to the read address R_addr to generate an output bit ui having undergone the multiplexing process and the bit de-interleaving process. In this embodiment, the data processing circuit 200 takes into account the bit sorting rule of the multiplexing process in the write operation, and completes offset compensation of the bit de-interleaving process in the read operation, and so the data bit read from the memory has already undergone the multiplexing process and the bit de-interleaving process. More specifically, the data processing circuit 200 of the present invention can simultaneously complete the multiplexing process and the bit de-interleaving process after performing only one write operation and one read operation on the data bit generated by the de-mapping circuit 110, thus enhancing circuit performance while saving memory space.
The write address generating circuit 500 includes an address mapping circuit 502, a column index calculating circuit 504, a row index calculating circuit 506 and a bit counter 508. The bit counter 508 cyclically sequentially outputs a counter value d, where 0≤d<ηmod. The column index calculating circuit 504 generates a column index cd,q (0≤cd,q<Nc) according to the sequence number q of the OFDM symbol and the counter value d of the bit counter 508. More specifically, the column index generating circuit 504 generates the column index cd,q0≤cd,q<Nc according to the rules in Table-1 and Table-2, wherein the first sub-rule (Table-1) is referred to when the sequence number q is an even number (including 0), and the second sub-rule (Table-2) is referred to when the sequence number q is an odd number.
The row index calculating circuit 506 generates a row index rd,q (0≤rd,q<Nr) according to the sequence number q of the OFDM symbol and the counter value d of the bit counter 508, and takes into account the value of offset compensation tc
r
d,q=mod(div(d+q×ηmod, Nc)−tc
Taking Nr=4050 and Nc=16 for example, the value of the offset compensation tc
The address mapping circuit 502 eventually generates the write address W_addr according to equation (6).
W_addrd,q=cd,q×Nr+rd,q . . . (6)
In the read address generating circuit 550, an address mapping circuit 554 generates the read address R_addr according to a counter value i (0≤i<NLDPC) outputted by a counter 552 and equation (7):
The memory controller 220 writes data into the memory 230 according to the write address W_addr, and reads the data from the memory 230 according to the read address R_addr to generate an output bit ui having undergone the multiplexing process and the bit de-interleaving process. Similarly, the data processing circuit 200 of the present invention is capable of simultaneously completing the multiplexing process and the bit de-interleaving process after performing only one write operation and only read operation on the data bit generated by the de-mapping circuit 110. Further, in this embodiment, because the data processing circuit 200 has already taken into account both the bit sorting rule of the multiplexing process and the offset compensation of the bit de-interleaving process while writing the data bits into the memory 230, successively reading the data bits can be carried out when reading the data bits from the memory 230 (i.e., R_addri=i), further enhancing reading performance of the memory 230.
The write address generating circuit 600 includes an address mapping circuit 602, a column index calculating circuit 604, a row index calculating circuit 606 and a bit counter 608. The bit counter 608 cyclically sequentially outputs a counter value d, where 0≤d<ηmod. The column index calculating circuit 604 generates a column index cd,q (0≤cd,q<Nc) according to the sequence number q of the OFDM symbol and the counter value d of the bit counter 608. More specifically, the column index generating circuit 604 generates the column index cd,q according to equation (8).
c
d,q
=d+mod(q, Nc/ηmod)×ηmod . . . (8)
The row index calculating circuit 606 generates a row index rd,q (0≤rd,q<Nr) according to the sequence number q of the OFDM symbol and the counter value d of the bit counter 608. More specifically, the row index calculating circuit 606 generates the row index rd,q according to equation (9).
r
d,q=mod(div(d+q×ηmod, Nc)−tc
In the above, tc
W_addrd,q=Cd,q+rd,q×Nc . . . (10)
The read address generating circuit 650 includes an address mapping circuit 652, a column index calculating circuit 654, a row index calculating circuit 656 and a counter 658. The column index calculating circuit 654 calculates an intermediate value bi according to the counter value i (0≤i<NLDPC) outputted by the counter 658 as well as equation (11), and generates a column index ci according to the intermediate value bi and Table-5.
b
i=div(i, Nr) . . . (11)
The row index calculating circuit 656 obtains a row index ri according the counter value i outputted by the counter 658 as well as equation (12).
r
i=mod(i, Nr) . . . (12)
The address mapping circuit 652 eventually obtains the read address R_addr according to the column index ci, the row index ri and equation (13):
R_addri=ci+ri×Nc . . . (13)
The memory controller 220 writes data into the memory 230 according to the write address W_addr, and reads the data from the memory 230 according to the read address R_addr to generate an output bit ui having undergone the multiplexing process and the bit de-interleaving process. In this embodiment, the data processing circuit 200 completes offset compensation of the bit de-interleaving process in the write operation, and takes into account the bit sorting rule of the multiplexing process in the read operation, and so the data bit read from the memory has already undergone the multiplexing process and the bit de-interleaving process. More specifically, the data processing circuit 200 of the present invention can simultaneously complete the multiplexing process and the bit de-interleaving process after performing only one write operation and one read operation on the data bit generated by the de-mapping circuit 110, thus enhancing circuit performance while saving memory space.
The write address generating circuit 700 includes an address mapping circuit 702, a column index calculating circuit 704, a row index calculating circuit 706 and a bit counter 708. The bit counter 708 cyclically sequentially outputs a counter value d, where 0≤d<ηmod. The column index calculating circuit 704 generates a column index cd,q (0≤cd,q<Nc) according to the sequence number q of the OFDM symbol and the counter value d of the bit counter 508. More specifically, the column index generating circuit 504 generates the column index cd,q according equation (14).
c
d,q
=d+mod(q, Nc/ηmod)×ηmod . . . (14)
The row index calculating circuit 706 generates a row index rd,q (0≤rd,q<Nr) according to the sequence number q of the OFDM symbol and the counter value d of the bit counter 708. More specifically, the row index calculating circuit 706 generates the row index rd,q according to equation (15):
r
d,q=div(d+q×μmod, Nc)=div(q, Nc/ηmod) . . . (15)
The address mapping circuit 702 eventually generates the write address W_addr according to an equation below:
In fact, because the counter d=0, 1, 2, . . . , ηmod−1, 0, 1, 2 . . . , and the sequence number q=0, 1, 2 . . . , Waddr
The read address generating circuit 750 includes an address mapping circuit 752, a column index calculating circuit 754, a row index calculating circuit 756 and a counter 758. The column index calculating circuit 754 calculates an intermediate value bi according to the counter value i (0≤i<NLDPC) and equation (17), and then generates a column index ci according to the intermediate value bi and Table-5.
b
i=div(i, Nr) . . . (17)
The row index calculating circuit 756 obtains a row index ri according the counter value i outputted by the counter 758 and equation (18).
r
i=mod(i+tc
In the above, tc
R_addri=ci+ri×Nc . . . (19)
The memory controller 220 writes data into the memory 230 according to the write address W_addr, and reads the data from the memory 230 according to the read address R_addr to generate an output bit ui having undergone the multiplexing process and the bit de-interleaving process. In this embodiment, because the data processing circuit 200 has, in the reading process, already taken into account both the bit sorting rule of the multiplexing process and the offset compensation of the bit de-interleaving process, successively writing the data bits can be carried out when writing the data bit from the memory 230 (i.e., W_addri=i), further enhancing writing performance of the memory 230.
In addition to the foregoing data processing circuit, the present invention correspondingly discloses a data processing method, which can be performed by the foregoing data processing circuit 200 or an equivalent device.
In step S910, a target OFDM symbol among a plurality of OFDM symbols is stored.
In step S920, a write address is generated for each bit of the target OFDM symbol according to a sequence number of the target OFDM symbol.
In step S930, a read address is generated for each bit of the target OFDM symbol according to a counter value.
In step S940, each bit of the target OFDM symbol is written into a memory according to the write addresses, and each bit of the target OFDM symbol is read from the memory according to the read addresses.
Details of steps S910 to S940 are as described in the embodiments in
One person skilled in the art can easily understand implementation details and variations based on the disclosure of the device of the present invention, and these details shall be omitted herein. While the invention has been described by way of example and in terms of the embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
This application claims the benefit of U.S. Provisional Application Serial No. 62/459,551, filed Feb. 15, 2017, the subject matter of which is incorporated herein by reference.
Number | Date | Country | |
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62459551 | Feb 2017 | US |