Patent Grant
RE49243
This application is a reissue application of U.S. Pat. No. 9,621,191, which issued from a U.S. national stage application of PCT Application No. PCT/JP2015/053181, filed on Feb. 5, 2015, and is based upon and claims the benefit of priority from prior Japanese Application No. 2014-030012, filed on Feb. 19, 2014. The entire contents of the above-identified documents are incorporated herein by reference.
The present technology relates to a data processing device and a data processing method, and particularly to a data processing device and a data processing method which can ensure excellent communication quality in data transmission using, for example, an LDPC code.
Some information used in the present specification and drawings was provided by Samsung Electronics Co., Ltd. (hereinafter referred to as Samsung), LG Electronics Inc., NERC, and CRC/ETRI (which is clarified in the drawings).
A Low Density Parity Check (LDPC) code has a high error correcting capability and has been widely adopted in transmission systems for digital broadcasting, for example, Digital Video Broadcasting (DVB)-S.2, DVB-T.2, and DVB-C.2 of Europe, Advanced Television Systems Committee (ATSC) 3.0 of the U.S., and the like in recent years (for example, refer to Non-Patent Literature 1).
From a recent study, it is known that performance near a Shannon limit is obtained from the LDPC code when a code length increases, similar to a turbo code. Because the LDPC code has a property that a shortest distance is proportional to the code length, the LDPC code has advantages of a block error probability characteristic being superior and a so-called error floor phenomenon observed in a decoding characteristic of the turbo code being rarely generated, as characteristics thereof.
In data transmission using LDPC codes, for example, an LDPC code serves as a symbol (becomes a symbol) of quadrature modulation (digital modulation) such as Quadrature Phase Shift Keying (QPSK), and the symbol is mapped to a signal point of the quadrature modulation and is transmitted.
Such data transmission using LDPC codes continues to become widespread worldwide and ensuring communication (transmission) quality is being demanded.
The present technology takes the above situation into account, and aims to ensure excellent communication quality in data transmission using LDPC codes.
A first data processing device/method according to the present technology includes: an encoding unit/step configured to perform LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 64800 bits and an encoding rate r of 5/15; a group-wise interleaving unit/step configured to perform group-wise interleaving of interleaving the LDPC code in a unit of a bit group of 360 bits; and a mapping unit/step configured to map the LDPC code to any one of four signal points decided using a modulation method in a unit of 2 bits. In the group-wise interleaving, setting an i+1-th bit group from a head of the LDPC code as a bit group i, arrangement of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into arrangement of bit groups
39, 47, 96, 176, 33, 75, 165, 38, 27, 58, 90, 76, 17, 46, 10, 91, 133, 69, 171, 32, 117, 78, 13, 146, 101, 36, 0, 138, 25, 77, 122, 49, 14, 125, 140, 93, 130, 2, 104, 102, 128, 4, 111, 151, 84, 167, 35, 127, 156, 55, 82, 85, 66, 114, 8, 147, 115, 113, 5, 31, 100, 106, 48, 52, 67, 107, 18, 126, 112, 50, 9, 143, 28, 160, 71, 79, 43, 98, 86, 94, 64, 3, 166, 105, 103, 118, 63, 51, 139, 172, 141, 175, 56, 74, 95, 29, 45, 129, 120, 168, 92, 150, 7, 162, 153, 137, 108, 159, 157, 173, 23, 89, 132, 57, 37, 70, 134, 40, 21, 149, 80, 1, 121, 59, 110, 142, 152, 15, 154, 145, 12, 170, 54, 155, 99, 22, 123, 72, 177, 131, 116, 44, 158, 73, 11, 65, 164, 119, 174, 34, 83, 53, 24, 42, 60, 26, 161, 68, 178, 41, 148, 109, 87, 144, 135, 20, 62, 81, 169, 124, 6, 19, 30, 163, 61, 179, 136, 97, 16, and 88.
The parity check matrix includes an A matrix which is on an upper left of the parity check matrix having g rows and K columns represented with a predetermined value g and an information length K=N×r of the LDPC code, a B matrix which has a staircase structure close to a right side of the A matrix having g rows and g columns, a Z matrix which is a zero matrix close to a right side of the B matrix having g rows and N−K−g columns, a C matrix which is close to a bottom side of the A matrix and the B matrix having N−K−g rows and K+g columns, and a D matrix which is a unit matrix close to a right side of the C matrix having N−K−g rows and N−K−g columns. The predetermined value g is 1440. The A matrix and the C matrix are expressed using a parity check matrix initial value table. The parity check matrix initial value table is a table representing positions of elements of 1 of the A matrix and the C matrix for every 360 columns, the table including
221 1011 1218 4299 7143 8728 11072 15533 17356 33909 36833
360 1210 1375 2313 3493 16822 21373 23588 23656 26267 34098
544 1347 1433 2457 9186 10945 13583 14858 19195 34606 37441
37 596 715 4134 8091 12106 24307 24658 34108 40591 42883
235 398 1204 2075 6742 11670 13512 23231 24784 27915 34752
204 873 890 13550 16570 19774 34012 35249 37655 39885 42890
221 371 514 11984 14972 15690 28827 29069 30531 31018 43121
280 549 1435 1889 3310 10234 11575 15243 20748 30469 36005
223 666 1248 13304 14433 14732 18943 21248 23127 38529 39272
370 819 1065 9461 10319 25294 31958 33542 37458 39681 40039
585 870 1028 5087 5216 12228 16216 16381 16937 27132 27893
164 167 1210 7386 11151 20413 22713 23134 24188 36771 38992
298 511 809 4620 7347 8873 19602 24162 29198 34304 41145
105 830 1212 2415 14759 15440 16361 16748 22123 32684 42575
659 665 668 6458 22130 25972 30697 31074 32048 36078 37129
91 808 953 8015 8988 13492 13987 15979 28355 34509 39698
594 983 1265 3028 4029 9366 11069 11512 27066 40939 41639
506 740 1321 1484 10747 16376 17384 20285 31502 38925 42606
338 356 975 2022 3578 18689 18772 19826 22914 24733 27431
709 1264 1366 4617 8893 25226 27800 29080 30277 37781 39644
840 1179 1338 2973 3541 7043 12712 15005 17149 19910 36795
1009 1267 1380 4919 12679 22889 29638 30987 34637 36232 37284
466 913 1247 1646 3049 5924 9014 20539 34546 35029 36540
374 697 984 1654 5870 10883 11684 20294 28888 31612 34031
117 240 635 5093 8673 11323 12456 14145 21397 39619 42559
122 1265 1427 13528 14282 15241 16852 17227 34723 36836 39791
595 1180 1310 6952 17916 24725 24971 27243 29555 32138 35987
140 470 1017 13222 13253 18462 20806 21117 28673 31598 37235
7 710 1072 8014 10804 13303 14292 16690 26676 36443 41966
48 189 759 12438 14523 16388 23178 27315 28656 29111 29694
285 387 410 4294 4467 5949 25386 27898 34880 41169 42614
474 545 1320 10506 13186 18126 27110 31498 35353 36193 37322
1075 1130 1424 11390 13312 14161 16927 25071 25844 34287 38151
161 396 427 5944 17281 22201 25218 30143 35566 38261 42513
233 247 694 1446 3180 3507 9069 20764 21940 33422 39358
271 508 1013 6271 21760 21858 24887 29808 31099 35475 39924
8 674 1329 3135 5110 14460 28108 28388 31043 31137 31863
1035 1222 1409 8287 16083 24450 24888 29356 30329 37834 39684
391 1090 1128 1866 4095 10643 13121 14499 20056 22195 30593
161 1402 6289 6837 8791 17937 21425 26602 30461 37241
110 377 1228 6875 13253 17032 19008 23274 32285 33452 41630
360 638 1355 5933 12593 13533 23377 23881 24586 26040 41663
535 1240 1333 3354 10860 16032 32573 34908 34957 39255 40759
526 936 1321 7992 10260 18527 28248 29356 32636 34666 35552
336 785 875 7530 13062 13075 18925 27963 28703 33688 36502
36 591 1062 1518 3821 7048 11197 17781 19408 22731 24783
214 1145 1223 1546 9475 11170 16061 21273 38688 40051 42479
1136 1226 1423 20227 22573 24951 26462 29586 34915 42441 43048
26 276 1425 6048 7224 7917 8747 27559 28515 35002 37649
127 294 437 4029 8585 9647 11904 24115 28514 36893 39722
748 1093 1403 9536 19305 20468 31049 38667 40502 40720 41949
96 638 743 9806 12101 17751 22732 24937 32007 32594 38504
649 904 1079 2770 3337 9158 20125 24619 32921 33698 35173
401 518 984 7372 12438 12582 18704 35874 39420 39503 39790
10 451 1077 8078 16320 17409 25807 28814 30613 41261 42955
405 592 1178 15936 18418 19585 21966 24219 30637 34536 37838
50 584 851 9720 11919 22544 22545 25851 35567 41587 41876
911 1113 1176 1806 10058 10809 14220 19044 20748 29424 36671
441 550 1135 1956 11254 18699 30249 33099 34587 35243 39952
510 1016 1281 8621 13467 13780 15170 16289 20925 26426 34479
4969 5223 17117 21950 22144 24043 27151 39809
11452 13622 18918 19670 23995 32647 37200 37399
6351 6426 13185 13973 16699 22524 31070 31916
4098 10617 14854 18004 28580 36158 37500 38552.
In the above-described first data processing device/method, LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 64800 bits and an encoding rate r of 5/15 is performed; group-wise interleaving of interleaving the LDPC code is performed in a unit of a bit group of 360 bits; and the LDPC code is mapped to any one of four signal points decided using a modulation method in a unit of 2 bits. In the group-wise interleaving, setting an i+1-th bit group from a head of the LDPC code as a bit group i, arrangement of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into arrangement of bit groups
39, 47, 96, 176, 33, 75, 165, 38, 27, 58, 90, 76, 17, 46, 10, 91, 133, 69, 171, 32, 117, 78, 13, 146, 101, 36, 0, 138, 25, 77, 122, 49, 14, 125, 140, 93, 130, 2, 104, 102, 128, 4, 111, 151, 84, 167, 35, 127, 156, 55, 82, 85, 66, 114, 8, 147, 115, 113, 5, 31, 100, 106, 48, 52, 67, 107, 18, 126, 112, 50, 9, 143, 28, 160, 71, 79, 43, 98, 86, 94, 64, 3, 166, 105, 103, 118, 63, 51, 139, 172, 141, 175, 56, 74, 95, 29, 45, 129, 120, 168, 92, 150, 7, 162, 153, 137, 108, 159, 157, 173, 23, 89, 132, 57, 37, 70, 134, 40, 21, 149, 80, 1, 121, 59, 110, 142, 152, 15, 154, 145, 12, 170, 54, 155, 99, 22, 123, 72, 177, 131, 116, 44, 158, 73, 11, 65, 164, 119, 174, 34, 83, 53, 24, 42, 60, 26, 161, 68, 178, 41, 148, 109, 87, 144, 135, 20, 62, 81, 169, 124, 6, 19, 30, 163, 61, 179, 136, 97, 16, and 88.
The parity check matrix includes an A matrix which is on an upper left of the parity check matrix having g rows and K columns represented with a predetermined value g and an information length K=N×r of the LDPC code, a B matrix which has a staircase structure close to a right side of the A matrix having g rows and g columns, a Z matrix which is a zero matrix close to a right side of the B matrix having g rows and N−K−g columns, a C matrix which is close to a bottom side of the A matrix and the B matrix having N−K−g rows and K+g columns, and a D matrix which is a unit matrix close to a right side of the C matrix having N−K−g rows and N−K−g columns. The predetermined value g is 1440. The A matrix and the C matrix are expressed using a parity check matrix initial value table. The parity check matrix initial value table is a table representing positions of elements of 1 of the A matrix and the C matrix for every 360 columns, the table including
221 1011 1218 4299 7143 8728 11072 15533 17356 33909 36833
360 1210 1375 2313 3493 16822 21373 23588 23656 26267 34098
544 1347 1433 2457 9186 10945 13583 14858 19195 34606 37441
37 596 715 4134 8091 12106 24307 24658 34108 40591 42883
235 398 1204 2075 6742 11670 13512 23231 24784 27915 34752
204 873 890 13550 16570 19774 34012 35249 37655 39885 42890
221 371 514 11984 14972 15690 28827 29069 30531 31018 43121
280 549 1435 1889 3310 10234 11575 15243 20748 30469 36005
223 666 1248 13304 14433 14732 18943 21248 23127 38529 39272
370 819 1065 9461 10319 25294 31958 33542 37458 39681 40039
585 870 1028 5087 5216 12228 16216 16381 16937 27132 27893
164 167 1210 7386 11151 20413 22713 23134 24188 36771 38992
298 511 809 4620 7347 8873 19602 24162 29198 34304 41145
105 830 1212 2415 14759 15440 1 6361 16748 22123 32684 42575 659 665 668 6458 22130 25972 30697 31074 32048 36078 37129
91 808 953 8015 8988 13492 13987 15979 28355 34509 39698
594 983 1265 3028 4029 9366 11069 11512 27066 40939 41639
506 740 1321 1484 10747 16376 17384 20285 31502 38925 42606
338 356 975 2022 3578 18689 18772 19826 22914 24733 27431
709 1264 1366 4617 8893 25226 27800 29080 30277 37781 39644
840 1179 1338 2973 3541 7043 12712 15005 17149 19910 36795
1009 1267 1380 4919 12679 22889 29638 30987 34637 36232 37284
466 913 1247 1646 3049 5924 9014 20539 34546 35029 36540
374 697 984 1654 5870 10883 11684 20294 28888 31612 34031
117 240 635 5093 8673 11323 12456 14145 21397 39619 42559
122 1265 1427 13528 14282 15241 16852 17227 34723 36836 39791
595 1180 1310 6952 17916 24725 24971 27243 29555 32138 35987
140 470 1017 13222 13253 18462 20806 21117 28673 31598 37235
7 710 1072 8014 10804 13303 14292 16690 26676 36443 41966
48 189 759 12438 14523 16388 23178 27315 28656 29111 29694
285 387 410 4294 4467 5949 25386 27898 34880 41169 42614
474 545 1320 10506 13186 18126 27110 31498 35353 36193 37322
1075 1130 1424 11390 13312 14161 16927 25071 25844 34287 38151
161 396 427 5944 17281 22201 25218 30143 35566 38261 42513
233 247 694 1446 3180 3507 9069 20764 21940 33422 39358
271 508 1013 6271 21760 21858 24887 29808 31099 35475 39924
8 674 1329 3135 5110 14460 28108 28388 31043 31137 31863
1035 1222 1409 8287 16083 24450 24888 29356 30329 37834 39684
391 1090 1128 1866 4095 10643 13121 14499 20056 22195 30593
55 161 1402 6289 6837 8791 17937 21425 26602 30461 37241
110 377 1228 6875 13253 17032 19008 23274 32285 33452 41630
360 638 1355 5933 12593 13533 23377 23881 24586 26040 41663
535 1240 1333 3354 10860 16032 32573 34908 34957 39255 40759
526 936 1321 7992 10260 18527 28248 29356 32636 34666 35552
336 785 875 7530 13062 13075 18925 27963 28703 33688 36502
36 591 1062 1518 3821 7048 11197 17781 19408 22731 24783
214 1145 1223 1546 9475 11170 16061 21273 38688 40051 42479
1136 1226 1423 20227 22573 24951 26462 29586 34915 42441 43048
26 276 1425 6048 7224 7917 8747 27559 28515 35002 37649
127 294 437 4029 8585 9647 11904 24115 28514 36893 39722
748 1093 1403 9536 19305 20468 31049 38667 40502 40720 41949
96 638 743 9806 12101 17751 22732 24937 32007 32594 38504
649 904 1079 2770 3337 9158 20125 24619 32921 33698 35173
401 518 984 7372 12438 12582 18704 35874 39420 39503 39790
10 451 1077 8078 16320 17409 25807 28814 30613 41261 42955
405 592 1178 15936 18418 19585 21966 24219 30637 34536 37838
50 584 851 9720 11919 22544 22545 25851 35567 41587 41876
911 1113 1176 1806 10058 10809 14220 19044 20748 29424 36671
441 550 1135 1956 11254 18699 30249 33099 34587 35243 39952
510 1016 1281 8621 13467 13780 15170 16289 20925 26426 34479
4969 5223 17117 21950 22144 24043 27151 39809
11452 13622 18918 19670 23995 32647 37200 37399
6351 6426 13185 13973 16699 22524 31070 31916
4098 10617 14854 18004 28580 36158 37500 38552.
A second data processing device/method according to the present technology includes: a group-wise deinterleaving unit/step configured to return an arrangement of the LDPC code that has undergone group-wise interleaving obtained from data transmitted from a transmitting device to an original arrangement, the transmitting device including an encoding unit configured to perform LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 64800 bits and an encoding rate r of 5/15; a group-wise interleaving unit configured to perform group-wise interleaving of interleaving the LDPC code in a unit of a bit group of 360 bits; and a mapping unit configured to map the LDPC code to any one of four signal points decided using a modulation method in a unit of 2 bits. In the group-wise interleaving, setting an i+1-th bit group from a head of the LDPC code as a bit group i, arrangement of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into arrangement of bit groups
39, 47, 96, 176, 33, 75, 165, 38, 27, 58, 90, 76, 17, 46, 10, 91, 133, 69, 171, 32, 117, 78, 13, 146, 101, 36, 0, 138, 25, 77, 122, 49, 14, 125, 140, 93, 130, 2, 104, 102, 128, 4, 111, 151, 84, 167, 35, 127, 156, 55, 82, 85, 66, 114, 8, 147, 115, 113, 5, 31, 100, 106, 48, 52, 67, 107, 18, 126, 112, 50, 9, 143, 28, 160, 71, 79, 43, 98, 86, 94, 64, 3, 166, 105, 103, 118, 63, 51, 139, 172, 141, 175, 56, 74, 95, 29, 45, 129, 120, 168, 92, 150, 7, 162, 153, 137, 108, 159, 157, 173, 23, 89, 132, 57, 37, 70, 134, 40, 21, 149, 80, 1, 121, 59, 110, 142, 152, 15, 154, 145, 12, 170, 54, 155, 99, 22, 123, 72, 177, 131, 116, 44, 158, 73, 11, 65, 164, 119, 174, 34, 83, 53, 24, 42, 60, 26, 161, 68, 178, 41, 148, 109, 87, 144, 135, 20, 62, 81, 169, 124, 6, 19, 30, 163, 61, 179, 136, 97, 16, and 88.
The parity check matrix includes an A matrix which is on an upper left of the parity check matrix having g rows and K columns represented with a predetermined value g and an information length K=N×r of the LDPC code, a B matrix which has a staircase structure close to a right side of the A matrix having g rows and g columns, a Z matrix which is a zero matrix close to a right side of the B matrix having g rows and N−K−g columns, a C matrix which is close to a bottom side of the A matrix and the B matrix having N−K−g rows and K+g columns, and a D matrix which is a unit matrix close to a right side of the C matrix having N−K−g rows and N−K−g columns. The predetermined value g is 1440. The A matrix and the C matrix are expressed using a parity check matrix initial value table. The parity check matrix initial value table is a table representing positions of elements of 1 of the A matrix and the C matrix for every 360 columns, the table including
221 1011 1218 4299 7143 8728 11072 15533 17356 33909 36833
360 1210 1375 2313 3493 16822 21373 23588 23656 26267 34098
544 1347 1433 2457 9186 10945 13583 14858 19195 34606 37441
37 596 715 4134 8091 12106 24307 24658 34108 40591 42883
235 398 1204 2075 6742 11670 13512 23231 24784 27915 34752
204 873 890 13550 16570 19774 34012 35249 37655 39885 42890
221 371 514 11984 14972 15690 28827 29069 30531 31018 43121
280 549 1435 1889 3310 10234 11575 15243 20748 30469 36005
223 666 1248 13304 14433 14732 18943 21248 23127 38529 39272
370 819 1065 9461 10319 25294 31958 33542 37458 39681 40039
585 870 1028 5087 5216 12228 16216 16381 16937 27132 27893
164 167 1210 7386 11151 20413 22713 23134 24188 36771 38992
298 511 809 4620 7347 8873 19602 24162 29198 34304 41145
105 830 1212 2415 14759 15440 16361 16748 22123 32684 42575
659 665 668 6458 22130 25972 30697 31074 32048 36078 37129
91 808 953 8015 8988 13492 13987 15979 28355 34509 39698
594 983 1265 3028 4029 9366 11069 11512 27066 40939 41639
506 740 1321 1484 10747 16376 17384 20285 31502 38925 42606
338 356 975 2022 3578 18689 18772 19826 22914 24733 27431
709 1264 1366 4617 8893 25226 27800 29080 30277 37781 39644
840 1179 1338 2973 3541 7043 12712 15005 17149 19910 36795
1009 1267 1380 4919 12679 22889 29638 30987 34637 36232 37284
466 913 1247 1646 3049 5924 9014 20539 34546 35029 36540
374 697 984 1654 5870 10883 11684 20294 28888 31612 34031
117 240 635 5093 8673 11323 12456 14145 21397 39619 42559
122 1265 1427 13528 14282 15241 16852 17227 34723 36836 39791
595 1180 1310 6952 17916 24725 24971 27243 29555 32138 35987
140 470 1017 13222 13253 18462 20806 21117 28673 31598 37235
7 710 1072 8014 10804 13303 14292 16690 26676 36443 41966
48 189 759 12438 14523 16388 23178 27315 28656 29111 29694
285 387 410 4294 4467 5949 25386 27898 34880 41169 42614
474 545 1320 10506 13186 18126 27110 31498 35353 36193 37322
1075 1130 1424 11390 13312 14161 16927 25071 25844 34287 38151
161 396 427 5944 17281 22201 25218 30143 35566 38261 42513
233 247 694 1446 3180 3507 9069 20764 21940 33422 39358
271 508 1013 6271 21760 21858 24887 29808 31099 35475 39924
8 674 1329 3135 5110 14460 28108 28388 31043 31137 31863
1035 1222 1409 8287 16083 24450 24888 29356 30329 37834 39684
391 1090 1128 1866 4095 10643 13121 14499 20056 22195 30593
55 161 1402 6289 6837 8791 17937 21425 26602 30461 37241
110 377 1228 6875 13253 17032 19008 23274 32285 33452 41630
360 638 1355 5933 12593 13533 23377 23881 24586 26040 41663
535 1240 1333 3354 10860 16032 32573 34908 34957 39255 40759
526 936 1321 7992 10260 18527 28248 29356 32636 34666 35552
336 785 875 7530 13062 13075 18925 27963 28703 33688 36502
36 591 1062 1518 3821 7048 11197 17781 19408 22731 24783
214 1145 1223 1546 9475 11170 16061 21273 38688 40051 42479
1136 1226 1423 20227 22573 24951 26462 29586 34915 42441 43048
26 276 1425 6048 7224 7917 8747 27559 28515 35002 37649
127 294 437 4029 8585 9647 11904 24115 28514 36893 39722
748 1093 1403 9536 19305 20468 31049 38667 40502 40720 41949
96 638 743 9806 12101 17751 22732 24937 32007 32594 38504
649 904 1079 2770 3337 9158 20125 24619 32921 33698 35173
401 518 984 7372 12438 12582 18704 35874 39420 39503 39790
10 451 1077 8078 16320 17409 25807 28814 30613 41261 42955
405 592 1178 15936 18418 19585 21966 24219 30637 34536 37838
50 584 851 9720 11919 22544 22545 25851 35567 41587 41876
911 1113 1176 1806 10058 10809 14220 19044 20748 29424 36671
441 550 1135 1956 11254 18699 30249 33099 34587 35243 39952
510 1016 1281 8621 13467 13780 15170 16289 20925 26426 34479
4969 5223 17117 21950 22144 24043 27151 39809
11452 13622 18918 19670 23995 32647 37200 37399
6351 6426 13185 13973 16699 22524 31070 31916
4098 10617 14854 18004 28580 36158 37500 38552.
In the above-described second data processing device/method, an arrangement of the LDPC code that has undergone group-wise interleaving obtained from data transmitted from a transmitting device is returned to an original arrangement, the transmitting device including an encoding unit configured to perform LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 64800 bits and an encoding rate r of 5/15; a group-wise interleaving unit configured to perform group-wise interleaving of interleaving the LDPC code in a unit of a bit group of 360 bits; and a mapping unit configured to map the LDPC code to any one of four signal points decided using a modulation method in a unit of 2 bits. In the group-wise interleaving, setting an i+1-th bit group from a head of the LDPC code as a bit group i, arrangement of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into arrangement of bit groups
39, 47, 96, 176, 33, 75, 165, 38, 27, 58, 90, 76, 17, 46, 10, 91, 133, 69, 171, 32, 117, 78, 13, 146, 101, 36, 0, 138, 25, 77, 122, 49, 14, 125, 140, 93, 130, 2, 104, 102, 128, 4, 111, 151, 84, 167, 35, 127, 156, 55, 82, 85, 66, 114, 8, 147, 115, 113, 5, 31, 100, 106, 48, 52, 67, 107, 18, 126, 112, 50, 9, 143, 28, 160, 71, 79, 43, 98, 86, 94, 64, 3, 166, 105, 103, 118, 63, 51, 139, 172, 141, 175, 56, 74, 95, 29, 45, 129, 120, 168, 92, 150, 7, 162, 153, 137, 108, 159, 157, 173, 23, 89, 132, 57, 37, 70, 134, 40, 21, 149, 80, 1, 121, 59, 110, 142, 152, 15, 154, 145, 12, 170, 54, 155, 99, 22, 123, 72, 177, 131, 116, 44, 158, 73, 11, 65, 164, 119, 174, 34, 83, 53, 24, 42, 60, 26, 161, 68, 178, 41, 148, 109, 87, 144, 135, 20, 62, 81, 169, 124, 6, 19, 30, 163, 61, 179, 136, 97, 16, and 88.
The parity check matrix includes an A matrix which is on an upper left of the parity check matrix having g rows and K columns represented with a predetermined value g and an information length K=N×r of the LDPC code, a B matrix which has a staircase structure close to a right side of the A matrix having g rows and g columns, a Z matrix which is a zero matrix close to a right side of the B matrix having g rows and N−K−g columns, a C matrix which is close to a bottom side of the A matrix and the B matrix having N−K−g rows and K+g columns, and a D matrix which is a unit matrix close to a right side of the C matrix having N−K−g rows and N−K−g columns. The predetermined value g is 1440. The A matrix and the C matrix are expressed using a parity check matrix initial value table. The parity check matrix initial value table is a table representing positions of elements of 1 of the A matrix and the C matrix for every 360 columns, the table including
221 1011 1218 4299 7143 8728 11072 15533 17356 33909 36833
360 1210 1375 2313 3493 16822 21373 23588 23656 26267 34098
544 1347 1433 2457 9186 10945 13583 14858 19195 34606 37441
37 596 715 4134 8091 12106 24307 24658 34108 40591 42883
235 398 1204 2075 6742 11670 13512 23231 24784 27915 34752
204 873 890 13550 16570 19774 34012 35249 37655 39885 42890
221 371 514 11984 14972 15690 28827 29069 30531 31018 43121
280 549 1435 1889 3310 10234 11575 15243 20748 30469 36005
223 666 1248 13304 14433 14732 18943 21248 23127 38529 39272
370 819 1065 9461 10319 25294 31958 33542 37458 39681 40039
585 870 1028 5087 5216 12228 16216 16381 16937 27132 27893
164 167 1210 7386 11151 20413 22713 23134 24188 36771 38992
298 511 809 4620 7347 8873 19602 24162 29198 34304 41145
105 830 1212 2415 14759 15440 16361 16748 22123 32684 42575
659 665 668 6458 22130 25972 30697 31074 32048 36078 37129
91 808 953 8015 8988 13492 13987 15979 28355 34509 39698
594 983 1265 3028 4029 9366 11069 11512 27066 40939 41639
506 740 1321 1484 10747 16376 17384 20285 31502 38925 42606
338 356 975 2022 3578 18689 18772 19826 22914 24733 27431
709 1264 1366 4617 8893 25226 27800 29080 30277 37781 39644
840 1179 1338 2973 3541 7043 12712 15005 17149 19910 36795
1009 1267 1380 4919 12679 22889 29638 30987 34637 36232 37284
466 913 1247 1646 3049 5924 9014 20539 34546 35029 36540
374 697 984 1654 5870 10883 11684 20294 28888 31612 34031
117 240 635 5093 8673 11323 12456 14145 21397 39619 42559
122 1265 1427 13528 14282 15241 16852 17227 34723 36836 39791
595 1180 1310 6952 17916 24725 24971 27243 29555 32138 35987
140 470 1017 13222 13253 18462 20806 21117 28673 31598 37235
7 710 1072 8014 10804 13303 14292 16690 26676 36443 41966
48 189 759 12438 14523 16388 23178 27315 28656 29111 29694
285 387 410 4294 4467 5949 25386 27898 34880 41169 42614
474 545 1320 10506 13186 18126 27110 31498 35353 36193 37322
1075 1130 1424 11390 13312 14161 16927 25071 25844 34287 38151
161 396 427 5944 17281 22201 25218 30143 35566 38261 42513
233 247 694 1446 3180 3507 9069 20764 21940 33422 39358
271 508 1013 6271 21760 21858 24887 29808 31099 35475 39924
8 674 1329 3135 5110 14460 28108 28388 31043 31137 31863
1035 1222 1409 8287 16083 24450 24888 29356 30329 37834 39684
391 1090 1128 1866 4095 10643 13121 14499 20056 22195 30593
55 161 1402 6289 6837 8791 17937 21425 26602 30461 37241
110 377 1228 6875 13253 17032 19008 23274 32285 33452 41630
360 638 1355 5933 12593 13533 23377 23881 24586 26040 41663
535 1240 1333 3354 10860 16032 32573 34908 34957 39255 40759
526 936 1321 7992 10260 18527 28248 29356 32636 34666 35552
336 785 875 7530 13062 13075 18925 27963 28703 33688 36502
36 591 1062 1518 3821 7048 11197 17781 19408 22731 24783
214 1145 1223 1546 9475 11170 16061 21273 38688 40051 42479
1136 1226 1423 20227 22573 24951 26462 29586 34915 42441 43048
26 276 1425 6048 7224 7917 8747 27559 28515 35002 37649
127 294 437 4029 8585 9647 11904 24115 28514 36893 39722
748 1093 1403 9536 19305 20468 31049 38667 40502 40720 41949
96 638 743 9806 12101 17751 22732 24937 32007 32594 38504
649 904 1079 2770 3337 9158 20125 24619 32921 33698 35173
401 518 984 7372 12438 12582 18704 35874 39420 39503 39790
10 451 1077 8078 16320 17409 25807 28814 30613 41261 42955
405 592 1178 15936 18418 19585 21966 24219 30637 34536 37838
50 584 851 9720 11919 22544 22545 25851 35567 41587 41876
911 1113 1176 1806 10058 10809 14220 19044 20748 29424 36671
441 550 1135 1956 11254 18699 30249 33099 34587 35243 39952
510 1016 1281 8621 13467 13780 15170 16289 20925 26426 34479
4969 5223 17117 21950 22144 24043 27151 39809
11452 13622 18918 19670 23995 32647 37200 37399
6351 6426 13185 13973 16699 22524 31070 31916
4098 10617 14854 18004 28580 36158 37500 38552.
A third data processing device/method according to the present technology includes: an encoding unit/step configured to perform LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 64800 bits and an encoding rater of 5/15; a group-wise interleaving unit/step configured to perform group-wise interleaving of interleaving the LDPC code in a unit of a bit group of 360 bits; and a mapping unit/step configured to map the LDPC code to any one of 16 signal points decided using a modulation method in a unit of 4 bits. In the group-wise interleaving, setting an i+1-th bit group from a head of the LDPC code as a bit group i, arrangement of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into arrangement of bit groups
6, 14, 1, 127, 161, 177, 75, 123, 62, 103, 17, 18, 167, 88, 27, 34, 8, 110, 7, 78, 94, 44, 45, 166, 149, 61, 163, 145, 155, 157, 82, 130, 70, 92, 151, 139, 160, 133, 26, 2, 79, 15, 95, 122, 126, 178, 101, 24, 138, 146, 179, 30, 86, 58, 11, 121, 159, 49, 84, 132, 117, 119, 50, 52, 4, 51, 48, 74, 114, 59, 40, 131, 33, 89, 66, 136, 72, 16, 134, 37, 164, 77, 99, 173, 20, 158, 156, 90, 41, 176, 81, 42, 60, 109, 22, 150, 105, 120, 12, 64, 56, 68, 111, 21, 148, 53, 169, 97, 108, 35, 140, 91, 115, 152, 36, 106, 154, 0, 25, 54, 63, 172, 80, 168, 142, 118, 162, 135, 73, 83, 153, 141, 9, 28, 55, 31, 112, 107, 85, 100, 175, 23, 57, 47, 38, 170, 137, 76, 147, 93, 19, 98, 124, 39, 87, 174, 144, 46, 10, 129, 69, 71, 125, 96, 116, 171, 128, 65, 102, 5, 43, 143, 104, 13, 67, 29, 3, 113, 32, and 165.
The parity check matrix includes an A matrix which is on an upper left of the parity check matrix having g rows and K columns represented with a predetermined value g and an information length K=N×r of the LDPC code, a B matrix which has a staircase structure close to a right side of the A matrix having g rows and g columns, a Z matrix which is a zero matrix close to a right side of the B matrix having g rows and N−K−g columns, a C matrix which is close to a bottom side of the A matrix and the B matrix having N−K−g rows and K+g columns, and a D matrix which is a unit matrix close to a right side of the C matrix having N−K−g rows and N−K−g columns. The predetermined value g is 1440. The A matrix and the C matrix are expressed using a parity check matrix initial value table. The parity check matrix initial value table is a table representing positions of elements of 1 of the A matrix and the C matrix for every 360 columns, the table including
221 1011 1218 4299 7143 8728 11072 15533 17356 33909 36833
360 1210 1375 2313 3493 16822 21373 23588 23656 26267 34098
544 1347 1433 2457 9186 10945 13583 14858 19195 34606 37441
37 596 715 4134 8091 12106 24307 24658 34108 40591 42883
235 398 1204 2075 6742 11670 13512 23231 24784 27915 34752
204 873 890 13550 16570 19774 34012 35249 37655 39885 42890
221 371 514 11984 14972 15690 28827 29069 30531 31018 43121
280 549 1435 1889 3310 10234 11575 15243 20748 30469 36005
223 666 1248 13304 14433 14732 18943 21248 23127 38529 39272
370 819 1065 9461 10319 25294 31958 33542 37458 39681 40039
585 870 1028 5087 5216 12228 16216 16381 16937 27132 27893
164 167 1210 7386 11151 20413 22713 23134 24188 36771 38992
298 511 809 4620 7347 8873 19602 24162 29198 34304 41145
105 830 1212 2415 14759 15440 16361 16748 22123 32684 42575
659 665 668 6458 22130 25972 30697 31074 32048 36078 37129
91 808 953 8015 8988 13492 13987 15979 28355 34509 39698
594 983 1265 3028 4029 9366 11069 11512 27066 40939 41639
506 740 1321 1484 10747 16376 17384 20285 31502 38925 42606
338 356 975 2022 3578 18689 18772 19826 22914 24733 27431
709 1264 1366 4617 8893 25226 27800 29080 30277 37781 39644
840 1179 1338 2973 3541 7043 12712 15005 17149 19910 36795
1009 1267 1380 4919 12679 22889 29638 30987 34637 36232 37284
466 913 1247 1646 3049 5924 9014 20539 34546 35029 36540
374 697 984 1654 5870 10883 11684 20294 28888 31612 34031
117 240 635 5093 8673 11323 12456 14145 21397 39619 42559
122 1265 1427 13528 14282 15241 16852 17227 34723 36836 39791
595 1180 1310 6952 17916 24725 24971 27243 29555 32138 35987
140 470 1017 13222 13253 18462 20806 21117 28673 31598 37235
7 710 1072 8014 10804 13303 14292 16690 26676 36443 41966
48 189 759 12438 14523 16388 23178 27315 28656 29111 29694
285 387 410 4294 4467 5949 25386 27898 34880 41169 42614
474 545 1320 10506 13186 18126 27110 31498 35353 36193 37322
1075 1130 1424 11390 13312 14161 16927 25071 25844 34287 38151
161 396 427 5944 17281 22201 25218 30143 35566 38261 42513
233 247 694 1446 3180 3507 9069 20764 21940 33422 39358
271 508 1013 6271 21760 21858 24887 29808 31099 35475 39924
8 674 1329 3135 5110 14460 28108 28388 31043 31137 31863
1035 1222 1409 8287 16083 24450 24888 29356 30329 37834 39684
391 1090 1128 1866 4095 10643 13121 14499 20056 22195 30593
55 161 1402 6289 6837 8791 17937 21425 26602 30461 37241
110 377 1228 6875 13253 17032 19008 23274 32285 33452 41630
360 638 1355 5933 12593 13533 23377 23881 24586 26040 41663
535 1240 1333 3354 10860 16032 32573 34908 34957 39255 40759
526 936 1321 7992 10260 18527 28248 29356 32636 34666 35552
336 785 875 7530 13062 13075 18925 27963 28703 33688 36502
36 591 1062 1518 3821 7048 11197 17781 19408 22731 24783
214 1145 1223 1546 9475 11170 16061 21273 38688 40051 42479
1136 1226 1423 20227 22573 24951 26462 29586 34915 42441 43048
26 276 1425 6048 7224 7917 8747 27559 28515 35002 37649
127 294 437 4029 8585 9647 11904 24115 28514 36893 39722
748 1093 1403 9536 19305 20468 31049 38667 40502 40720 41949
96 638 743 9806 12101 17751 22732 24937 32007 32594 38504
649 904 1079 2770 3337 9158 20125 24619 32921 33698 35173
401 518 984 7372 12438 12582 18704 35874 39420 39503 39790
10 451 1077 8078 16320 17409 25807 28814 30613 41261 42955
405 592 1178 15936 18418 19585 21966 24219 30637 34536 37838
50 584 851 9720 11919 22544 22545 25851 35567 41587 41876
911 1113 1176 1806 10058 10809 14220 19044 20748 29424 36671
441 550 1135 1956 11254 18699 30249 33099 34587 35243 39952
510 1016 1281 8621 13467 13780 15170 16289 20925 26426 34479
4969 5223 17117 21950 22144 24043 27151 39809
11452 13622 18918 19670 23995 32647 37200 37399
6351 6426 13185 13973 16699 22524 31070 31916
4098 10617 14854 18004 28580 36158 37500 38552.
In the above-described third data processing device/method, LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 64800 bits and an encoding rate r of 5/15 is performed, group-wise interleaving of interleaving the LDPC code is performed in a unit of a bit group of 360 bits; and the LDPC code is mapped to any one of 16 signal points decided using a modulation method in a unit of 4 bits. In the group-wise interleaving, setting an i+1-th bit group from a head of the LDPC code as a bit group i, arrangement of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into arrangement of bit groups
6, 14, 1, 127, 161, 177, 75, 123, 62, 103, 17, 18, 167, 88, 27, 34, 8, 110, 7, 78, 94, 44, 45, 166, 149, 61, 163, 145, 155, 157, 82, 130, 70, 92, 151, 139, 160, 133, 26, 2, 79, 15, 95, 122, 126, 178, 101, 24, 138, 146, 179, 30, 86, 58, 11, 121, 159, 49, 84, 132, 117, 119, 50, 52, 4, 51, 48, 74, 114, 59, 40, 131, 33, 89, 66, 136, 72, 16, 134, 37, 164, 77, 99, 173, 20, 158, 156, 90, 41, 176, 81, 42, 60, 109, 22, 150, 105, 120, 12, 64, 56, 68, 111, 21, 148, 53, 169, 97, 108, 35, 140, 91, 115, 152, 36, 106, 154, 0, 25, 54, 63, 172, 80, 168, 142, 118, 162, 135, 73, 83, 153, 141, 9, 28, 55, 31, 112, 107, 85, 100, 175, 23, 57, 47, 38, 170, 137, 76, 147, 93, 19, 98, 124, 39, 87, 174, 144, 46, 10, 129, 69, 71, 125, 96, 116, 171, 128, 65, 102, 5, 43, 143, 104, 13, 67, 29, 3, 113, 32, and 165.
The parity check matrix includes an A matrix which is on an upper left of the parity check matrix having g rows and K columns represented with a predetermined value g and an information length K=N×r of the LDPC code, a B matrix which has a staircase structure close to a right side of the A matrix having g rows and g columns, a Z matrix which is a zero matrix close to a right side of the B matrix having g rows and N−K−g columns, a C matrix which is close to a bottom side of the A matrix and the B matrix having N−K−g rows and K+g columns, and a D matrix which is a unit matrix close to a right side of the C matrix having N−K−g rows and N−K−g columns. The predetermined value g is 1440. The A matrix and the C matrix are expressed using a parity check matrix initial value table. The parity check matrix initial value table is a table representing positions of elements of 1 of the A matrix and the C matrix for every 360 columns, the table including
221 1011 1218 4299 7143 8728 11072 15533 17356 33909 36833
360 1210 1375 2313 3493 16822 21373 23588 23656 26267 34098
544 1347 1433 2457 9186 10945 13583 14858 19195 34606 37441
37 596 715 4134 8091 12106 24307 24658 34108 40591 42883
235 398 1204 2075 6742 11670 13512 23231 24784 27915 34752
204 873 890 13550 16570 19774 34012 35249 37655 39885 42890
221 371 514 11984 14972 15690 28827 29069 30531 31018 43121
280 549 1435 1889 3310 10234 11575 15243 20748 30469 36005
223 666 1248 13304 14433 14732 18943 21248 23127 38529 39272
370 819 1065 9461 10319 25294 31958 33542 37458 39681 40039
585 870 1028 5087 5216 12228 16216 16381 16937 27132 27893
164 167 1210 7386 11151 20413 22713 23134 24188 36771 38992
298 511 809 4620 7347 8873 19602 24162 29198 34304 41145
105 830 1212 2415 14759 15440 16361 16748 22123 32684 42575
659 665 668 6458 22130 25972 30697 31074 32048 36078 37129
91 808 953 8015 8988 13492 13987 15979 28355 34509 39698
594 983 1265 3028 4029 9366 11069 11512 27066 40939 41639
506 740 1321 1484 10747 16376 17384 20285 31502 38925 42606
338 356 975 2022 3578 18689 18772 19826 22914 24733 27431
709 1264 1366 4617 8893 25226 27800 29080 30277 37781 39644
840 1179 1338 2973 3541 7043 12712 15005 17149 19910 36795
1009 1267 1380 4919 12679 22889 29638 30987 34637 36232 37284
466 913 1247 1646 3049 5924 9014 20539 34546 35029 36540
374 697 984 1654 5870 10883 11684 20294 28888 31612 34031
117 240 635 5093 8673 11323 12456 14145 21397 39619 42559
122 1265 1427 13528 14282 15241 16852 17227 34723 36836 39791
595 1180 1310 6952 17916 24725 24971 27243 29555 32138 35987
140 470 1017 13222 13253 18462 20806 21117 28673 31598 37235
7 710 1072 8014 10804 13303 14292 16690 26676 36443 41966
48 189 759 12438 14523 16388 23178 27315 28656 29111 29694
285 387 410 4294 4467 5949 25386 27898 34880 41169 42614
474 545 1320 10506 13186 18126 27110 31498 35353 36193 37322
1075 1130 1424 11390 13312 14161 16927 25071 25844 34287 38151
161 396 427 5944 17281 22201 25218 30143 35566 38261 42513
233 247 694 1446 3180 3507 9069 20764 21940 33422 39358
271 508 1013 6271 21760 21858 24887 29808 31099 35475 39924
8 674 1329 3135 5110 14460 28108 28388 31043 31137 31863
1035 1222 1409 8287 16083 24450 24888 29356 30329 37834 39684
391 1090 1128 1866 4095 10643 13121 14499 20056 22195 30593
55 161 1402 6289 6837 8791 17937 21425 26602 30461 37241
110 377 1228 6875 13253 17032 19008 23274 32285 33452 41630
360 638 1355 5933 12593 13533 23377 23881 24586 26040 41663
535 1240 1333 3354 10860 16032 32573 34908 34957 39255 40759
526 936 1321 7992 10260 18527 28248 29356 32636 34666 35552
336 785 875 7530 13062 13075 18925 27963 28703 33688 36502
36 591 1062 1518 3821 7048 11197 17781 19408 22731 24783
214 1145 1223 1546 9475 11170 16061 21273 38688 40051 42479
1136 1226 1423 20227 22573 24951 26462 29586 34915 42441 43048
26 276 1425 6048 7224 7917 8747 27559 28515 35002 37649
127 294 437 4029 8585 9647 11904 24115 28514 36893 39722
748 1093 1403 9536 19305 20468 31049 38667 40502 40720 41949
96 638 743 9806 12101 17751 22732 24937 32007 32594 38504
649 904 1079 2770 3337 9158 20125 24619 32921 33698 35173
401 518 984 7372 12438 12582 18704 35874 39420 39503 39790
10 451 1077 8078 16320 17409 25807 28814 30613 41261 42955
405 592 1178 15936 18418 19585 21966 24219 30637 34536 37838
50 584 851 9720 11919 22544 22545 25851 35567 41587 41876
911 1113 1176 1806 10058 10809 14220 19044 20748 29424 36671
441 550 1135 1956 11254 18699 30249 33099 34587 35243 39952
510 1016 1281 8621 13467 13780 15170 16289 20925 26426 34479
4969 5223 17117 21950 22144 24043 27151 39809
11452 13622 18918 19670 23995 32647 37200 37399
6351 6426 13185 13973 16699 22524 31070 31916
4098 10617 14854 18004 28580 36158 37500 38552.
A fourth data processing device/method according to the present technology includes: a group-wise deinterleaving unit/step configured to return an arrangement of the LDPC code that has undergone group-wise interleaving obtained from data transmitted from a transmitting device to an original arrangement, the transmitting device including an encoding unit configured to perform LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 64800 bits and an encoding rate r of 5/15, a group-wise interleaving unit configured to perform group-wise interleaving of interleaving the LDPC code in a unit of a bit group of 360 bits, and a mapping unit configured to map the LDPC code to any one of 16 signal points decided using a modulation method in a unit of 4 bits. In the group-wise interleaving, setting an i+1-th bit group from a head of the LDPC code as a bit group i, arrangement of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into arrangement of bit groups
6, 14, 1, 127, 161, 177, 75, 123, 62, 103, 17, 18, 167, 88, 27, 34, 8, 110, 7, 78, 94, 44, 45, 166, 149, 61, 163, 145, 155, 157, 82, 130, 70, 92, 151, 139, 160, 133, 26, 2, 79, 15, 95, 122, 126, 178, 101, 24, 138, 146, 179, 30, 86, 58, 11, 121, 159, 49, 84, 132, 117, 119, 50, 52, 4, 51, 48, 74, 114, 59, 40, 131, 33, 89, 66, 136, 72, 16, 134, 37, 164, 77, 99, 173, 20, 158, 156, 90, 41, 176, 81, 42, 60, 109, 22, 150, 105, 120, 12, 64, 56, 68, 111, 21, 148, 53, 169, 97, 108, 35, 140, 91, 115, 152, 36, 106, 154, 0, 25, 54, 63, 172, 80, 168, 142, 118, 162, 135, 73, 83, 153, 141, 9, 28, 55, 31, 112, 107, 85, 100, 175, 23, 57, 47, 38, 170, 137, 76, 147, 93, 19, 98, 124, 39, 87, 174, 144, 46, 10, 129, 69, 71, 125, 96, 116, 171, 128, 65, 102, 5, 43, 143, 104, 13, 67, 29, 3, 113, 32, and 165.
The parity check matrix includes an A matrix which is on an upper left of the parity check matrix having g rows and K columns represented with a predetermined value g and an information length K=N×r of the LDPC code, a B matrix which has a staircase structure close to a right side of the A matrix having g rows and g columns, a Z matrix which is a zero matrix close to a right side of the B matrix having g rows and N−K−g columns, a C matrix which is close to a bottom side of the A matrix and the B matrix having N−K−g rows and K+g columns, and a D matrix which is a unit matrix close to a right side of the C matrix having N−K−g rows and N−K−g columns. The predetermined value g is 1440. The A matrix and the C matrix are expressed using a parity check matrix initial value table. The parity check matrix initial value table is a table representing positions of elements of 1 of the A matrix and the C matrix for every 360 columns, the table including
221 1011 1218 4299 7143 8728 11072 15533 17356 33909 36833
360 1210 1375 2313 3493 16822 21373 23588 23656 26267 34098
544 1347 1433 2457 9186 10945 13583 14858 19195 34606 37441
37 596 715 4134 8091 12106 24307 24658 34108 40591 42883
235 398 1204 2075 6742 11670 13512 23231 24784 27915 34752
204 873 890 13550 16570 19774 34012 35249 37655 39885 42890
221 371 514 11984 14972 15690 28827 29069 30531 31018 43121
280 549 1435 1889 3310 10234 11575 15243 20748 30469 36005
223 666 1248 13304 14433 14732 1 8943 21248 23127 38529 39272
370 819 1065 9461 10319 25294 31958 33542 37458 39681 40039
585 870 1028 5087 5216 12228 16216 16381 16937 27132 27893
164 167 1210 7386 11151 20413 22713 23134 24188 36771 38992
298 511 809 4620 7347 8873 19602 24162 29198 34304 41145
105 830 1212 2415 14759 15440 16361 16748 22123 32684 42575
659 665 668 6458 22130 25972 30697 31074 32048 36078 37129
91 808 953 8015 8988 13492 13987 15979 28355 34509 39698
594 983 1265 3028 4029 9366 11069 11512 27066 40939 41639
506 740 1321 1484 10747 16376 17384 20285 31502 38925 42606
338 356 975 2022 3578 18689 18772 19826 22914 24733 27431
709 1264 1366 4617 8893 25226 27800 29080 30277 37781 39644
840 1179 1338 2973 3541 7043 12712 15005 17149 19910 36795
1009 1267 1380 4919 12679 22889 29638 30987 34637 36232 37284
466 913 1247 1646 3049 5924 9014 20539 34546 35029 36540
374 697 984 1654 5870 10883 11684 20294 28888 31612 34031
117 240 635 5093 8673 11323 12456 14145 21397 39619 42559
122 1265 1427 13528 14282 15241 16852 17227 34723 36836 39791
595 1180 1310 6952 17916 24725 24971 27243 29555 32138 35987
140 470 1017 13222 13253 18462 20806 21117 28673 31598 37235
7 710 1072 8014 10804 13303 14292 16690 26676 36443 41966
48 189 759 12438 14523 16388 23178 27315 28656 29111 29694
285 387 410 4294 4467 5949 25386 27898 34880 41169 42614
474 545 1320 10506 13186 18126 27110 31498 35353 36193 37322
1075 1130 1424 11390 13312 14161 16927 25071 25844 34287 38151
161 396 427 5944 17281 22201 25218 30143 35566 38261 42513
233 247 694 1446 3180 3507 9069 20764 21940 33422 39358
271 508 1013 6271 21760 21858 24887 29808 31099 35475 39924
8 674 1329 3135 5110 14460 28108 28388 31043 31137 31863
1035 1222 1409 8287 16083 24450 24888 29356 30329 37834 39684
391 1090 1128 1866 4095 10643 13121 14499 20056 22195 30593
55 161 1402 6289 6837 8791 17937 21425 26602 30461 37241
110 377 1228 6875 13253 17032 19008 23274 32285 33452 41630
360 638 1355 5933 12593 13533 23377 23881 24586 26040 41663
535 1240 1333 3354 10860 16032 32573 34908 34957 39255 40759
526 936 1321 7992 10260 18527 28248 29356 32636 34666 35552
336 785 875 7530 13062 13075 18925 27963 28703 33688 36502
36 591 1062 1518 3821 7048 11197 17781 19408 22731 24783
214 1145 1223 1546 9475 11170 16061 21273 38688 40051 42479
1136 1226 1423 20227 22573 24951 26462 29586 34915 42441 43048
26 276 1425 6048 7224 7917 8747 27559 28515 35002 37649
127 294 437 4029 8585 9647 11904 24115 28514 36893 39722
748 1093 1403 9536 19305 20468 31049 38667 40502 40720 41949
96 638 743 9806 12101 17751 22732 24937 32007 32594 38504
649 904 1079 2770 3337 9158 20125 24619 32921 33698 35173
401 518 984 7372 12438 12582 18704 35874 39420 39503 39790
10 451 1077 8078 16320 17409 25807 28814 30613 41261 42955
405 592 1178 15936 18418 19585 21966 24219 30637 34536 37838
50 584 851 9720 11919 22544 22545 25851 35567 41587 41876
911 1113 1176 1806 10058 10809 14220 19044 20748 29424 36671
441 550 1135 1956 11254 18699 30249 33099 34587 35243 39952
510 1016 1281 8621 13467 13780 15170 16289 20925 26426 34479
4969 5223 17117 21950 22144 24043 27151 39809
11452 13622 18918 19670 23995 32647 37200 37399
6351 6426 13185 13973 16699 22524 31070 31916
4098 10617 14854 18004 28580 36158 37500 38552.
In the above-described fourth data processing device/method, an arrangement of the LDPC code that has undergone group-wise interleaving obtained from data transmitted from a transmitting device is returned to an original arrangement, the transmitting device including an encoding unit configured to perform LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 64800 bits and an encoding rate r of 5/15, a group-wise interleaving unit configured to perform group-wise interleaving of interleaving the LDPC code in a unit of a bit group of 360 bits, and a mapping unit configured to map the LDPC code to any one of 16 signal points decided using a modulation method in a unit of 4 bits. In the group-wise interleaving, setting an i+1-th bit group from a head of the LDPC code as a bit group i, arrangement of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into arrangement of bit groups
6, 14, 1, 127, 161, 177, 75, 123, 62, 103, 17, 18, 167, 88, 27, 34, 8, 110, 7, 78, 94, 44, 45, 166, 149, 61, 163, 145, 155, 157, 82, 130, 70, 92, 151, 139, 160, 133, 26, 2, 79, 15, 95, 122, 126, 178, 101, 24, 138, 146, 179, 30, 86, 58, 11, 121, 159, 49, 84, 132, 117, 119, 50, 52, 4, 51, 48, 74, 114, 59, 40, 131, 33, 89, 66, 136, 72, 16, 134, 37, 164, 77, 99, 173, 20, 158, 156, 90, 41, 176, 81, 42, 60, 109, 22, 150, 105, 120, 12, 64, 56, 68, 111, 21, 148, 53, 169, 97, 108, 35, 140, 91, 115, 152, 36, 106, 154, 0, 25, 54, 63, 172, 80, 168, 142, 118, 162, 135, 73, 83, 153, 141, 9, 28, 55, 31, 112, 107, 85, 100, 175, 23, 57, 47, 38, 170, 137, 76, 147, 93, 19, 98, 124, 39, 87, 174, 144, 46, 10, 129, 69, 71, 125, 96, 116, 171, 128, 65, 102, 5, 43, 143, 104, 13, 67, 29, 3, 113, 32, and 165,
The parity check matrix includes an A matrix which is on an upper left of the parity check matrix having g rows and K columns represented with a predetermined value g and an information length K=N×r of the LDPC code, a B matrix which has a staircase structure close to a right side of the A matrix having g rows and g columns, a Z matrix which is a zero matrix close to a right side of the B matrix having g rows and N−K−g columns, a C matrix which is close to a bottom side of the A matrix and the B matrix having N−K−g rows and K+g columns, and a D matrix which is a unit matrix close to a right side of the C matrix having N−K−g rows and N−K−g columns. The predetermined value g is 1440. The A matrix and the C matrix are expressed using a parity check matrix initial value table. The parity check matrix initial value table is a table representing positions of elements of 1 of the A matrix and the C matrix for every 360 columns, the table including
221 1011 1218 4299 7143 8728 11072 15533 17356 33909 36833
360 1210 1375 2313 3493 16822 21373 23588 23656 26267 34098
544 1347 1433 2457 9186 10945 13583 14858 19195 34606 37441
37 596 715 4134 8091 12106 24307 24658 34108 40591 42883
235 398 1204 2075 6742 11670 13512 23231 24784 27915 34752
204 873 890 13550 16570 19774 34012 35249 37655 39885 42890
221 371 514 11984 14972 15690 28827 29069 30531 31018 43121
280 549 1435 1889 3310 10234 11575 15243 20748 30469 36005
223 666 1248 13304 14433 14732 18943 21248 23127 38529 39272
370 819 1065 9461 10319 25294 31958 33542 37458 39681 40039
585 870 1028 5087 5216 12228 16216 16381 16937 27132 27893
164 167 1210 7386 11151 20413 22713 23134 24188 36771 38992
298 511 809 4620 7347 8873 19602 24162 29198 34304 41145
105 830 1212 2415 14759 15440 16361 16748 22123 32684 42575
659 665 668 6458 22130 25972 30697 31074 32048 36078 37129
91 808 953 8015 8988 13492 13987 15979 28355 34509 39698
594 983 1265 3028 4029 9366 11069 11512 27066 40939 41639
506 740 1321 1484 10747 16376 17384 20285 31502 38925 42606
338 356 975 2022 3578 18689 18772 19826 22914 24733 27431
709 1264 1366 4617 8893 25226 27800 29080 30277 37781 39644
840 1179 1338 2973 3541 7043 12712 15005 17149 19910 36795
1009 1267 1389 4919 12679 22889 29638 30987 34637 36232 37284
466 913 1247 1646 3049 5924 9014 20539 34546 35029 36540
374 697 984 1654 5870 10883 11684 20294 28888 31612 34031
117 240 635 5093 8673 11323 12456 14145 21397 39619 42559
122 1265 1427 13528 14282 15241 16852 17227 34723 36836 39791
595 1180 1310 6952 17916 24725 24971 27243 29555 32138 35987
140 470 1017 13222 13253 18462 20806 21117 28673 31598 37235
7 710 1072 8014 10804 13303 14292 16690 26676 36443 41966
48 189 759 12438 14523 16388 23178 27315 28656 29111 29694
285 387 410 4294 4467 5949 25386 27898 34880 41169 42614
474 545 1320 10506 13186 18126 27110 31498 35353 36193 37322
1075 1130 1424 11390 13312 14161 16927 25071 25844 34287 38151
161 396 427 5944 17281 22201 25218 30143 35566 38261 42513
233 247 694 1446 3180 3507 9069 20764 21940 33422 39358
271 508 1013 6271 21760 21858 24887 29808 31099 35475 39924
8 674 1329 3135 5110 14460 28108 28388 31043 31137 31863
1035 1222 1409 8287 16083 24450 24888 29356 30329 37834 39684
391 1090 1128 1866 4095 10643 13121 14499 20056 22195 30593
55 161 1402 6289 6837 8791 17937 21425 26602 30461 37241
110 377 1228 6875 13253 17032 19008 23274 32285 33452 41630
360 638 1355 5933 12593 13533 23377 23881 24586 26040 41663
535 1240 1333 3354 10860 16032 32573 34908 34957 39255 40759
526 936 1321 7992 10260 18527 28248 29356 32636 34666 35552
336 785 875 7530 13062 13075 18925 27963 28703 33688 36502
36 591 1062 1518 3821 7048 11197 17781 19408 22731 24783
214 1145 1223 1546 9475 11170 16061 21273 38688 40051 42479
1136 1226 1423 20227 22573 24951 26462 29586 34915 42441 43048
26 276 1425 6048 7224 7917 8747 27559 28515 35002 37649
127 294 437 4029 8585 9647 11904 24115 28514 36893 39722
748 1093 1403 9536 19305 20468 31049 38667 40502 40720 41949
96 638 743 9806 12101 17751 22732 24937 32007 32594 38504
649 904 1079 2770 3337 9158 20125 24619 32921 33698 35173
401 518 984 7372 12438 12582 18704 35874 39420 39503 39790
10 451 1077 8078 16320 17409 25807 28814 30613 41261 42955
405 592 1178 15936 18418 19585 21966 24219 30637 34536 37838
50 584 851 9720 11919 22544 22545 25851 35567 41587 41876
911 1113 1176 1806 10058 10809 14220 19044 20748 29424 36671
441 550 1135 1956 11254 18699 30249 33099 34587 35243 39952
510 1016 1281 8621 13467 13780 15170 16289 20925 26426 34479
4969 5223 17117 21950 22144 24043 27151 39809
11452 13622 18918 19670 23995 32647 37200 37399
6351 6426 13185 13973 16699 22524 31070 31916
4098 10617 14854 18004 28580 36158 37500 38552.
A fifth data processing device/method according to the present technology includes: an encoding unit/step configured to perform LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 64800 bits and an encoding rate r of 5/15; a group-wise interleaving unit/step configured to perform group-wise interleaving of interleaving the LDPC code in a unit of a bit group of 360 bits; and a mapping unit/step configured to map the LDPC code to any one of 64 signal points decided using a modulation method in a unit of 6 bits. In the group-wise interleaving, setting an i+1-th bit group from a head of the LDPC code as a bit group i, arrangement of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into arrangement of bit groups
103, 116, 158, 0, 27, 73, 140, 30, 148, 36, 153, 154, 10, 174, 122, 178, 6, 106, 162, 59, 142, 112, 7, 74, 11, 51, 49, 72, 31, 65, 156, 95, 171, 105, 173, 168, 1, 155, 125, 82, 86, 161, 57, 165, 54, 26, 121, 25, 157, 93, 22, 34, 33, 39, 19, 46, 150, 141, 12, 9, 79, 118, 24, 17, 85, 117, 67, 58, 129, 160, 89, 61, 146, 77, 130, 102, 101, 137, 94, 69, 14, 133, 60, 149, 136, 16, 108, 41, 90, 28, 144, 13, 175, 114, 2, 18, 63, 68, 21, 109, 53, 123, 75, 81, 143, 169, 42, 119, 138, 104, 4, 131, 145, 8, 5, 76, 15, 88, 177, 124, 45, 97, 64, 100, 37, 132, 38, 44, 107, 35, 43, 80, 50, 91, 152, 78, 166, 55, 115, 170, 159, 147, 167, 87, 83, 29, 96, 172, 48, 98, 62, 139, 70, 164, 84, 47, 151, 134, 126, 113, 179, 110, 111, 128, 32, 52, 66, 40, 135, 176, 99, 127, 163, 3, 120, 71, 56, 92, 23, and 20.
The parity check matrix includes an A matrix which is on an upper left of the parity check matrix having g rows and K columns represented with a predetermined value g and an information length K=N×r of the LDPC code, a B matrix which has a staircase structure close to a right side of the A matrix having g rows and g columns, a Z matrix which is a zero matrix close to a right side of the B matrix having g rows and N−K−g columns, a C matrix which is close to a bottom side of the A matrix and the B matrix having N−K−g rows and K+g columns, and a D matrix which is a unit matrix close to a right side of the C matrix having N−K−g rows and N−K−g columns. The predetermined value g is 1440. The A matrix and the C matrix are expressed using a parity check matrix initial value table. The parity check matrix initial value table is a table representing positions of elements of 1 of the A matrix and the C matrix for every 360 columns, the table including
221 1011 1218 4299 7143 8728 11072 15533 17356 33909 36833
360 1210 1375 2313 3493 16822 21373 23588 23656 26267 34098
544 1347 1433 2457 9186 10945 13583 14858 19195 34606 37441
37 596 715 4134 8091 12106 24307 24658 34108 40591 42883
235 398 1204 2075 6742 11670 13512 23231 24784 27915 34752
204 873 890 13550 16570 19774 34012 35249 37655 39885 42890
221 371 514 11984 14972 15690 28827 29069 30531 31018 43121
280 549 1435 1889 3310 10234 11575 15243 20748 30469 36005
223 666 1248 13304 14433 14732 18943 21248 23127 38529 39272
370 819 1065 9461 10319 25294 31958 33542 37458 39681 40039
585 870 1028 5087 5216 12228 16216 16381 16937 27132 27893
164 167 1210 7386 11151 20413 22713 23134 24188 36771 38992
298 511 809 4620 7347 8873 19602 24162 29198 34304 41145
105 830 1212 2415 14759 15440 16361 16748 22123 32684 42575
659 665 668 6458 22130 25972 30697 31074 32048 36078 37129
91 808 953 8015 8988 13492 13987 15979 28355 34509 39698
594 983 1265 3028 4029 9366 11069 11512 27066 40939 41639
506 740 1321 1484 10747 16376 17384 20285 31502 38925 42606
338 356 975 2022 3578 18689 18772 19826 22914 24733 27431
709 1264 1366 4617 8893 25226 27800 29080 30277 37781 39644
840 1179 1338 2973 3541 7043 12712 15005 17149 19910 36795
1009 1267 1380 4919 12679 22889 29638 30987 34637 36232 37284
466 913 1247 1646 3049 5924 9014 20539 34546 35029 36540
374 697 984 1654 5870 10883 11684 20294 28888 31612 34031
117 240 635 5093 8673 11323 12456 14145 21397 39619 42559
122 1265 1427 13528 14282 15241 16852 17227 34723 36836 39791
595 1180 1310 6952 17916 24725 24971 27243 29555 32138 35987
140 470 1017 13222 13253 18462 20806 21117 28673 31598 37235
7 710 1072 8014 1 0804 13303 14292 16690 26676 36443 41966
48 189 759 12438 14523 16388 23178 27315 28656 29111 29694
285 387 410 4294 4467 5949 25386 27898 34880 41169 42614
474 545 1320 10506 13186 18126 27110 31498 35353 36193 37322
1075 1130 1424 11390 13312 14161 16927 25071 25844 34287 38151
161 396 427 5944 17281 22201 25218 30143 35566 38261 42513
233 247 694 1446 3180 3507 9069 20764 21940 33422 39358
271 508 1013 6271 21760 21858 24887 29808 31099 35475 39924
8 674 1329 3135 5110 14460 28108 28388 31043 31137 31863
1035 1222 1409 8287 16083 24450 24888 29356 30329 37834 39684
391 1090 1128 1866 4095 10643 13121 14499 20056 22195 30593
55 161 1402 6289 6837 8791 17937 21425 26602 30461 37241
110 377 1228 6875 13253 17032 19008 23274 32285 33452 41630
360 638 1355 5933 12593 13533 23377 23881 24586 26040 41663
535 1240 1333 3354 10860 16032 32573 34908 34957 39255 40759
526 936 1321 7992 10260 18527 28248 29356 32636 34666 35552
336 785 875 7530 13062 13075 18925 27963 28703 33688 36502
36 591 1062 1518 3821 7048 11197 17781 19408 22731 24783
214 1145 1223 1546 9475 11170 16061 21273 38688 40051 42479
1136 1226 1423 20227 22573 24951 26462 29586 34915 42441 43048
26 276 1425 6048 7224 7917 8747 27559 28515 35002 37649
127 294 437 4029 8585 9647 11904 24115 28514 36893 39722
748 1093 1403 9536 19305 20468 31049 38667 40502 40720 41949
96 638 743 9806 12101 17751 22732 24937 32007 32594 38504
649 904 1079 2770 3337 9158 20125 24619 32921 33698 35173
401 518 984 7372 12438 12582 18704 35874 39420 39503 39790
10 451 1077 8078 16320 17409 25807 28814 30613 41261 42955
405 592 1178 15936 18418 19585 21966 24219 30637 34536 37838
50 584 851 9720 11919 22544 22545 25851 35567 41587 41876
911 1113 1176 1806 10058 10809 14220 19044 20748 29424 36671
441 550 1135 1956 11254 18699 30249 33099 34587 35243 39952
510 1016 1281 8621 13467 13780 15170 16289 20925 26426 34479
4969 5223 1 7117 21950 22144 24043 27151 39809
11452 13622 18918 19670 23995 32647 37200 37399
6351 6426 13185 13973 16699 22524 31070 31916
4098 10617 14854 18004 28580 36158 37500 38552.
In the fifth data processing device/method according to the present technology, a LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 64800 bits and an encoding rate r of 5/15 is performed; group-wise interleaving of interleaving the LDPC code is performed in a unit of a bit group of 360 bits; and the LDPC code is mapped to any one of 64 signal points decided using a modulation method in a unit of 6 bits. In the group-wise interleaving, setting an i+1-th bit group from a head of the LDPC code as a bit group i, arrangement of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into arrangement of bit groups
103, 116, 158, 0, 27, 73, 140, 30, 148, 36, 153, 154, 10, 174, 122, 178, 6, 106, 162, 59, 142, 112, 7, 74, 11, 51, 49, 72, 31, 65, 156, 95, 171, 105, 173, 168, 1, 155, 125, 82, 86, 161, 57, 165, 54, 26, 121, 25, 157, 93, 22, 34, 33, 39, 19, 46, 150, 141, 12, 9, 79, 118, 24, 17, 85, 117, 67, 58, 129, 160, 89, 61, 146, 77, 130, 102, 101, 137, 94, 69, 14, 133, 60, 149, 136, 16, 108, 41, 90, 28, 144, 13, 175, 114, 2, 18, 63, 68, 21, 109, 53, 123, 75, 81, 143, 169, 42, 119, 138, 104, 4, 131, 145, 8, 5, 76, 15, 88, 177, 124, 45, 97, 64, 100, 37, 132, 38, 44, 107, 35, 43, 80, 50, 91, 152, 78, 166, 55, 115, 170, 159, 147, 167, 87, 83, 29, 96, 172, 48, 98, 62, 139, 70, 164, 84, 47, 151, 134, 126, 113, 179, 110, 111, 128, 32, 52, 66, 40, 135, 176, 99, 127, 163, 3, 120, 71, 56, 92, 23, and 20.
The parity check matrix includes an A matrix which is on an upper left of the parity check matrix having g rows and K columns represented with a predetermined value g and an information length K=N×r of the LDPC code, a B matrix which has a staircase structure close to a right side of the A matrix having g rows and g columns, a Z matrix which is a zero matrix close to a right side of the B matrix having g rows and N−K−g columns, a C matrix which is close to a bottom side of the A matrix and the B matrix having N−K−g rows and K+g columns, and a D matrix which is a unit matrix close to a right side of the C matrix having N−K−g rows and N−K−g columns. The predetermined value g is 1440. The A matrix and the C matrix are expressed using a parity check matrix initial value table. The parity check matrix initial value table is a table representing positions of elements of 1 of the A matrix and the C matrix for every 360 columns, the table including
221 1011 1218 4299 7143 8728 11072 15533 17356 33909 36833
360 1210 1375 2313 3493 16822 21373 23588 23656 26267 34098
544 1347 1433 2457 9186 10945 13583 14858 19195 34606 37441
37 596 715 4134 8091 12106 24307 24658 34108 40591 42883
235 398 1204 2075 6742 11670 13512 23231 24784 27915 34752
204 873 890 13550 16570 19774 34012 35249 37655 39885 42890
221 371 514 11984 14972 15690 28827 29069 30531 31018 43121
280 549 1435 1889 3310 10234 11575 15243 20748 30469 36005
223 666 1248 13304 14433 14732 18943 21248 23127 38529 39272
370 819 1065 9461 10319 25294 31958 33542 37458 39681 40039
585 870 1028 5087 5216 12228 16216 16381 16937 27132 27893
164 167 1210 7386 11151 20413 22713 23134 24188 36771 38992
298 511 809 4620 7347 8873 19602 24162 29198 34304 41145
105 830 1212 2415 14759 15440 16361 16748 22123 32684 42575
659 665 668 6458 22130 25972 30697 31074 32048 36078 37129
91 808 953 8015 8988 13492 13987 15979 28355 34509 39698
594 983 1265 3028 4029 9366 11069 11512 27066 40939 41639
506 740 1321 1484 10747 16376 17384 20285 31502 38925 42606
338 356 975 2022 3578 18689 18772 19826 22914 24733 27431
709 1264 1366 4617 8893 25226 27800 29080 30277 37781 39644
840 1179 1338 2973 3541 7043 12712 15005 17149 19910 36795
1009 1267 1380 4919 12679 22889 29638 30987 34637 36232 37284
466 913 1247 1646 3049 5924 9014 20539 34546 35029 36540
374 697 984 1654 5870 10883 11684 20294 28888 31612 34031
117 240 635 5093 8673 11323 12456 14145 21397 39619 42559
122 1265 1427 13528 14282 15241 16852 17227 34723 36836 39791
595 1180 1310 6952 17916 24725 24971 27243 29555 32138 35987
140 470 1017 13222 13253 18462 20806 21117 28673 31598 37235
7 710 1072 8014 10804 13303 14292 16690 26676 36443 41966
48 189 759 12438 14523 16388 23178 27315 28656 29111 29694
285 387 410 4294 4467 5949 25386 27898 34880 41169 42614
474 545 1320 10506 13186 18126 27110 31498 35353 36193 37322
1075 1130 1424 11390 13312 14161 16927 25071 25844 34287 38151
161 396 427 5944 17281 22201 25218 30143 35566 38261 42513
233 247 694 1446 3180 3507 9069 20764 21940 33422 39358
271 508 1013 6271 21760 21858 24887 29808 31099 35475 39924
8 674 1329 3135 5110 14460 28108 28388 31043 31137 31863
1035 1222 1409 8287 16083 24450 24888 29356 30329 37834 39684
391 1090 1128 1866 4095 10643 13121 14499 20056 22195 30593
55 161 1402 6289 6837 8791 17937 21425 26602 30461 37241
110 377 1228 6875 13253 17032 19008 23274 32285 33452 41630
360 638 1355 5933 12593 13533 23377 23881 24586 26040 41663
535 1240 1333 3354 10860 16032 32573 34908 34957 39255 40759
526 936 1321 7992 10260 18527 28248 29356 32636 34666 35552
336 785 875 7530 13062 13075 18925 27963 28703 33688 36502
36 591 1062 1518 3821 7048 11197 17781 19408 22731 24783
214 1145 1223 1546 9475 11170 16061 21273 38688 40051 42479
1136 1226 1423 20227 22573 24951 26462 29586 34915 42441 43048
26 276 1425 6048 7224 7917 8747 27559 28515 35002 37649
127 294 437 4029 8585 9647 11904 24115 28514 36893 39722
748 1093 1403 9536 19305 20468 31049 38667 40502 40720 41949
96 638 743 9806 12101 17751 22732 24937 32007 32594 38504
649 904 1079 2770 3337 9158 20125 24619 32921 33698 35173
401 518 984 7372 12438 12582 18704 35874 39420 39503 39790
10 451 1077 8078 16320 17409 25807 28814 30613 41261 42955
405 592 1178 15936 18418 19585 21966 24219 30637 34536 37838
50 584 851 9720 11919 22544 22545 25851 35567 41587 41876
911 1113 1176 1806 10058 10809 14220 19044 20748 29424 36671
441 550 1135 1956 11254 18699 30249 33099 34587 35243 39952
510 1016 1281 8621 13467 13780 15170 16289 20925 26426 34479
4969 5223 17117 21950 22144 24043 27151 39809
11452 13622 18918 19670 23995 32647 37200 37399
6351 6426 13185 13973 16699 22524 31070 31916
4098 10617 14854 18004 28580 36158 37500 38552.
A sixth data processing device/method according to the present technology includes: a group-wise deinterleaving unit/step configured to return an arrangement of the LDPC code that has undergone group-wise interleaving obtained from data transmitted from a transmitting device to an original arrangement, the transmitting device including an encoding unit configured to perform LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 64800 bits and an encoding rate r of 5/15, a group-wise interleaving unit configured to perform group-wise interleaving of interleaving the LDPC code in a unit of a bit group of 360 bits, and a mapping unit configured to map the LDPC code to any one of 64 signal points decided using a modulation method in a unit of 6 bits. In the group-wise interleaving, setting an i+1-th bit group from a head of the LDPC code as a bit group i, arrangement of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into arrangement of bit groups
103, 116, 158, 0, 27, 73, 140, 30, 148, 36, 153, 154, 10, 174, 122, 178, 6, 106, 162, 59, 142, 112, 7, 74, 11, 51, 49, 72, 31, 65, 156, 95, 171, 105, 173, 168, 1, 155, 125, 82, 86, 161, 57, 165, 54, 26, 121, 25, 157, 93, 22, 34, 33, 39, 19, 46, 150, 141, 12, 9, 79, 118, 24, 17, 85, 117, 67, 58, 129, 160, 89, 61, 146, 77, 130, 102, 101, 137, 94, 69, 14, 133, 60, 149, 136, 16, 108, 41, 90, 28, 144, 13, 175, 114, 2, 18, 63, 68, 21, 109, 53, 123, 75, 81, 143, 169, 42, 119, 138, 104, 4, 131, 145, 8, 5, 76, 15, 88, 177, 124, 45, 97, 64, 100, 37, 132, 38, 44, 107, 35, 43, 80, 50, 91, 152, 78, 166, 55, 115, 170, 159, 147, 167, 87, 83, 29, 96, 172, 48, 98, 62, 139, 70, 164, 84, 47, 151, 134, 126, 113, 179, 110, 111, 128, 32, 52, 66, 40, 135, 176, 99, 127, 163, 3, 120, 71, 56, 92, 23, and 20.
The parity check matrix includes an A matrix which is on an upper left of the parity check matrix having g rows and K columns represented with a predetermined value g and an information length K=N×r of the LDPC code, a B matrix which has a staircase structure close to a right side of the A matrix having g rows and g columns, a Z matrix which is a zero matrix close to a right side of the B matrix having g rows and N−K−g columns, a C matrix which is close to a bottom side of the A matrix and the B matrix having N−K−g rows and K+g columns, and a D matrix which is a unit matrix close to a right side of the C matrix having N−K−g rows and N−K−g columns. The predetermined value g is 1440. The A matrix and the C matrix are expressed using a parity check matrix initial value table. The parity check matrix initial value table is a table representing positions of elements of 1 of the A matrix and the C matrix for every 360 columns, the table including
221 1011 1218 4299 7143 8728 11072 15533 17356 33909 36833
360 1210 1375 2313 3493 16822 21373 23588 23656 26267 34098
544 1347 1433 2457 9186 10945 13583 14858 19195 34606 37441
37 596 715 4134 8091 12106 24307 24658 34108 40591 42883
235 398 1204 2075 6742 11670 13512 23231 24784 27915 34752
204 873 890 13550 16570 19774 34012 35249 37655 39885 42890
221 371 514 11984 14972 15690 28827 29069 30531 31018 43121
280 549 1435 1889 3310 10234 11575 15243 20748 30469 36005
223 666 1248 13304 14433 14732 18943 21248 23127 38529 39272
370 819 1065 9461 10319 25294 31958 33542 37458 39681 40039
585 870 1028 5087 5216 12228 16216 16381 16937 27132 27893
164 167 1210 7386 11151 20413 22713 23134 24188 36771 38992
298 511 809 4620 7347 8873 19602 24162 29198 34304 41145
105 830 1212 2415 14759 15440 16361 16748 22123 32684 42575
659 665 668 6458 22130 25972 30697 31074 32048 36078 37129
91 808 953 8015 8988 13492 13987 15979 28355 34509 39698
594 983 1265 3028 4029 9366 11069 11512 27066 40939 41639
506 740 1321 1484 10747 16376 17384 20285 31502 38925 42606
338 356 975 2022 3578 18689 18772 19826 22914 24733 27431
709 1264 1366 4617 8893 25226 27800 29080 30277 37781 39644
840 1179 1338 2973 3541 7043 12712 15005 17149 19910 36795
1009 1267 1380 4919 12679 22889 29638 30987 34637 36232 37284
466 913 1247 1646 3049 5924 9014 20539 34546 35029 36540
374 697 984 1654 5870 10883 11684 20294 28888 31612 34031
117 240 635 5093 8673 11323 12456 14145 21397 39619 42559
122 1265 1427 13528 14282 15241 16852 17227 34723 36836 39791
595 1180 1310 6952 17916 24725 24971 27243 29555 32138 35987
140 470 1017 13222 13253 18462 20806 21117 28673 31598 37235
7 710 1072 8014 10804 13303 14292 16690 26676 36443 41966
48 189 759 12438 14523 16388 23178 27315 28656 29111 29694
285 387 410 4294 4467 5949 25386 27898 34880 41169 42614
474 545 1320 10506 13186 18126 27110 31498 35353 36193 37322
1075 1130 1424 11390 13312 14161 16927 25071 25844 34287 38151
161 396 427 5944 17281 22201 25218 30143 35566 38261 42513
233 247 694 1446 3180 3507 9069 20764 21940 33422 39358
271 508 1013 6271 21760 21858 24887 29808 31099 35475 39924
8 674 1329 3135 5110 14460 28108 28388 31043 31137 31863
1035 1222 1409 8287 16083 24450 24888 29356 30329 37834 39684
391 1090 1128 1866 4095 10643 13121 14499 20056 22195 30593
55 161 1402 6289 6837 8791 17937 21425 26602 30461 37241
110 377 1228 6875 13253 17032 19008 23274 32285 33452 41630
360 638 1355 5933 12593 13533 23377 23881 24586 26040 41663
535 1240 1333 3354 10860 16032 32573 34908 34957 39255 40759
526 936 1321 7992 10260 18527 28248 29356 32636 34666 35552
336 785 875 7530 13062 13075 18925 27963 28703 33688 36502
36 591 1062 1518 3821 7048 11197 17781 19408 22731 24783
214 1145 1223 1546 9475 11170 16061 21273 38688 40051 42479
1136 1226 1423 20227 22573 24951 26462 29586 34915 42441 43048
26 276 1425 6048 7224 7917 8747 27559 28515 35002 37649
127 294 437 4029 8585 9647 11904 24115 28514 36893 39722
748 1093 1403 9536 19305 20468 31049 38667 40502 40720 41949
96 638 743 9806 12101 17751 22732 24937 32007 32594 38504
649 904 1079 2770 3337 9158 20125 24619 32921 33698 35173
401 518 984 7372 12438 12582 18704 35874 39420 39503 39790
10 451 1077 8078 16320 17409 25807 28814 30613 41261 42955
405 592 1178 15936 18418 19585 21966 24219 30637 34536 37838
50 584 851 9720 11919 22544 22545 25851 35567 41587 41876
911 1113 1176 1806 10058 10809 14220 19044 20748 29424 36671
441 550 1135 1956 11254 18699 30249 33099 34587 35243 39952
510 1016 1281 8621 13467 13780 15170 16289 20925 26426 34479
4969 5223 17117 21950 22144 24043 27151 39809
11452 13622 18918 19670 23995 32647 37200 37399
6351 6426 13185 13973 16699 22524 31070 31916
4098 10617 14854 18004 28580 36158 37500 38552.
In the above-described sixth data processing method, an arrangement of the LDPC code that has undergone group-wise interleaving obtained from data transmitted from a transmitting device is returned to an original arrangement, the transmitting device including an encoding unit configured to perform LDPC encoding based on a parity check matrix of an LDPC code having a code length N of 64800 bits and an encoding rater of 5/15, a group-wise interleaving unit configured to perform group-wise interleaving of interleaving the LDPC code in a unit of a bit group of 360 bits, and a mapping unit configured to map the LDPC code to any one of 64 signal points decided using a modulation method in a unit of 6 bits. In the group-wise interleaving, setting an i+1-th bit group from a head of the LDPC code as a bit group i, arrangement of bit groups 0 to 179 of the LDPC code of 64800 bits is interleaved into arrangement of bit groups
103, 116, 158, 0, 27, 73, 140, 30, 148, 36, 153, 154, 10, 174, 122, 178, 6, 106, 162, 59, 142, 112, 7, 74, 11, 51, 49, 72, 31, 65, 156, 95, 171, 105, 173, 168, 1, 155, 125, 82, 86, 161, 57, 165, 54, 26, 121, 25, 157, 93, 22, 34, 33, 39, 19, 46, 150, 141, 12, 9, 79, 118, 24, 17, 85, 117, 67, 58, 129, 160, 89, 61, 146, 77, 130, 102, 101, 137, 94, 69, 14, 133, 60, 149, 136, 16, 108, 41, 90, 28, 144, 13, 175, 114, 2, 18, 63, 68, 21, 109, 53, 123, 75, 81, 143, 169, 42, 119, 138, 104, 4, 131, 145, 8, 5, 76, 15, 88, 177, 124, 45, 97, 64, 100, 37, 132, 38, 44, 107, 35, 43, 80, 50, 91, 152, 78, 166, 55, 115, 170, 159, 147, 167, 87, 83, 29, 96, 172, 48, 98, 62, 139, 70, 164, 84, 47, 151, 134, 126, 113, 179, 110, 111, 128, 32, 52, 66, 40, 135, 176, 99, 127, 163, 3, 120, 71, 56, 92, 23, and 20.
The parity check matrix includes an A matrix which is on an upper left of the parity check matrix having g rows and K columns represented with a predetermined value g and an information length K=N×r of the LDPC code, a B matrix which has a staircase structure close to a right side of the A matrix having g rows and g columns, a Z matrix which is a zero matrix close to a right side of the B matrix having g rows and N−K−g columns, a C matrix which is close to a bottom side of the A matrix and the B matrix having N−K−g rows and K+g columns, and a D matrix which is a unit matrix close to a right side of the C matrix having N−K−g rows and N−K−g columns. The predetermined value g is 1440. The A matrix and the C matrix are expressed using a parity check matrix initial value table. The parity check matrix initial value table is a table representing positions of elements of 1 of the A matrix and the C matrix for every 360 columns, the table including
221 1011 1218 4299 7143 8728 11072 15533 17356 33909 36833
360 1210 1375 2313 3493 16822 21373 23588 23656 26267 34098
544 1347 1433 2457 9186 10945 13583 14858 19195 34606 37441
37 596 715 4134 8091 12106 24307 24658 34108 40591 42883
235 398 1204 2075 6742 11670 13512 23231 24784 27915 34752
204 873 890 13550 16570 19774 34012 35249 37655 39885 42890
221 371 514 11984 14972 15690 28827 29069 30531 31018 43121
280 549 1435 1889 3310 10234 11575 15243 20748 30469 36005
223 666 1248 13304 14433 14732 18943 21248 23127 38529 39272
370 819 1065 9461 10319 25294 31958 33542 37458 39681 40039
585 870 1028 5087 5216 12228 16216 16381 16937 27132 27893
164 167 1210 7386 11151 20413 22713 23134 24188 36771 38992
298 511 809 4620 7347 8873 19602 24162 29198 34304 41145
105 830 1212 2415 14759 15440 16361 16748 22123 32684 42575
659 665 668 6458 22130 25972 30697 31074 32048 36078 37129
91 808 953 8015 8988 13492 13987 15979 28355 34509 39698
594 983 1265 3028 4029 9366 11069 11512 27066 40939 41639
506 740 1321 1484 10747 16376 17384 20285 31502 38925 42606
338 356 975 2022 3578 18689 18772 19826 22914 24733 27431
709 1264 1366 4617 8893 25226 27800 29080 30277 37781 39644
840 1179 1338 2973 3541 7043 12712 15005 17149 19910 36795
1009 1267 1380 4919 12679 22889 29638 30987 34637 36232 37284
466 913 1247 1646 3049 5924 9014 20539 34546 35029 36540
374 697 984 1654 5870 10883 11684 20294 28888 31612 34031
117 240 635 5093 8673 11323 12456 14145 21397 39619 42559
122 1265 1427 13528 14282 15241 16852 17227 34723 36836 39791
595 1180 1310 6952 17916 24725 24971 27243 29555 32138 35987
140 470 1017 13222 13253 18462 20806 21117 28673 31598 37235
7 710 1072 8014 10804 13303 14292 16690 26676 36443 41966
48 189 759 12438 14523 16388 23178 27315 28656 29111 29694
285 387 410 4294 4467 5949 25386 27898 34880 41169 42614
474 545 1320 10506 13186 18126 27110 31498 35353 36193 37322
1075 1130 1424 11390 13312 14161 16927 25071 25844 34287 38151
161 396 427 5944 17281 22201 25218 30143 35566 38261 42513
233 247 694 1446 3180 3507 9069 20764 21940 33422 39358
271 508 1013 6271 21760 21858 24887 29808 31099 35475 39924
8 674 1329 3135 5110 14460 28108 28388 31043 31137 31863
1035 1222 1409 8287 16083 24450 24888 29356 30329 37834 39684
391 1090 1128 1866 4095 10643 13121 14499 20056 22195 30593
55 161 1402 6289 6837 8791 17937 21425 26602 30461 37241
110 377 1228 6875 13253 17032 19008 23274 32285 33452 41630
360 638 1355 5933 12593 13533 23377 23881 24586 26040 41663
535 1240 1333 3354 10860 16032 32573 34908 34957 39255 40759
526 936 1321 7992 10260 18527 28248 29356 32636 34666 35552
336 785 875 7530 13062 13075 18925 27963 28703 33688 36502
36 591 1062 1518 3821 7048 11197 17781 19408 22731 24783
214 1145 1223 1546 9475 11170 16061 21273 38688 40051 42479
1136 1226 1423 20227 22573 24951 26462 29586 34915 42441 43048
26 276 1425 6048 7224 7917 8747 27559 28515 35002 37649
127 294 437 4029 8585 9647 11904 24115 28514 36893 39722
748 1093 1403 9536 19305 20468 31049 38667 40502 40720 41949
96 638 743 9806 12101 17751 22732 24937 32007 32594 38504
649 904 1079 2770 3337 9158 20125 24619 32921 33698 35173
401 518 984 7372 12438 12582 18704 35874 39420 39503 39790
10 451 1077 8078 16320 17409 25807 28814 30613 41261 42955
405 592 1178 15936 18418 19585 21966 24219 30637 34536 37838
50 584 851 9720 11919 22544 22545 25851 35567 41587 41876
911 1113 1176 1806 10058 10809 14220 19044 20748 29424 36671
441 550 1135 1956 11254 18699 30249 33099 34587 35243 39952
510 1016 1281 8621 13467 13780 15170 16289 20925 26426 34479
4969 5223 17117 21950 22144 24043 27151 39809
11452 13622 18918 19670 23995 32647 37200 37399
6351 6426 13185 13973 16699 22524 31070 31916
4098 10617 14854 18004 28580 36158 37500 38552.
The data processing device may be an independent device and may be an internal block constituting one device.
According to the present technology, it is possible to ensure excellent communication quality in data transmission using LDPC codes.
Note that the effects described herein are not entirely limitative, and any effect described in the present disclosure is acceptable.
Embodiments of the present technology will be described below; however, prior to the description, an LDPC code will be described.
<LDPC Code>
The LDPC code is a linear code and it is not necessary for the LDPC code to be a binary code. However, in this case, it is assumed that the LDPC code is the binary code.
A maximum characteristic of the LDPC code is that a parity check matrix defining the LDPC code is sparse. In this case, the sparse matrix is a matrix in which the number of “1” of elements of the matrix is very small (a matrix in which most elements are 0).
In the parity check matrix H of
In encoding using the LDPC code (LDPC encoding), for example, a generation matrix G is generated on the basis of the parity check matrix H and the generation matrix G is multiplied by binary information bits, so that a code word (LDPC code) is generated.
Specifically, an encoding device that performs the LDPC encoding first calculates the generation matrix G in which an expression GHT=0 is realized, between a transposed matrix HT of the parity check matrix H and the generation matrix G. In this case, when the generation matrix G is a K×N matrix, the encoding device multiplies the generation matrix G with a bit string (vector u) of information bits including K bits and generates a code word c (=uG) including N bits. The code word (LDPC code) that is generated by the encoding device is received at a reception side through a predetermined communication path.
The LDPC code can be decoded by an algorithm called probabilistic decoding suggested by Gallager, that is, a message passing algorithm using belief propagation on a so-called Tanner graph, including a variable node (also referred to as a message node) and a check node. Hereinafter, the variable node and the check node are appropriately referred to as nodes simply.
Hereinafter, a real value (a reception LLR) that is obtained by representing the likelihood of “0” of a value of an i-th code bit of the LDPC code (one code word) received by the reception side by a log likelihood ratio is appropriately referred to as a reception value u0i. In addition, a message output from the check node is referred to as uj and a message output from the variable node is referred to as vi.
First, in decoding of the LDPC code, as illustrated in
Here, dv and dc in Expression (1) and Expression (2) are respectively parameters which can be arbitrarily selected and illustrates the number of “1” in the longitudinal direction (column) and transverse direction (row) of the parity check matrix H. For example, in the case of an LDPC code ((3, 6) LDPC code) with respect to the parity check matrix H with a column weight of 3 and a row weight of 6 as illustrated in
In the variable node operation of Expression (1) and the check node operation of Expression (2), because a message input from an edge (line coupling the variable node and the check node) for outputting the message is not an operation target, an operation range becomes 1 to dv−1 or 1 to d3−1. The check node operation of Expression (2) is performed actually by previously making a table of a function R (v1, v2) represented by Expression (3) defined by one output with respect to two inputs v1 and v2 and using the table consecutively (recursively), as represented by Expression (4).
[Math 3]
x=2 tan h−1{tan h(v1/2)tan h(v2/2)}=R(v1,v2) (3)
[Math 4]
uj=R(V1,R(v2,R(v3, . . . R(Vd
In Step S12, the variable k is incremented by “1” and the processing proceeds to Step S13. In Step S13, it is determined whether the variable k is more than the predetermined repetition decoding number of times C. When it is determined in Step S13 that the variable k is not more than C, the processing returns to Step S12 and the same processing is repeated hereinafter.
When it is determined in Step S13 that the variable k is more than C, the processing proceeds to Step S14, the message vi that corresponds to a decoding result to be finally output is calculated by performing an operation represented by Expression (5) and is output, and the decoding processing of the LDPC code ends.
In this case, the operation of Expression (5) is performed using messages uj from all edges connected to the variable node, different from the variable node operation of Expression (1).
In the parity check matrix H of
In
That is, when an element of a j-th row and an i-th column of the parity check matrix is 1, in
In a sum product algorithm that is a decoding method of the LDPC code, the variable node operation and the check node operation are repetitively performed.
In the variable node, the message vi that corresponds to the edge for calculation is calculated by the variable node operation of Expression (1) using messages u1 and u2 from the remaining edges connected to the variable node and the reception value u0i. The messages that correspond to the other edges are also calculated by the same method.
In this case, the check node operation of Expression (2) can be rewritten by Expression (6) using a relation of an expression a×b=exp{1n(|a|)+1n(|b|)}×sign(a)×sign(b). However, sign (x) is 1 in the case of x≥0 and is −1 in the case of x<0.
In x≥0, if a function ϕ(x) is defined as an expression ϕ(x)=1n(tan h(x/2)), an expression ϕ−1(x)=2 tan h−1(e−X) is realized. For this reason, Expression (6) can be changed to Expression (7).
In the check node, the check node operation of Expression (2) is performed according to Expression (7).
That is, in the check node, as illustrated in
The function ϕ(x) of Expression (7) can be represented as ϕ(x)=1n((ex+1)/(ex−1)) and ϕ(x)=ϕ−1(x) is satisfied in x>0. When the functions ϕ(x) and ϕ−1(x) are mounted to hardware, the functions ϕ(x) and ϕ−1(x) may be mounted using an LUT (Look Up Table). However, both the functions ϕ(x) and ϕ−1(x) become the same LUT.
<Configuration Example of Transmission System to which Present Disclosure is Applied>
In
For example, the transmitting device 11 transmits (broadcasts) (transfers) a program of television broadcasting, and so on. That is, for example, the transmitting device 11 encodes target data that is a transmission target such as image data and audio data as a program into LDPC codes, and, for example, transmits them through a communication path 13 such as a satellite circuit, a ground wave and a cable (wire circuit).
The receiving device 12 receives the LDPC code transmitted from the transmitting device 11 through the communication path 13, decodes the LDPC code to obtain the target data, and outputs the target data.
In this case, it is known that the LDPC code used by the transmission system of
Meanwhile, in the communication path 13, burst error or erasure may be generated. Especially in the case where the communication path 13 is the ground wave, for example, in an Orthogonal Frequency Division Multiplexing (OFDM) system, power of a specific symbol may become 0 (erasure) according to delay of an echo (paths other than a main path), under a multi-path environment in which D/U (Desired to Undesired Ratio) is 0 dB (power of Undesired=echo is equal to power of Desired=main path).
In the flutter (communication path in which delay is 0 and an echo having a Doppler frequency is added), when D/U is 0 dB, entire power of an OFDM symbol at a specific time may become 0 (erasure) by the Doppler frequency.
In addition, the burst error may be generated due to a situation of a wiring line from a receiving unit (not illustrated in the drawings) of the side of the receiving device 12 such as an antenna receiving a signal from the transmitting device 11 to the receiving device 12 or instability of a power supply of the receiving device 12.
Meanwhile, in decoding of the LDPC code, in the variable node corresponding to the column of the parity check matrix H and the code bit of the LDPC code, as illustrated in
In the decoding of the LDPC code, in the check node, the check node operation of Expression (7) is performed using the message calculated by the variable node connected to the check node. For this reason, if the number of check nodes in which error (including erasure) is generated simultaneously in (the code bits of the LDPC codes corresponding to) the plurality of connected variable nodes increases, decoding performance is deteriorated.
That is, if the two or more variable nodes of the variable nodes connected to the check node become simultaneously erasure, the check node returns a message in which the probability of a value being 0 and the probability of a value being 1 are equal to each other, to all the variable nodes. In this case, the check node that returns the message of the equal probabilities does not contribute to one decoding processing (one set of the variable node operation and the check node operation). As a result, it is necessary to increase the repetition number of times of the decoding processing, the decoding performance is deteriorated, and consumption power of the receiving device 12 that performs decoding of the LDPC code increases.
Therefore, in the transmission system of
<Example of Configuration of Transmitting Device 11>
In the transmitting device 11, one or more input streams corresponding to target data are supplied to a mode adaptation/multiplexer 111.
The mode adaptation/multiplexer 111 performs mode selection and processes such as multiplexing of one or more input streams supplied thereto, as needed, and supplies data obtained as a result to a padder 112.
The padder 112 performs necessary zero padding (insertion of Null) with respect to the data supplied from the mode adaptation/multiplexer 111 and supplies data obtained as a result to a BB scrambler 113.
The BB scrambler 113 performs base-band scrambling (BB scrambling) with respect to the data supplied from the padder 112 and supplies data obtained as a result to a BCH encoder 114.
The BCH encoder 114 performs BCH encoding with respect to the data supplied from the BB scrambler 113 and supplies data obtained as a result as LDPC target data to be an LDPC encoding target to an LDPC encoder 115.
The LDPC encoder 115 performs, for example, LDPC encoding according to a parity check matrix in which a parity matrix to be a portion corresponding to a parity bit of an LDPC code becomes a staircase (dual diagonal) structure with respect to the LDPC target data supplied from the BCH encoder 114, and outputs an LDPC code in which the LDPC target data is information bits.
That is, the LDPC encoder 115 performs the LDPC encoding to encode the LDPC target data with an LDPC such as the LDPC code (corresponding to the parity check matrix) defined in the predetermined standard of the DVB-S.2, the DVB-T.2, the DVB-C.2 or the like and outputs the LDPC code that is yet to be applied by ATSC 3.0 (corresponding to the parity check matrix) or the like obtained as a result.
The LDPC code defined in the standard of the DVB-T.2 and the LDPC code that is to be adopted by the ATSC 3.0 are an Irregular Repeat Accumulate (IRA) code and a parity matrix of the parity check matrix of the LDPC code becomes a staircase structure. The parity matrix and the staircase structure will be described later. The IRA code is described in “Irregular Repeat-Accumulate Codes”, H. Jin, A. Khandekar, and R. J. McEliece, in Proceedings of 2nd International Symposium on Turbo codes and Related Topics, pp. 1 to 8, September 2000, for example.
The LDPC code that is output by the LDPC encoder 115 is supplied to the bit interleaver 116.
The bit interleaver 116 performs bit interleaving to be described later with respect to the LDPC code supplied from the LDPC encoder 115 and supplies the LDPC code after the bit interleaving to a mapper 117.
The mapper 117 maps the LDPC code supplied from the bit interleaver 116 to a signal point representing one symbol of quadrature modulation in a unit (symbol unit) of code bits of one or more bits of the LDPC code and performs the quadrature modulation (multilevel modulation).
That is, the mapper 117 performs mapping the LDPC code supplied from the bit interleaver 116 to a signal point determined by a modulation method performing the quadrature modulation of the LDPC code, on an IQ plane (IQ constellation) defined by an I axis representing an I component of the same phase as a carrier and a Q axis representing a Q component orthogonal to the carrier, and performs the quadrature modulation.
When the number of signal points decided using a modulation method of quadrature modulation performed by the mapper 117 is 2m, code bits having m bits of an LDPC code are set as a symbol (one symbol) and the mapper 117 maps the LDPC code from the bit interleaver 116 to a signal point indicating the symbol among the 2m signal points in units of symbols.
In this case, as the modulation method of the quadrature modulation performed by the mapper 117, there are modulation methods including the modulation method defined in the standard of the DVB-T.2 or the like, and other modulation method to be adopted by the ATSC 3.0, that is, BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), 8PSK (Phase-Shift Keying), 16APSK (Amplitude Phase-Shift Keying), 32APSK, 16QAM (Quadrature Amplitude Modulation), 16QAM, 64QAM, 256QAM, 1024QAM, 4096QAM, 4PAM (Pulse Amplitude Modulation), or the like. In the mapper 117, to perform the quadrature modulation based on which modulation method is previously set according to an operation of an operator of the transmitting device 11.
Data (mapping result in which the symbol is mapped to the signal point) that is obtained by processing in the mapper 117 is supplied to the time interleaver 118.
The time interleaver 118 performs time interleaving (interleaving in a time direction) in a unit of symbol with respect to the data supplied from the mapper 117 and supplies data obtained as a result to an SISO/MISO encoder (SISO/MISO (Single Input Single Output/Multiple Input Single Output) encoder) 119.
The SISO/MISO encoder 119 performs spatiotemporal encoding with respect to the data supplied from the time interleaver 118 and supplies the data to the frequency interleaver 120.
The frequency interleaver 120 performs frequency interleaving (interleaving in a frequency direction) in a unit of symbol with respect to the data supplied from the SISO/MISO encoder 119 and supplies the data to a frame builder/resource allocation unit 131.
On the other hand, for example, control data (signaling) for transfer control such as BB signaling (Base Band Signaling) (BB Header) is supplied to the BCH encoder 121.
The BCH encoder 121 performs the BCH encoding with respect to the signaling supplied thereto and supplies data obtained as a result to an LDPC encoder 122, similar to the BCH encoder 114.
The LDPC encoder 122 sets the data supplied from the BCH encoder 121 as LDPC target data, performs the LDPC encoding with respect to the data, and supplies an LDPC code obtained as a result to a mapper 123, similar to the LDPC encoder 115.
The mapper 123 maps the LDPC code supplied from the LDPC encoder 122 to a signal point representing one symbol of quadrature modulation in a unit (symbol unit) of code bits of one or more bits of the LDPC code, performs the quadrature modulation, and supplies data obtained as a result to the frequency interleaver 124, similar to the mapper 117.
The frequency interleaver 124 performs the frequency interleaving in a unit of symbol with respect to the data supplied from the mapper 123 and supplies the data to the frame builder/resource allocation unit 131, similar to the frequency interleaver 120.
The frame builder/resource allocation unit 131 inserts symbols of pilots into necessary positions of the data (symbols) supplied from the frequency interleavers 120 and 124, configures a frame (for example, a physical layer (PL) frame, a T2 frame, a C2 frame, and so on) including symbols of a predetermined number from data (symbols) obtained as a result, and supplies the frame to an OFDM generating unit 132.
The OFDM generating unit 132 generates an OFDM signal corresponding to the frame from the frame supplied from the frame builder/resource allocation unit 131 and transmits the OFDM signal through the communication path 13 (
Here, for example, the transmitting device 11 can be configured without including part of the blocks illustrated in
<Configuration of Bit Interleaver 116>
The bit interleaver 116 has a function of interleaving data and includes a parity interleaver 23, a group-wise interleaver 24, and a block interleaver 25.
The parity interleaver 23 performs parity interleaving of interleaving a parity bit of an LDPC code from the LDPC encoder 115 to a position of another parity bit, and supplies the parity-interleaved LDPC code to the group-wise interleaver 24.
The group-wise interleaver 24 performs group-wise interleaving on the LDPC code from the parity interleaver 23, and supplies the group-wise-interleaved LDPC code to the block interleaver 25.
Here, in the group-wise interleaving, with a bit group of 360 bits of one section obtained by sectioning the LDPC code corresponding to one code in a unit of 360 bits that is equal to a unit size P to be described later from the head of the code, the LDPC code from the parity interleaver 23 is interleaved in units of bit groups.
When group-wise interleaving is performed, an error rate can be improved more than when group-wise interleaving is not performed, and as a result, excellent communication quality can be ensured in data transmission.
The block interleaver 25 performs block interleaving for inversely multiplexing the LDPC code from the group-wise interleaver 24, then makes the LDPC code corresponding to one code, for example, into a symbol having m bits that is a unit of mapping, and supplies the symbol to the mapper 117 (
Here, in block interleaving, for example, in a storage region in which columns serving as a storage region storing a predetermined number of bits in the column (longitudinal) direction are arrayed in a number equal to the number of bits m of the symbol in the row (transverse) direction, the LDPC code from the group-wise interleaver 24 is written in the column direction and read in the row direction, and thereby the LDPC code corresponding to one code is made into a symbol of m bits.
<Parity Check Matrix of LDPC Code>
The parity check matrix H becomes an LDGM (Low-Density Generation Matrix) structure and can be represented by Expression H=[HA|HT] (a matrix in which elements of the information matrix HA are set to left elements and elements of the parity matrix HT are set to right elements), using an information matrix HA of a portion corresponding to information bits among the code bits of the LDPC code and a parity matrix HT corresponding to the parity bits.
In this case, a bit number of the information bits among the code bits of one LDPC code and a bit number of the parity bits are referred to as an information length K and a parity length M, respectively, and a bit number of the code bits of one LDPC code (one code word) is referred to as a code length N (=K+M).
The information length K and the parity length M of the LDPC code having the certain code length N are determined by an encoding rate. The parity check matrix H becomes a matrix in which row×column is M×N (a matrix whose row is M and column is N). The information matrix HA becomes a matrix of M×K and the parity matrix HT becomes a matrix of M×M.
The parity matrix HT of the parity check matrix H that is used for LDPC encoding by the LDPC encoder 115 becomes the same as the parity matrix HT of the parity check matrix H of the LDPC code defined in the standard of, for example, DVB-T.2, or the like.
The parity matrix HT of the parity check matrix H of the LDPC code that is defined in the standard of the DVB-T.2 or the like becomes a staircase structure matrix (lower bidagonal matrix) in which elements of 1 are arranged in a staircase shape, as illustrated in
As described above, the LDPC code of the parity check matrix H in which the parity matrix HT becomes the staircase structure can be easily generated using the parity check matrix H.
That is, the LDPC code (one code word) is represented by a row vector c and a column vector obtained by transposing the row vector is represented by CT. In addition, a portion of information bits of the row vector c to be the LDPC code is represented by a row vector A and a portion of the parity bits is represented by a row vector T.
The row vector c can be represented by Expression c=[A|T] (a row vector in which elements of the row vector A are set to left elements and elements of the row vector T are set to right elements), using the row vector A corresponding to the information bits and the row vector T corresponding to the parity bits.
In the parity check matrix H and the row vector c=[A|T] corresponding to the LDPC code, it is necessary to satisfy Expression HcT=0. The row vector T that corresponds to the parity bits constituting the row vector c=[A|T] satisfying Expression HcT=0 can be sequentially calculated by setting elements of each row to 0, sequentially (in order) from elements of a first row of the column vector HcT in Expression HcT=0, when the parity matrix HT of the parity check matrix H=[HA|HT] becomes the staircase structure illustrated in
The column weight becomes X with respect KX columns from a first column of the parity check matrix H of the LDPC code defined in the standard of the DVB-T.2 or the like, becomes 3 with respect to the following K3 columns, becomes 2 with respect to the following (M−1) columns, and becomes 1 with respect to a final column.
In this case, KX+K3+M−1+1 is equal to the code length N.
In the standard of the DVB-T.2 or the like, LDPC codes that have code lengths N of 64800 bits and 16200 bits are defined.
With respect to the LDPC code having the code length N of 64800 bits, 11 encoding rates (nominal rates) of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10 are defined. With respect to the LDPC code having the code length N of 16200 bits, 10 encoding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9 are defined.
Hereinafter, the code length N of the 64800 bits is referred to as 64 k bits and the code length N of the 16200 is referred to as 16 k bits.
With respect to the LDPC code, an error rate tends to be low in a code bit corresponding to a column of which a column weight of the parity check matrix H is large.
In the parity check matrix H that is illustrated in
<Parity Interleaving>
The parity interleaving by the parity interleaver 23 of
As illustrated in
Meanwhile, the LDPC code that is output by the LDPC encoder 115 of
A of
In the parity matrix HT with a staircase structure, elements of 1 are adjacent in each row (excluding the first row). Therefore, in the Tanner graph of the parity matrix HD two adjacent variable nodes corresponding to a column of two adjacent elements in which the value of the parity matrix HT is 1 are connected with the same check node.
Therefore, when parity bits corresponding to two above-mentioned adjacent variable nodes become errors at the same time by burst error and erasure, and so on, the check node connected with two variable nodes (variable nodes to find a message by the use of parity bits) corresponding to those two parity bits that became errors returns message that the probability with a value of 0 and the probability with a value of 1 are equal probability, to the variable nodes connected with the check node, and therefore the performance of decoding is deteriorated. Further, when the burst length (bit number of parity bits that continuously become errors) becomes large, the number of check nodes that return the message of equal probability increases and the performance of decoding is further deteriorated.
Therefore, the parity interleaver 23 (
In this case, the information matrix HA of the parity check matrix H corresponding to the LDPC code that is output by the LDPC encoder 115 becomes a cyclic structure, similar to the information matrix of the parity check matrix H corresponding to the LDPC code defined in the standard of the DVB-T.2 or the like.
The cyclic structure means a structure in which a certain column is matched with a column obtained by cyclically shifting another column. For example, the cyclic structure includes a structure in which a position of 1 of each row of P columns becomes a position obtained by cyclically shifting a first column of the P columns in a column direction by a predetermined value, such as a value proportional to a value q obtained by dividing a parity length M, for every P columns. Hereinafter, the P columns in the cyclic structure are appropriately referred to as a unit size.
As an LDPC code defined in a standard such as DVB-T.2, as described in
The parity length M becomes a value other than primes represented by Expression M=q×P=q×360, using a value q different according to the encoding rate. Therefore, similar to the unit size P, the value q is one other than 1 and M among the divisors of the parity length M and is obtained by dividing the parity length M by the unit size P (the product of P and q to be the divisors of the parity length M becomes the parity length M).
As described above, when information length is assumed to be K, an integer equal to or greater than 0 and less than P is assumed to be x and an integer equal to or greater than 0 and less than q is assumed to be y, the parity interleaver 23 interleaves the K+qx+y+1-th code bit among code bits of an LDPC code of N bits to the position of the K+Py+x+1-th code bit as parity interleaving.
Since both of the K+qx+y+1-th code bit and the K+Py+x+1-th code bit are code bits after the K+1-th one, they are parity bits, and therefore the positions of the parity bits of the LDPC code are moved according to the parity interleaving.
According to the parity interleaving, (the parity bits corresponding to) the variable nodes connected to the same check node are separated by the unit size P, that is, 360 bits in this case. For this reason, when the burst length is less than 360 bits, the plurality of variable nodes connected to the same check node can be prevented from simultaneously becoming the error. As a result, tolerance against the burst error can be improved.
The LDPC code after the interleave for interleaving the (K+qx+y+1)-th code bit into the position of the (K+Py+x+1)-th code bit is matched with an LDPC code of a parity check matrix (hereinafter, referred to as a transformed parity check matrix) obtained by performing column replacement for replacing the (K+qx+y+1)-th column of the original parity check matrix H with the (K+Py+x+1)-th column.
In the parity matrix of the transformed parity check matrix, as illustrated in
In this case, the pseudo-cyclic structure means a structure in which a cyclic structure is formed except for a part thereof. T
he transformed parity check matrix that is obtained by performing the column replacement corresponding to the parity interleaving with respect to the parity check matrix of the LDPC code defined in the standard of the DVB-T.2 or the like becomes the pseudo-cyclic structure, not the (perfect) cyclic structure, because the number of elements of 1 is less than 1 (elements of 0 exist) in a portion (shifted matrix to be described later) of 360 rows×360 columns of a upper right corner portion of the transformed parity check matrix.
The transformed parity check matrix with respect to the parity check matrix of the LDPC code output by the LDPC encoder 115 has a pseudo-cyclic structure like the transformed parity check matrix with respect to the parity check matrix of the LDPC code defined in the standard of, for example, DVB-T.2, or the like
The transformed parity check matrix of
The LDPC encoder 115 awaits supply of the LDPC target data from the BCH encoder 114. In Step S101, the LDPC encoder 115 encodes the LDPC target data with the LDPC code and supplies the LDPC code to the bit interleaver 116. The processing proceeds to Step S102.
In Step S102, the bit interleaver 116 performs bit interleave with respect to the LDPC code supplied from the LDPC encoder 115 and supplies a symbol obtained by the bit interleave to the mapper 117. The processing proceeds to Step S103.
That is, in Step S102, in the bit interleaver 116 (
The group-wise interleaver 24 performs group-wise interleaving with respect to the LDPC code supplied from the parity interleaver 23 and supplies the LDPC code to the block interleaver 25.
The block interleaver 25 performs the block interleave with respect to the LDPC code after the group-wise interleaving is performed by the group-wise interleaver 24 and supplies a symbol of m bits obtained as a result to the mapper 117.
In Step S103, the mapper 117 maps the symbol supplied from the block interleaver 25 to any of 2m signal points determined by the modulation method of the orthogonal modulation performed by the mapper 117, performs the orthogonal modulation, and supplies data obtained as a result to the time interleaver 118.
As described above, the parity interleaving or the group-wise interleaving is performed, so that an error rate when the plurality of code bits of the LDPC code are transmitted as one symbol can be improved.
In
That is, both the parity interleaving and the group-wise interleaving can be performed by writing and reading of the code bits with respect to the memory and can be represented by a matrix to convert an address (write address) to perform writing of the code bits into an address (read address) to perform reading of the code bits.
Therefore, if a matrix obtained by multiplying a matrix representing the parity interleaving and a matrix representing the group-wise interleaving is calculated, the code bits are converted by the matrix, the parity interleaving is performed, and a group-wise interleaving result of the LDPC code after the parity interleaving can be obtained.
In addition to the parity interleaver 23 and the group-wise interleaver 24, the block interleaver 25 can be integrally configured.
That is, the block interleave executed by the block interleaver 25 can be represented by the matrix to convert the write address of the memory 31 storing the LDPC code into the read address.
Therefore, if a matrix obtained by multiplying the matrix representing the parity interleaving, the matrix representing the group-wise interleaving, and the matrix representing the block interleaving is calculated, the parity interleaving, the group-wise interleaving, and the block interleaving can be collectively executed by the matrix.
<Configuration Example of LDPC Encoder 115>
The LDPC encoder 122 of
As described in
With respect to the LDPC code having the code length N of 64800 bits, 11 encoding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10 are defined. With respect to the LDPC code having the code length N of 16200 bits, 10 encoding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9 are defined (
For example, the LDPC encoder 115 can perform encoding (error correction encoding) using the LDPC code of each encoding rate having the code length N of 64800 bits or 16200 bits, according to the parity check matrix H prepared for each code length N and each encoding rate.
The LDPC encoder 115 includes an encoding processing unit 601 and a storage unit 602.
The encoding processing unit 601 includes an encoding rate setting unit 611, an initial value table reading unit 612, a parity check matrix generating unit 613, an information bit reading unit 614, an encoding parity operation unit 615, an a control unit 616. The encoding processing unit 601 performs the LDPC encoding of LDPC target data supplied to the LDPC encoder 115 and supplies an LDPC code obtained as a result to the bit interleaver 116 (
That is, the encoding rate setting unit 611 sets the code length N and the encoding rate of the LDPC code, according to an operation of an operator.
The initial value table reading unit 612 reads a parity check matrix initial value table to be described later, which corresponds to the code length N and the encoding rate set by the encoding rate setting unit 611, from the storage unit 602.
The parity check matrix generating unit 613 generates a parity check matrix H by arranging elements of 1 of an information matrix HA corresponding to an information length K (=information length N-parity length M) according to the code length N and the encoding rate set by the encoding rate setting unit 611 in the column direction with a period of 360 columns (unit size P), on the basis of the parity check matrix initial value table read by the initial value table reading unit 612, and stores the parity check matrix H in the storage unit 602.
The information bit reading unit 614 reads (extracts) information bits corresponding to the information length K, from the LDPC target data supplied to the LDPC encoder 115.
The encoding parity operation unit 615 reads the parity check matrix H generated by the parity check matrix generating unit 613 from the storage unit 602, and generates a code word (LDPC code) by calculating parity bits for the information bits read by the information bit reading unit 614 on the basis of a predetermined expression using the parity check matrix H.
The control unit 616 controls each block constituting the encoding processing unit 601.
In the storage unit 602, a plurality of parity check matrix initial value tables that correspond to the plurality of encoding rates illustrated in
In Step S201, the encoding rate setting unit 611 determines (sets) the code length N and the encoding rate r to perform the LDPC encoding.
In Step S202, the initial value table reading unit 612 reads the previously determined parity check matrix initial value table corresponding to the code length N and the encoding rate r determined by the encoding rate setting unit 611, from the storage unit 602.
In Step S203, the parity check matrix generating unit 613 calculates (generates) the parity check matrix H of the LDPC code of the code length N and the encoding rate r determined by the encoding rate setting unit 611, using the parity check matrix initial value table read from the storage unit 602 by the initial value table reading unit 612, supplies the parity check matrix to the storage unit 602, and stores the parity check matrix in the storage unit.
In Step S204, the information bit reading unit 614 reads the information bits of the information length K (=N×r) corresponding to the code length N and the encoding rate r determined by the encoding rate setting unit 611, from the LDPC target data supplied to the LDPC encoder 115, reads the parity check matrix H calculated by the parity check matrix generating unit 613 from the storage unit 602, and supplies the information bits and the parity check matrix to the encoding parity operation unit 615.
In Step S205, the encoding parity operation unit 615 sequentially operates parity bits of a code word c that satisfies Expression (8) using the information bits and the parity check matrix H that have been read from the information bit reading unit 614.
HcT=0 (8)
In Expression (8), c represents a row vector as the code word (LDPC code) and cT represents transposition of the row vector c.
As described above, when a portion of the information bits of the row vector c as the LDPC code (one code word) is represented by a row vector A and a portion of the parity bits is represented by a row vector T, the row vector c can be represented by Expression c=[A/T], using the row vector A as the information bits and the row vector T as the parity bits.
In the parity check matrix H and the row vector c=[A|T] corresponding to the LDPC code, it is necessary to satisfy Expression HcT=0. The row vector T that corresponds to the parity bits constituting the row vector c=[A|T] satisfying Expression HcT=0 can be sequentially calculated by setting elements of each row to 0, sequentially from elements of a first row of the column vector HcT in Expression HcT=0, when the parity matrix HT of the parity check matrix H=[HA|HT] becomes the staircase structure illustrated in
If the encoding parity operation unit 615 calculates the parity bits T with respect to the information bits A from the information bit reading unit 614, the encoding parity operation unit 615 outputs the code word c=[A/T] represented by the information bits A and the parity bits T as an LDPC encoding result of the information bits A.
Then, in Step S206, the control unit 616 determines whether the LDPC encoding ends. When it is determined in Step S206 that the LDPC encoding does not end, that is, when there is LDPC target data to perform the LDPC encoding, the processing returns to Step S201 (or Step S204). Hereinafter, the processing of Steps S201 (or Step S204) to S206 is repeated.
When it is determined in Step S206 that the LDPC encoding ends, that is, there is no LDPC target data to perform the LDPC encoding, the LDPC encoder 115 ends the processing.
As described above, the parity check matrix initial value table corresponding to each code length N and each encoding rate r is prepared and the LDPC encoder 115 performs the LDPC encoding of the predetermined code length N and the predetermined encoding rate r, using the parity check matrix H generated from the parity check matrix initial value table corresponding to the predetermined code length N and the predetermined encoding rate r.
<Example of Parity Check Matrix Initial Value Table>
The parity check matrix initial value table is a table that represents positions of elements of 1 of the information matrix HA (
That is to say, the parity check matrix initial value table represents the positions of the elements of 1 of the information matrix HA at least for every 360 columns (unit size P).
In addition, as the parity check matrix H, there are a parity check matrix defined in DVB-T.2 or the like in which the (entire) parity matrix HT has the staircase structure and a parity check matrix proposed by CRC/ETRI in which a part of the parity matrix HT has the staircase structure and the rest is a diagonal matrix (unit matrix).
Hereinbelow, an expression method of a parity check matrix initial value table representing the parity check matrix defined in DVB-T.2 or the like in which the parity matrix HT has the staircase structure will be referred to as a DBV method and an expression method of a parity check matrix initial value table representing the parity check matrix proposed by CRC/ETRI will be referred to as an ETRI method.
That is,
The parity check matrix generating unit 613 (
That is,
The parity check matrix initial value table of the DVB method is the table that represents the positions of the elements of 1 of the entire information matrix HA corresponding to the information length K according to the code length N and the encoding rate r of the LDPC code for every 360 columns (unit size P). In the i-th row thereof, row numbers (row numbers when a row number of a first row of the parity check matrix H is set to 0) of elements of 1 of an 1+360×(i−1)-th column of the parity check matrix H are arranged by a number of column weights of the 1+360×(i−1)-th column.
Here, since the parity matrix HT (
A row number k+1 of the parity check matrix initial value table of the DVB method is different according to the information length K.
A relation of Expression (9) is realized between the information length K and the row number k+1 of the parity check matrix initial value table.
K=(k+1)×360 (9)
In this case, 360 of Expression (9) is the unit size P described in
In the parity check matrix initial value table of
Therefore, the column weights of the parity check matrix H that are calculated from the parity check matrix initial value table of
The first row of the parity check matrix initial value table of
The second row of the parity check matrix initial value table of
As described above, the parity check matrix initial value table represents positions of elements of 1 of the information matrix HA of the parity check matrix H for every 360 columns.
The columns other than the (1+360×(i−1))-th column of the parity check matrix H, that is, the individual columns from the (2+360×(i−1))-th column to the (360×i)-th column are arranged by cyclically shifting elements of 1 of the (1+360×(i−1))-th column determined by the parity check matrix initial value table periodically in a downward direction (downward direction of the columns) according to the parity length M.
That is, the (2+360×(i−1))-th column is obtained by cyclically shifting (1+360×(i−1))-th column in the downward direction by M/360 (=q) and the next (3+360×(i−1))-th column is obtained by cyclically shifting (1+360×(i−1))-th column in the downward direction by 2×M/360 (=2×q) (obtained by cyclically shifting (2+360×(i−1))-th column in the downward direction by M/360 (=q)).
If a numerical value of a j-th column (j-th column from the left side) of an i-th row (i-th row from the upper side) of the parity check matrix initial value table is represented as hi,j and a row number of the j-th element of 1 of the w-th column of the parity check matrix H is represented as Hw-j, the row number Hw-j of the element of 1 of the w-th column to be a column other than the (1+360×(i−1))-th column of the parity check matrix H can be calculated by Expression (10).
Hw-j=mod {hi,j+mod((w−1),P)×q,M) (10)
In this case, mod(x, y) means a remainder that is obtained by dividing x by y.
In addition, P is a unit size described above. In the embodiment, for example, similar to the standard of the DVB-S.2, the DVB-T.2, and the DVB-C.2, P is 360. In addition, q is a value M/360 that is obtained by dividing the parity length M by the unit size P (=360).
The parity check matrix generating unit 613 (
The parity check matrix generating unit 613 (
The parity check matrix of the ETRI method includes an A matrix, a B matrix, a C matrix, a D matrix, and a Z matrix.
The A matrix is a parity check matrix on the upper left side having g rows and K columns represented with the predetermined value g and the information length K of the LDPC code=code length N×encoding rate r.
The B matrix is a matrix with the staircase structure close to the right side of the A matrix, having g rows and g columns.
The C matrix is a matrix close to the bottom side of the A and B matrixes, having N−K−g rows and K+g columns.
The D matrix is a unit matrix close to the right side of the C matrix having N−K−g rows and N−K−g columns.
The Z matrix is a zero matrix (0 matrix) close to the right side of the B matrix, having g rows and N−K−g columns.
In the parity check matrix of the ETRI method including the A matrix to the D matrix and the Z matrix as described above, the A matrix and a part of the C matrix constitute an information matrix, and the B matrix, the remainder of the C matrix, the D matrix, and the Z matrix constitute a parity matrix.
Note that, since the B matrix is a matrix with the staircase structure and the D matrix is a unit matrix, the parity matrix of the parity check matrix of the ETRI method has the staircase structure in a part thereof (the portion of the B matrix) and the remaining part (the portion of the D matrix) forms a diagonal matrix (unit matrix).
The A and C matrixes have the cyclic structure for every 360 columns (unit side P), like the information matrix of the parity check matrix of the DVB method, and the parity check matrix initial value table of the ETRI method represents positions of elements of 1 of the A and C matrixes for every 360 columns.
Here, since the A matrix and the part of the C matrix constitute the information matrix as described above, the parity check matrix initial value table of the ETRI method expressing the positions of elements of 1 of the A and C matrixes for every 360 columns can be said to represent positions of elements of 1 of the information matrix HA for every 360 columns.
That is to say,
The parity check matrix initial value table of the ETRI method is a table representing the positions of the elements of 1 of the A and C matrixes for each unit size P, and in the i-th row thereof, row numbers (row numbers when a row number of a first row of the parity check matrix is set to 0) of elements of 1 of a 1+P×(i−1)-th column of the parity check matrix are arranged equal in number to column weights of the 1+P×(i−1)-th column.
Note that, in order to simplify description, the unit size P is set to, for example, 5 herein.
In addition, for the parity check matrix of the ETRI method, g=M1, M2, Q1, and Q2 are used as parameters.
g=M1 is a parameter for deciding the size of the B matrix, and is set to the value of a multiple of the unit size R By adjusting g=M1, performance of the LDPC code is changed, and when the parity check matrix is decided, it is adjusted to a predetermined value. Herein, for g=M1, 15, which is three times the unit size P=5, is set to be employed.
M2 is the value of M−M1 which is obtained by subtracting M1 from the parity length M.
Here, the information length K is N×r=50×1/2=25, and the parity length M is N−K=50−25=25, and thus M2 is M−M1=25−15=10.
Q1 is obtained according to the expression Q1=M1/P, representing the number of shifts (the number of rows) of cyclic shift of the A matrix.
That is to say, columns other than the 1+P×(i−1)-th column of the A matrix of the parity check matrix of the ETRI method, i.e., columns from the 2+P×(i−1)-th column to the P×i-th column are arranged by cyclically shifting elements of 1 of the 1+360×(i−1)-th column determined by the parity check matrix initial value table periodically in a downward direction (downward direction of the columns), and Q1 represents the number of shifts of the cyclic shift of the A matrix.
Q2 is obtained according to the expression Q2=M2/P, representing the number of shifts (the number of rows) of cyclic shift of the C matrix.
That is to say, columns other than the 1+P×(i−1)-th column of the C matrix of the parity check matrix of the ETRI method, i.e., columns from the 2+P×(i−1)-th column to the P×i-th column are arranged by cyclically shifting elements of 1 of the 1+360×(i−1)-th column determined by the parity check matrix initial value table periodically in a downward direction (downward direction of the columns), and Q2 represents the number of shifts of the cyclic shift of the C matrix.
Here, Q1 is M1/P=15/3=5, and Q2 is M2/P=10/5=2.
In the parity check matrix initial value table of
That is to say, the first row of the parity check matrix initial value table of
Here, in this case, the A matrix is a matrix having 15 rows and 25 columns (g rows and K columns) and the C matrix is a matrix having 10 rows and 40 columns (N−K−g rows and K+g columns), and thus rows having the row numbers of 0 to 14 of the parity check matrix are rows of the A matrix, and rows having the row numbers of 15 to 24 of the parity check matrix are rows of the C matrix.
Thus, among rows having the row numbers of 2, 6, and 18 (hereinafter described as rows #2, #6, and #18), the rows #2 and #6 are rows of the A matrix, and the row #18 is a row of the C matrix.
The second row of the parity check matrix initial value table of
Here, in the 6 (=1+5×(2−1))-th column of the parity check matrix, among the rows #2, #10, and #19, the rows #2 and #10 are rows of the A matrix, and the row #19 is a row of the C matrix.
The third row of the parity check matrix initial value table of
Here, in the 11 (=1+5×(3−1))-th column of the parity check matrix, the row #22 is a row of the C matrix.
Likewise, 19 in the fourth row of the parity check matrix initial value table of
As described above, the parity check matrix initial value table represents the elements of 1 of the A and C matrixes of the parity check matrix for every unit size P=5 columns.
Columns other than the 1+5×(i−1)-th columns of the A and C matrixes, i.e., columns from the 2+5×(i−1)-th column to the 5×i-th column are arranged by cyclically shifting the elements of 1 of the 1+5×(i−1)-th column determined in the parity check matrix initial table periodically in the downward direction (downward direction of the columns) according to the parameters Q1 and Q2.
That is to say, for example, the 2+5×(i−1)-th column of the A matrix is obtained by cyclically shifting the 1+5×(i−1)-th column in the downward direction by Q1 (=3), and the next 3+5×(i−1)-th column is obtained by cyclically shifting the 1+5×(i−1)-th column in the downward direction by 2×Q1 (=2×3) (cyclically shifting the 2+5×(i−1)-th column in the downward direction by Q1).
In addition, for example, the 2+5×(i−1)-th column of the C matrix is obtained by cyclically shifting the 1+5×(i−1)-th column in the downward direction by Q2 (=2), and the next 3+5×(i−1)-th column is obtained by cyclically shifting the 1+5×(i−1)-th column in the downward direction by 2×Q2 (=2×2) (cyclically shifting the 2+5×(i−1)-th column in the downward direction by Q2).
In the A matrix of
Thus, respective columns from the 2 (=2+5×(1−1))-nd column to the 5 (=5+5×(1−1))-th column are obtained by cyclically shifting their previous columns in the downward direction by Q1=3.
Further, in the A matrix of
Thus, respective columns from the 7 (=2+5×(2−1))-th column to the 10 (=5+5×(2−1))-th column are obtained by cyclically shifting their previous columns in the downward direction by Q1=3.
The parity check matrix generating unit 613 (
In addition, respective columns from the 2 (=2+5×(1−1))-nd column to the 5 (=5+5×(1−1))-th column of the C matrix are obtained by cyclically shifting their previous columns in the downward direction by Q2=2.
Further, in the C matrix of
In addition, respective columns from the 7 (=2+5×(1−1))th column to the 10 (=5+5×(2−1))-th column, respective columns from the 12 (=2+5×(3−1))-th column to the 15 (=5+5×(3−1))-th column, respective columns from the 17 (2+5×(4−1))-th column to the 20 (=5+5×(4−1))-th column, and respective columns from the 22 (=2+5×(5−1))-nd column to the 25 (5+5×(5−1))-th column are obtained by cyclically shifting their previous columns in the downward direction by Q2=2.
The parity check matrix generating unit 613 (
Further, the parity check matrix generating unit 613 disposes the Z matrix on the right side of the B matrix and the D matrix on the right side of the C matrix, thereby generating the parity check matrix illustrated in
After generating the parity check matrix of
The LDPC encoder 115 (especially, the encoding parity operation unit 615 thereof (
Here, the LDPC code generated using the parity check matrix of
The LDPC encoder 115 can perform LDPC encoding (generation of the LDPC code) using the parity check matrix of
When the LDPC encoding is performed using the parity check matrix of
The transformed parity check matrix is represented by a combination of a P×P unit matrix, a quasi unit matrix in which one or more 1s of the unit matrix are set to zero, a shifted matrix obtained by cyclically shifting the unit matrix or the quasi unit matrix, a sum matrix of two or more matrixes of the unit matrix, the quasi unit matrix, and the shifted matrix, and a P×P zero matrix as will be described below.
By using the transformed parity check matrix in decoding of the LDPC code, an architecture in which check node operations and variable node operations are simultaneously performed P times can be used in decoding of the LDPC code as will be described below.
<New LDPC Code>
At present, a standard for terrestrial digital television broadcasting called ATSC 3.0 is being developed.
Thus, a novel LDPC code (hereinafter also referred to as a new LDPC code) which can be used in ATSC 3.0 and other data transmission will be described.
As the new LDPC code, for example, an LDPC code of the DVB method or an LDPC code of the ETRI method corresponding to a parity check matrix having the cyclic structure and the unit size P of 360 the same as that of DVB-T.2 or the like.
The LDPC encoder 115 (
In this case, the storage unit 602 of the LDPC encoder 115 (
Note that
Note that
Note that
Note that
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Note that
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Note that
Among new LDPC codes, the Sony code is an LDPC code with particularly good performance.
Here, the LDPC code of good performance is an LDPC code obtained from an appropriate parity check matrix H.
Moreover, the appropriate parity check matrix H is a parity check matrix that satisfies a predetermined condition to make BER (bit error rate) (and FER (frame error rate)) smaller when an LDPC code obtained from the parity check matrix H is transmitted at low Es/N0 or Eb/N0 (signal-to-noise power ratio per bit).
For example, the appropriate parity check matrix H can be found by performing simulation to measure BER when LDPC codes obtained from various parity check matrices that satisfy a predetermined condition are transmitted at low Es/N0.
As a predetermined condition to be satisfied by the appropriate parity check matrix H, for example, an analysis result obtained by a code performance analysis method called density evolution (Density Evolution) is excellent, and a loop of elements of 1 does not exist, which is called cycle 4, and so on.
Here, in the information matrix HA, it is known that the decoding performance of LDPC code is deteriorated when elements of 1 are dense like cycle 4, and therefore it is requested that cycle 4 does not exist, as a predetermined condition to be satisfied by the appropriate parity check matrix H.
Here, the predetermined condition to be satisfied by the appropriate parity check matrix H can be arbitrarily determined from the viewpoint of the improvement in the decoding performance of LDPC code and the facilitation (simplification) of decoding processing of LDPC code, and so on.
The density evolution is a code analysis method that calculates the expectation value of the error probability of the entire LDPC code (ensemble) with a code length N of ∞ characterized by a degree sequence described later.
For example, when the dispersion value of noise is gradually increased from 0 on the AWGN channel, the expectation value of the error probability of a certain ensemble is 0 first, but, when the dispersion value of noise becomes equal to or greater than a certain threshold, it is not 0.
According to the density evolution, by comparison of the threshold of the dispersion value of noise (which may also be called a performance threshold) in which the expectation value of the error probability is not 0, it is possible to decide the quality of ensemble performance (appropriateness of the parity check matrix).
Here, as for a specific LDPC code, when an ensemble to which the LDPC code belongs is decided and density evolution is performed for the ensemble, rough performance of the LDPC code can be expected.
Therefore, if an ensemble of good performance is found, an LDPC code of good performance can be found from LDPC codes belonging to the ensemble.
Here, the above-mentioned degree sequence shows at what percentage a variable node or check node having the weight of each value exists with respect to the code length N of an LDPC code.
For example, a regular (3,6) LDPC code with an encoding rate of 1/2 belongs to an ensemble characterized by a degree sequence in which the weight (column weight) of all variable nodes is 3 and the weight (row weight) of all check nodes is 6.
In the Tanner graph of
Three branches (edge) equal to the column weight are connected with each variable node, and therefore there are totally 3N branches connected with N variable nodes.
Moreover, six branches (edge) equal to the row weight are connected with each check node, and therefore there are totally 3N branches connected with N/2 check nodes.
In addition, there is one interleaver in the Tanner graph in
The interleaver randomly rearranges 3N branches connected with N variable nodes and connects each rearranged branch with any of 3N branches connected with N/2 check nodes.
There are (3N)! (=(3N)×(3N−1)× . . . ×1) rearrangement patterns to rearrange 3N branches connected with N variable nodes in the interleaver. Therefore, an ensemble characterized by the degree sequence in which the weight of all variable nodes is 3 and the weight of all check nodes is 6, becomes aggregation of (3N)! LDPC codes.
In simulation to find an LDPC code of good performance (appropriate parity check matrix), an ensemble of a multi-edge type is used in the density evolution.
In the multi edge type, an interleaver through which the branches connected with the variable nodes and the branches connected with the check nodes pass, is divided into plural (multi edge), and, by this means, the ensemble is characterized more strictly.
In the Tanner graph of
Moreover, in the Tanner graph chart of
Furthermore, in the Tanner graph chart of
Here, for example, the density evolution and the mounting thereof are described in “On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit”, S. Y. Chung, G. D. Forney, T. J. Richardson, R. Urbanke, IEEE Communications Leggers, VOL. 5, NO. 2, February 2001.
In simulation to find (a parity check matrix initial value table of) a Sony code, by the density evaluation of the multi-edge type, an ensemble in which a performance threshold that is Eb/N0 (signal-to-noise power ratio per bit) with deteriorating (decreasing) BER is equal to or less than a predetermined value is found, and an LDPC code that decreases BER in case of using one or more orthogonal modulation, such as QPSK, is selected from LDPC codes belonging to the ensemble as an LDPC code of good performance.
The parity check matrix initial value table of a Sony code is obtained from the simulation as described above.
Thus, according to a Sony code obtained from the parity check matrix initial value table, excellent communication quality can be ensured in data transmission.
As minimum cycle lengths of the parity check matrix H of the Sony codes with (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15) are values all exceeding cycle 4, cycle 4 is not present (a loop of elements of 1 with a loop length of 4). Here, a minimum cycle length (girth) means a minimum value of the length of a loop (loop length) constituted by elements of 1 in a parity check matrix H.
In addition, a performance threshold value of the Sony code with (16 k, 8/15) is set to 0.805765, a performance threshold value of the Sony code with (16 k, 10/15) to 2.471011, and a performance threshold value of the Sony code with (16 k, 12/15) to 4.269922, respectively.
KX1 columns from the first column of the parity check matrix H of the Sony codes with (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15) are set to have the column weight of X1, the next KX2 columns to have the column weight of X2, the next KY1 columns to have the column weight of Y1, the next KY2 columns to have the column weight of Y2, the next M−1 columns to have the column weight of 2, and the final one column to have the column weight of 1.
Here, KX1+KX2+KY1+KY2+M−1+1 is equal to a code length N=16200 bits of the Sony codes with (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15).
The number of columns KX1, KX2, KY1, KY2, and M and the column weights X1, X2, Y1, and Y2 of the parity check matrix H of the Sony codes with (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15) are set as illustrated in
With respect to the parity check matrix H of the Sony codes with (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15), columns on the head side (left side) tend to have a greater column weight, like the parity check matrixes described with reference to
According to simulations performed by the present applicant, satisfactory BER/FER are obtained with respect to the Sony codes with (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15), and thus excellent communication quality can be ensured in data transmission using the Sony codes with (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15).
Minimum cycle lengths of the parity check matrix H of the Sony codes with (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15) all have values exceeding cycle 4, and thus cycle 4 is not present.
In addition, a performance threshold value of the Sony code with (64 k, 7/15) is set to −0.093751, a performance threshold value of the Sony code with (64 k, 9/15) to 1.658523, a performance threshold value of the Sony code with (64 k, 11/15) to 3.351930, and a performance threshold value of the Sony code with (64 k, 13/15) to 5.301749.
KX1 columns from the first column of the parity check matrix H of the Sony codes with (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15) are set to have the column weight of X1, the next KX2 columns to have the column weight of X2, the next KY1 columns to have the column weight of Y1, the next KY2 columns to have the column weight of Y2, the next M−1 columns to have the column weight of 2, and the final one column to have the column weight of 1.
Here, KX1+KX2+KY1+KY2+M−1+1 is equal to a code length N=64800 bits of the Sony codes with (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15).
The number of columns KX1, KX2, KY1, KY2, and M and the column weights X1, X2, Y1, and Y2 of the parity check matrix H of the Sony codes with (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15) are set as illustrated in
With respect to the parity check matrix H of the Sony codes with (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15), columns on the head side (left side) tend to have a greater column weight, like the parity check matrixes described with reference to
According to simulations performed by the present applicant, satisfactory BER/FER are obtained with respect to the Sony codes with (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15), and thus excellent communication quality can be ensured in data transmission using the Sony codes with (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15).
KX1 columns from the first column of the parity check matrix H of the Samsung codes with (64 k, 6/15), (64 k, 8/15), and (64 k, 12/15) are set to have the column weight of X1, the next KX2 columns to have the column weight of X2, the next KY1 columns to have the column weight of Y1, the next KY2 columns to have the column weight of Y2, the next M−1 columns to have the column weight of 2, and the final one column to have the column weight of 1.
Here, KX1+KX2+KY1+KY2+M−1+1 is equal to a code length N=64800 bits of the Samsung codes with (64 k, 6/15), (64 k, 8/15), and (64 k, 12/15).
The number of columns KX1, KX2, KY1, KY2, and M and the column weights X1, X2, Y1, and Y2 of the parity check matrix H of the Samsung codes with (64 k, 6/15), (64 k, 8/15), and (64 k, 12/15) are set as illustrated in
KX1 columns from the first column of the parity check matrix H of the LGE codes with (16 k, 6/15), (16 k, 7/15), (16 k, 9/15), (16 k, 11/15), and (16 k, 13/15) are set to have the column weight of X1, the next KX2 columns to have the column weight of X2, the next KY1 columns to have the column weight of Y1, the next KY2 columns to have the column weight of Y2, the next M−1 columns to have the column weight of 2, and the final one column to have the column weight of 1.
Here, KX1+KX2+KY1+KY2+M−1+1 is equal to a code length N=64800 bits of the LGE codes with (16 k, 6/15), (16 k, 7/15), (16 k, 9/15), (16 k, 11/15), and (16 k, 13/15).
The number of columns KX1, KX2, KY1, KY2, and M and the column weights X1, X2, Y1, and Y2 of the parity check matrix H of the LGE codes with (16 k, 6/15), (16 k, 7/15), (16 k, 9/15), (16 k, 11/15), and (16 k, 13/15) are set as illustrated in
KX1 columns from the first column of the parity check matrix H of the LGE codes with (64 k, 10/15) are set to have the column weight of X1, the next KX2 columns to have the column weight of X2, the next KY1 columns to have the column weight of Y1, the next KY2 columns to have the column weight of Y2, the next M−1 columns to have the column weight of 2, and the final one column to have the column weight of 1.
Here, KX1+KX2+KY1+KY2+M−1+1 is equal to a code length N=64800 bits of the LGE codes with (64 k, 10/15).
The number of columns KX1, KX2, KY1, KY2, and M and the column weights X1, X2, Y1, and Y2 of the parity check matrix H of the LGE codes with (64 k, 10/15) are set as illustrated in
KX1 columns from the first column of the parity check matrix H of the NERC codes with (64 k, 9/15) are set to have the column weight of X1, the next KX2 columns to have the column weight of X2, the next KY1 columns to have the column weight of Y1, the next KY2 columns to have the column weight of Y2, the next M−1 columns to have the column weight of 2, and the final one column to have the column weight of 1.
Here, KX1+KX2+KY1+KY2+M−1+1 is equal to a code length N=64800 bits of the NERC codes with (64 k, 9/15).
The number of columns KX1, KX2, KY1, KY2, and M and the column weights X1, X2, Y1, and Y2 of the parity check matrix H of the NERC codes with (64 k, 9/15) are set as illustrated in
For the parity check matrix H of the ETRI code with (16 k, 5/15), the parameter g=M1 is set to 720.
In addition, since the code length N of the ETRI code with (16 k, 5/15) is 16200 and the encoding rate r is 5/15, the information length K=N×r is 16200×5/15=5400, and the parity length M=N−K is 16200−5400=10800.
Further, the parameter M2=M−M1=N−K−g is 10800−720=10080.
Thus, the parameter Q1=M1/P is 720/360=2, and the parameter Q2=M2/P is 10080/360=28.
The parameters g=M1, M2, Q1, and Q2 of the parity check matrix H of ETRI codes with (64 k, 5/15), (64 k, 6/15), and (64 k, 7/15) are set as illustrated in
<Constellation>
In the transmission system of
In ATSC 3.0, with regard to MODCOD that is a combination of a modulation method and an LDPC code, constellations to be used in MODCOD are set.
Here, in ATSC 3.0, five types of modulation methods of QPSK, 16QAM, 64QAM, 256QAM, and 1024QAM (1 kQAM) are scheduled to be adopted.
In addition, in ATSC 3.0, for each of two types of code lengths N of 16 k bits and 64 k bits, LDPC codes with 9 types of encoding rates r of 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12/15, and 13/15, i.e., 9×2=18 types of LDPC codes, are scheduled to be adopted.
In ATSC 3.0, the 18 types of LDPC codes are classified into 9 types according to an encoding rate r (not according to the code length N), the 9 types of LDPC codes (respective LDPC codes with the encoding rates r or 5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12/15, and 13/15) and 5 types of modulation methods form 45 combinations (9×5), and the combinations are scheduled to be adopted as MODCOD.
In addition, in ATSC 3.0, one or more constellations are scheduled to be adopted for one piece of MODCOD.
Among constellations, there are uniform constellations (UCs) which have uniform arrangement of signal points and non-uniform constellations (NUCs) which have non-uniform arrangement thereof.
In addition, among NUCs, for example, there are constellations called 1-dimensional M2-QAM non-uniform constellations (1D NUCs), constellations called 2-dimensional QQAM non-uniform constellations (2D NUCs), and the like.
In general, a 1D NUC has a more improved BER than a UC, and further, a 2D NUM has a more improved BER than a 1D NUC.
A UC is adopted as a constellation of QPSK. In addition, as a constellation of 16QAM, 64QAM, and 256QAM, for example, a 2D NUC is adopted, and as constellations of 1024QAM, for example, a 1D NUC and a 2D NUC are adopted.
Hereinbelow, a constellation of an NUC of which the modulation method is a modulation method of matching an m-bit symbol to any of 2m signal points used in MODCOD in which an encoding rate of an LDPC code is r is also described as NUC_2m_r (here, m=2, 4, 6, 8, and 10).
For example, “NUC_16_6/15” indicates a constellation of an NUC of which the modulation method is 16QAM used in MODCOD in which an encoding rate r of an LDPC code is 6/15.
In ATSC 3.0, the same constellation is scheduled to be used for the encoding rate r of the 9 types of LDPC codes when the modulation method is QPSK.
In addition, in ATSC 3.0, different constellations of the 2D NUC are scheduled to be used for respective encoding rates r of the 9 types of LDPC codes when the modulation method is 16QAM, 64QAM, or 256QAM.
Further, in ATSC 3.0, different constellations of the 1D NUC or 2D NUC are scheduled to be used for respective encoding rates r of the 9 types of LDPC codes when the modulation method is 1024QAM.
Thus, in ATSC 3.0, 1 type of constellation is scheduled to be prepared for QPSK, 9 types of constellations of 2D NUCs for 16QAM, 64QAM, and 256QAM, and a total of 18 types of constellations including 9 types of 1D NUCs and 9 types of 2D NUCs for 1024QAM.
In
In addition, in
In
In
In
In
In
In the 2D NUC, a signal point of a second quadrant of a constellation is disposed at the position obtained by symmetrically moving the signal point of the first quadrant about the Q axis, and a signal point of a third quadrant of the constellation is disposed at the position obtained by symmetrically moving the signal point of the first quadrant about the origin. In addition, a signal point of the fourth quadrant of the constellation is disposed at the position obtained by symmetrically moving the signal point of the first quadrant about the I axis.
Here, when the modulation method is 2mQAM, by setting m bits as one symbol, the one symbol is mapped to a signal point corresponding to the symbol.
The m-bit symbol is expressed by, for example, an integer of 0 to 2m−1; however, if b=2m/4 is set, symbols y(0), y(1), . . . , and y(2m−1), each of which is expressed by an integer of 0 to 2m−1, can be divided into four groups of symbols y(0) to y(b−1), y(b) to y(2b−1), y(2b) to y(3b−1), and y(3b) to y(4b−1).
In
In addition, the coordinates of a signal point corresponding to a symbol y(k+b) in the range of symbols y(b) to y(2b−1) are expressed as −conj(w#k), and the coordinates of a signal point corresponding to a symbol y(k+2b) in the range of symbols y(2b) to y(3b−1) are expressed as conj (w#k). In addition, the coordinates of a signal point corresponding to a symbol y(k+3b) in the range of symbols y(3b) to y(4b−1) are expressed as −w#k.
Here, conj (w#k) indicates the complex conjugate of w#k.
For example, when the modulation method is 16QAM, symbols y(0), (1), . . . , and y(15) with m=4 bits under a condition of b=24/4=4 are divided into four groups of symbols y(0) to y(3), y(4) to y(7), y(8) to y(11), and y(12) to y(15).
Then, among the symbols y(0) to y(15), the symbol y(12) is the symbol y(k+3b)=y(0+3×4) in the range of the symbols y(3b) to y(4b−1) with k=0, and thus the coordinates of the signal point corresponding to the symbol y(12) are −w#k=−w0.
When the encoding rate r of an LDPC code is, for example, 9/15, w0 for which the modulation method is 16QAM and the encoding rate r is 9/15 (NUC_16_9/15) is 0.4967+1.1932i according to
In
u#k represents a real part Re (zq) and an imaginary part Im (zq) of a complex number as the coordinates of a signal point zq of the 1D NUC.
Here, the 10-bit symbol y of 1024QAM is set to be expressed as y0,q, y1,q, y2,q, y3,q, y4,q, y5,q, y6,q, y7,q, y8,q, and y9,q in order from the head bit (most significant bit).
A of
B of
When the 10-bit symbol y=(y0,q, y1,q, y2,q, y3,q, y4,q, y5,q, y6,q, y7,q, y8,q, and y9,q) of 1024QAM is, for example, (0, 0, 1, 0, 0, 1, 1, 1, 0, 0), the odd-numbered 5 bits (y0,q, y2,q, y4,q, y6,q, and y8,q) are (0, 1, 0, 1, 0), and the even-numbered 5 bits (y1,q, y3,q, y5,q, y7,q, and y9,q) are (0, 0, 1, 1, 0).
In A of
In addition, in B of
On the other hand, when the encoding rate r of the LDPC code is, for example, 7/15, with regard to the 1D NUC (NUC_1k_7/15) used when the modulation method is 1024QAM and the encoding rate of the LDPC code is r=7/15, u3 is 1.04 and u11 is 6.28 according to
Thus, the real part Re (zq) of the signal point zq corresponding to the symbol y=(0, 0, 1, 0, 0, 1, 1, 1, 0, 0) is u3=1.04 and Im (zq) thereof is u11=6.28. As a result, the coordinate of the signal point zq corresponding to the symbol y=(0, 0, 1, 0, 0, 1, 1, 1, 0, 0) is expressed as 1.04+6.28i.
Note that signal points of the 1D NUC are arranged in a grid shape on a straight line parallel to the I axis or on a straight line parallel to the Q axis. An interval between the signal points, however, is not fixed. In addition, in transmission of (data mapped to) signal points, average power of the signal points on a constellation is normalized. The normalization is performed by multiplying the square mean value of the absolute values of (the coordinates of) the signal points of the constellation expressed as Pave and the reciprocal 1/(√Pave) the square root √Pave of the square mean value Pave by each signal point zq on the constellation.
According to the constellations described in
<Block Interleaver 25>
The block interleaver 25 has a storage region called a part 1 and a storage region called a part 2.
Both the parts 1 and 2 are configured to have columns arranged therein each serving as a storage region storing 1 bit in the row (horizontal) direction and a predetermined number of bits in the column (vertical) direction, and the number of columns arranged in the row direction is C which is equal to the number of bits m of a symbol.
When the number of bits stored in a column of the part 1 in the column direction (hereinafter also referred to as a part column length) is denoted as R1 and a part column length of a column of the part 2 is denoted as R2, (R1+R2)×C is equal to an encoding length N of an LDPC code that is a subject of block interleaving (which is 64800 bits or 16200 bits in the present embodiment).
In addition, the part column length R1 is equal to a multiple of 360 bits that is the unit size P, and the part column length R2 is equal to the remainder obtained when the sum of the part column length R1 of the part 1 and the part column length R2 of the part 2 (hereinafter also referred to as a column length), R1+R2, is divided by 360 bits that is the unit size P.
Here, the column length R1+R2 is equal to the value obtained by dividing the code length N of the LDPC code that is a subject of block interleaving by the number of bits m of a symbol.
For example, when 16QAM is adopted as the modulation method for an LDPC code having a code length N of 16200 bits, the number of bits m of a symbol is 4 bits, and thus the column length R1+R2 is 4050 (=16200/4).
Further, since the remainder obtained when the column length R1+R2=4050 is divided by 360 bits that is the unit size P is 90, the part column length R2 of the part 2 is 90 bits.
Then, the part column length R1 of the part 1 is R1+R2−R2=4050−90=3960 bits.
In
The block interleaver 25 performs block interleaving by writing and reading an LDPC code with respect to the parts 1 and 2.
That is to say, in block interleaving, writing code bits of an LDPC code of one code word from the top to the bottom of the columns of the part 1 (in the column direction) is performed for the columns from the left to the right direction, as illustrated in A of
Then, when the writing of the code bits is completed to the bottom of the rightmost column (the C-th column) among the columns of the part 1, writing of the remaining code bits from the top to the bottom of each column (column direction) of the part 2 is performed for the columns from the left to the right.
Then, the writing of the code bits is completed to the bottom of the rightmost column (the C-th column) among the columns of the part 2, and the code bits are read from the first row of all C of the columns of the part 1 in the row direction in units of C=m bits, as illustrated in B of
Then, reading of the code bits from all C of the columns of the part 1 is sequentially performed toward the lower rows, and when the reading is completed to the final R1-th row, the code bits are read from the first row of all C of the columns of the part 2 in the row direction in units of C=m bits.
Reading of the code bits from all C of the columns of the part 2 is sequentially performed toward the lower rows, and is performed to the final R2-th row.
As described above, the code bits read from the parts 1 and 2 in units of m bits are supplied as symbols to the mapper 117 (
<Group-Wise Interleaving>
In group-wise interleaving, with a bit group of 360 bits of one section obtained by sectioning the LDPC code of one code word in a unit of 360 bits that is equal to the unit size P from the head of the code, the LDPC code of one code word is interleaved in units of bit groups according to a predetermined pattern (hereinafter also referred to as a GW pattern).
Here, a bit group that is in the i+1-th order from the head when the LDPC code of one code word is sectioned into bit groups is also described as a bit group i below.
When the unit size P is 360, for example, an LDPC code with a code length N of 1800 bits is sectioned into 5 (=1800/360) bit groups including bit groups 0, 1, 2, 3, and 4. Further, an LDPC code with a code length N of, for example, 16200 bits is sectioned to 45 (=16200/360) bit groups including bit groups 0, 1, . . . , and 44, and an LDPC code with a code length N of 64800 bits is sectioned into 180 (=64800/360) bit groups including bit groups 0, 1, . . . , and 179.
In addition, a GW pattern is assumed to be expressed by arrangement of numbers indicating bit groups below. For example, for an LDPC code with a code length N of 1800 bits, a GW pattern 4, 2, 0, 3, 1 indicates interleaving (reordering) the arrangement of bit groups 0, 1, 2, 3, and 4, into the arrangement of bit groups 4, 2, 0, 3, and 1.
The GW pattern can be set at least for every code length N of LDPC codes.
According to the GW pattern of
According to the GW pattern of
According to the GW pattern of
According to the GW pattern of
According to the GW pattern of
According to the GW pattern of
According to the GW pattern of
According to the GW pattern of
According to the GW pattern of
According to the GW pattern of
According to the GW pattern of
According to the GW pattern of
According to the GW pattern of
According to the GW pattern of
According to the GW pattern of
The 1st to 15th examples of the GW pattern for the LDPC code with the code length N of 64 k bits can also be applied to any combination of an LDPC code with the code length N of 64 k bits and an arbitrary encoding rate r and an arbitrary modulation method (constellation).
With respect to the group-wise interleaving, however, by setting a GW pattern to be applied for each combination of a code length N of an LDPC code, an encoding rate r of an LDPC code, and a modulation method (constellation), an error rate of each combination can be further improved.
By applying the GW pattern of
By applying the GW pattern of
By applying the GW pattern of
By applying the GW pattern of
By applying the GW pattern of
By applying the GW pattern of
By applying the GW pattern of
By applying the GW pattern of
By applying the GW pattern of
By applying the GW pattern of
By applying the GW pattern of
By applying the GW pattern of
By applying the GW pattern of
By applying the GW pattern of
By applying the GW pattern of
Note that
In addition, in
According to
Note that the GW patterns of
Further, the GW patterns of
<Example of Configuration of Receiving Device 12>
An OFDM processing (OFDM operation) unit 151 receives an OFDM signal from the transmitting device 11 (
The frame management unit 152 performs processing of a frame including the data supplied from the OFDM processing unit 151 (frame interpretation), and supplies a signal of target data obtained as a result of the processing and a signal of control data to frequency deinterleavers 161 and 153.
The frequency deinterleaver 153 performs frequency deinterleaving on the data from the frame management unit 152 in units of symbols, and supplies the result to a demapper 154.
The demapper 154 performs demapping (signal point arrangement decoding) and quadrature demodulation on the data (data on a constellation) from the frequency deinterleaver 153 based on arrangement (constellation) of signal points decided through quadrature modulation performed on the transmitting device 11 side, and supplies data obtained as a result of the processing ((likelihood of) an LDPC code) to an LDPC decoder 155.
The LDPC decoder 155 performs LDPC decoding of the LDPC code from the demapper 154, and supplies LDPC target data (here, a BCH code) obtained as a result of the processing to a BCH decoder 156.
The BCH decoder 156 performs BCH decoding on the LDPC target data from the LDPC decoder 155, and outputs control data (signaling) obtained as a result of the processing.
On the other hand, the frequency deinterleaver 161 performs frequency deinterleaving on the data from the frame management unit 152 in units of symbols, and supplies the result to a SISO/MISO decoder 162.
The SISO/MISO decoder 162 performs spatiotemporal decoding on the data from the frequency deinterleaver 161, and supplies the result to a time deinterleaver 163.
The time deinterleaver 163 performs time deinterleaving on the data from the SISO/MISO decoder 162 in units of symbols, and supplies the result to a demapper 164.
The demapper 164 performs demapping (signal point arrangement decoding) and quadrature demodulation on the data from the time deinterleaver 163 (data on a constellation) based on arrangement (constellation) of signal points decided through quadrature modulation performed on the transmitting device 11 side, and supplies the data obtained as a result of the processing to a bit deinterleaver 165.
The bit deinterleaver 165 performs bit deinterleaving on the data from the demapper 164, and supplies (likelihood of) an LDPC code that is bit-interleaved data to an LDPC decoder 166.
The LDPC decoder 166 performs LDPC decoding on the LDPC code from the bit deinterleaver 165, and supplies LDPC target data (here, a BCH code) obtained as a result of the processing to a BCH decoder 167.
The BCH decoder 167 performs BCH decoding on the LDPC target data from the LDPC decoder 155, and supplies data obtained as a result of the processing to a BB descrambler 168.
The BB descrambler 168 performs BB descrambling on the data from the BCH decoder 167, and supplies data obtained as a result of the processing to a null deletion unit 169.
The null deletion unit 169 deletes null data input by the padder 112 of
The demultiplexer 170 separates one or more respective streams (target data) multiplexed to the data from the null deletion unit 169, performs necessary processing, and outputs the target data as output streams.
Note that the receiving device 12 can be configured without some of the blocks illustrated in
<Example of Configuration of Bit Deinterleaver 165>
The bit deinterleaver 165 includes a block deinterleaver 54 and a group-wise deinterleaver 55, and performs (bit) deinterleaving on symbol bits of symbols that are data from the demapper 164 (
That is to say, the block deinterleaver 54 performs block deinterleaving (inverse processing of block interleaving) corresponding to block interleaving performed by the block interleaver 25 of
The group-wise deinterleaver 55 performs group-wise deinterleaving (inverse processing of group-wise interleaving) corresponding to group-wise interleaving performed by the group-wise interleaver 24 of
Here, when parity interleaving, group-wise interleaving, and block interleaving are performed on the LDPC code supplied from the demapper 164 to the bit deinterleaver 165, the bit deinterleaver 165 can perform all of parity deinterleaving corresponding to the parity interleaving (inverse processing of parity interleaving, i.e., parity deinterleaving to return the code bits of the LDPC code of which the arrangement has been changed through parity interleaving to the original arrangement), block deinterleaving corresponding to the block interleaving, and group-wise deinterleaving corresponding to the group-wise interleaving.
In the bit deinterleaver 165 of
Thus, the LDPC code which has undergone block deinterleaving and group-wise deinterleaving but has not undergone parity deinterleaving is supplied to the LDPC decoder 166 from (the group-wise deinterleaver 55 of) the bit deinterleaver 165.
The LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using a transformed parity check matrix obtained by at least performing column permutation equivalent to parity interleaving on a parity check matrix H of the DVB method used by the LDPC encoder 115 of
In Step S111, the demapper 164 performs demapping on the data from the time deinterleaver 163 (data on the constellation mapped to the signal points) for quadrature demodulation, supplies the data to the bit deinterleaver 165, and then the process proceeds to Step S112.
In Step S112, the bit deinterleaver 165 performs deinterleaving (bit deinterleaving) on the data from the demapper 164, and then the process proceeds to Step S113.
In other words, in Step S112, the block deinterleaver 54 of the bit deinterleaver 165 performs block deinterleaving targeting the data (symbols) from the demapper 164, and supplies code bits of the LDPC code obtained as a result of the processing to the group-wise deinterleaver 55.
The group-wise deinterleaver 55 performs group-wise deinterleaving targeting the LDPC code from the block deinterleaver 54, and supplies (likelihood of) the LDPC code obtained as a result of the processing to the LDPC decoder 166.
In Step S113, the LDPC decoder 166 performs LDPC decoding on the LDPC code from the group-wise deinterleaver 55 using the parity check matrix H used by the LDPC encoder 115 of
Note that, for the sake of convenience in description, the block deinterleaver 54 which performs block deinterleaving and the group-wise deinterleaver 55 which performs group-wise deinterleaving are configured as separate components in
<LDPC Decoding>
LDPC decoding performed by the LDPC decoder 166 of
In the LDPC decoder 166 of
Here, LDPC decoding in which an operation frequency can be kept in a sufficiently feasible range while suppressing a circuit scale by performing the LDPC decoding using the transformed parity check matrix has been proposed before (for example, refer to Japanese Patent Number 4224777).
Thus, the LDPC decoding using the transformed parity check matrix that has been proposed before will first be described with reference to
Note that zeros (0) are expressed as periods (.) in
In the parity check matrix H of
Row permutation: 6s+t+1th row→5t+s+1-th row Expression (11)
Column permutation: 6x+y+61-th column→5y+x+61-th column Expression (12)
In Expressions (11) and (12), s, t, x, and y are integers in the ranges of 0≤s<5, 0≤t<6, 0≤x<5, and 0≤t<6.
According to the row permutation of Expression (11), the permutation is performed such that 1st, 7th, 13th, 19th, and 25th rows which have remainders of 1 when their numbers are divided by 6 are permuted to 1st, 2nd, 3rd, 4th and 5th rows, respectively, and 2nd, 8th, 14th, 20thand 26th rows which have remainders of 2 when their numbers are divided by 6 are permuted to 6th, 7th, 8th, 9th, and 10th rows, respectively.
In addition, according to the column permutation of Expression (12), permutation is performed for 61st and the succeeding columns (in the parity matrix) such that 61st, 67th, 73rd, 79th, and 85th columns which have remainders of 1 when their numbers are divided by 6 are permuted to 61st, 62nd, 63rd, 64th, and 65th columns, respectively, and 62nd, 68th, 74th, 80th, and 86th columns which have remainders of 2 when their numbers are divided by 6 are permuted to 66th, 67th, 68th, 69th, and 70th columns, respectively.
In this manner, the matrix obtained by performing row and column permutation on the parity check matrix H of
Here, even when row permutation of the parity check matrix H is performed, the arrangement of the code bits of the LDPC code is not affected.
In addition, the column permutation of Expression (12) is equivalent to parity interleaving when an information length K is set to 60, the unit size P to 5, and a divisor q (=M/P) of a parity length M (herein, 30) to 6 for parity interleaving to interleave a K+qx+y+1-th code bit to the position of a K+Py+x+1-th code bit.
Thus, the parity check matrix H′ of
When the parity check matrix H′ of
Based on the above, the parity check matrix H′ of
Thus, by performing the column permutation of Expression (12) on the LDPC code c of the original parity check matrix H, decoding the LDPC code c′ that has undergone the column permutation using the transformed parity check matrix H′ of
In
The transformed parity check matrix H′ of
In decoding of an LDPC code of a parity check matrix represented by P×P constitutive matrixes, an architecture in which check node operations and variable node operations are simultaneously performed P times can be used.
That is to say,
The decoding device of
First, a method of storing data in the branch data storing memories 300 and 304 will be described.
The branch data storing memory 300 includes the 6 FIFOs 3001 to 3006 that correspond to a number obtained by dividing the number of rows 30 of the transformed parity check matrix H′ of
In the FIFO 3001, data (messages vi from variable nodes) corresponding to positions of is in the first to fifth rows of the transformed parity check matrix H′ of
In the FIFO 3002, data corresponding to positions of ls in the sixth to tenth rows of the transformed parity check matrix H′ of
That is, with respect to a constitutive matrix of which the weight is two or higher, when the constitutive matrix is represented in the form of the sum of plural matrixes among a P×P unit matrix of which the weight is 1, a quasi unit matrix in which one or more elements of 1 in the unit matrix become 0, and a shifted matrix obtained by cyclically shifting the unit matrix or the quasi unit matrix, data corresponding to the positions of 1s in the unit matrix having the weight of 1, the quasi unit matrix, or the shifted matrix (messages corresponding to branches belonging to the unit matrix, the quasi unit matrix, or the shifted matrix) is stored at the same address (the same FIFO among the FIFOs 3001 to 3006).
Thereafter, also in the storage regions of the 3rd to 9th steps, data is stored in association with the transformed parity check matrix H′.
In the FIFOs 3003 to 3006, data is stored in association with the transformed parity check matrix H′ in the same manner as above.
The branch data storing memory 304 includes 18 FIFOs 3041 to 30418 of which the number is obtained by dividing the number of columns 90 of the transformed parity check matrix H′ by the number of columns 5 (the unit size P) of a constitutive matrix. The FIFO 304x (x=1, 2, . . . , and 18) includes storage regions having a plurality of steps, and in the storage region of each step, messages corresponding to five branches whose number is the number of rows or the number of columns (the unit size P) of a constitutive matrix can be simultaneously read or written.
In the FIFO 3041, data (messages uj from check nodes) corresponding to positions of 1s in the 1st to 5th columns of the transformed parity check matrix H′ of
That is, with respect to a constitutive matrix of which the weight is two or higher, when the constitutive matrix is represented by the sum of plural matrixes of a P×P unit matrix of which the weight is 1, a quasi unit matrix in which one or more elements of 1 in the unit matrix become 0, and a shifted matrix obtained by cyclically shifting the unit matrix or the quasi unit matrix, data corresponding to the positions of is in the unit matrix having the weight of 1, the quasi unit matrix, or the shifted matrix (messages corresponding to branches belonging to the unit matrix, the quasi unit matrix, or the shifted matrix) is stored at the same address (the same FIFO among the FIFOs 3041 to 30418).
Thereafter, also in the storage regions of the 4th and 5th steps, data is stored in association with the transformed parity check matrix H′. The number of steps of the storage regions of the FIFO 3041 becomes 5 that is the maximum number of 1 s (Hamming weight) of the row direction in the 1st to 5th columns of the transformed parity check matrix H′.
In the FIFOs 3042 and 3043, data is stored in association with the transformed parity check matrix H′ in the same manner as the above, and the length of each memory (the number of steps) is 5. In the FIFOs 3044 to 30412, data is stored in association with the transformed parity check matrix H′ in the same manner as above, and the length of each memory is 3. In the FIFOs 30413 to 30418, data is stored in association with the transformed parity check matrix H′ in the same manner as above, and the length of each memory is 2.
Next, an operation of the decoding device of
The branch data storing memory 300 includes the 6 FIFOs 3001 to 3006, and according to information (matrix data) D312 indicating to which row of the transformed parity check matrix H′ of
The selector 301 selects the five messages from the FIFO from which data is being currently read among the FIFOs 3001 to 3006, according to a select signal D301, and supplies the selected messages to the check node calculating unit 302 as messages D302.
The check node calculating unit 302 includes five check node calculators 3021 to 3025, and performs a check node operation according to Expression (7), using the messages D302 (D3021 to D3025) (messages vi of Expression (7)) supplied through the selector 301, and supplies five messages D303 (D3031 to D3035) (messages uj of Expression (7)) obtained as a result of the check node operation to a cyclic shift circuit 303.
The cyclic shift circuit 303 cyclically shifts the five messages D3031 to D3035 calculated by the check node calculating unit 302 on the basis of information (matrix data) D305 indicating how many unit matrixes (or quasi unit matrixes) in which the corresponding branches serve as bases in the corresponding transformed parity check matrix H′ are cyclically shifted, and supplies the result as messages D304 to the branch data storing memory 304.
The branch data storing memory 304 includes the 18 FIFOs 3041 to 30418, and according to information D305 indicating to which row of the transformed parity check matrix H′ five messages D304 supplied from a cyclic shift circuit 303 of a previous step belong, a FIFO storing data is selected from the FIFOs 3041 to 30418 and the five messages D304 are collectively stored in the selected FIFO in order. When reading the data, the branch data storing memory 304 sequentially reads the five messages D3061 from the FIFO 3041 and supplies the messages to the selector 305 of a next step. After finishing reading of the data from the FIFO 3041, the branch data storing memory 304 reads the messages sequentially from the FIFOs 3042 to 30418 and supplies the messages to the selector 305.
The selector 305 selects the five messages from the FIFO from which data is being currently read among the FIFOs 3041 to 30418, according to a select signal D307, and supplies the selected messages to the variable node calculating unit 307 and the decoding word calculating unit 309 as messages D308.
Meanwhile, the reception data rearranging unit 310 rearranges the LDPC code D313 that corresponds to the parity check matrix H in
The variable node calculating unit 307 includes five variable node calculators 3071 to 3075, and performs the variable node operation according to Expression (1) using the messages D308 (D3081 to D3085) (messages uj of Expression (1)) supplied through the selector 305 and the five reception values D309 (reception values uOi of Expression (1)) supplied from the reception data memory 306, and supplies messages D310 (D3101 to D3105) (message vi of Expression (1)) obtained as a result of the operation to the cyclic shift circuit 308.
The cyclic shift circuit 308 cyclically shifts the messages D3101 to D3105 calculated by the variable node calculating unit 307 on the basis of information indicating how many unit matrixes (or quasi unit matrixes) in which the corresponding branches serve as bases in the corresponding transformed parity check matrix H′ are cyclically shifted, and supplies the result as messages D311 to the branch data storing memory 300.
By circulating the above operation in one cycle, decoding (the variable node operation and check node operation) of the LDPC code can be performed once. After decoding the LDPC code a predetermined number of times, the decoding device of
That is, the decoding word calculating unit 309 includes five decoding word calculators 3091 to 3095, calculates a decoding result (decoding word) on the basis of Expression (5) as a final step of multiple times of decoding using the five messages D308 (D3081 to D3085) (messages uj of Expression (5)) output by the selector 305 and the five reception values D309 (reception values uO, of Expression (5)) supplied from the reception data memory 306, and supplies decoded data D315 obtained as a result to the decoded data rearranging unit 311.
The decoded data rearranging unit 311 performs the reverse permutation of the column permutation of Expression (12) with respect to the decoded data D315 supplied from the decoding word calculating unit 309, rearranges the order thereof, and outputs the decoded data as a final decoding result D316.
As mentioned above, by performing one or both of row permutation and column permutation on the parity check matrix (original parity check matrix) and transforming it into a parity check matrix (transformed parity check matrix) that can be represented by a combination of a P×P unit matrix, a quasi unit matrix in which one or more elements of 1 thereof become 0, a shifted matrix obtained by cyclically shifting the unit matrix or the quasi unit matrix, a sum matrix that is the sum of plural matrixes of the unit matrix, the quasi unit matrix and the shifted matrix, and a P×P zero matrix, that is, the combination of constitutive matrixes, an architecture in which check node operations and variable node operations are simultaneously performed P times, this number being lower than the number of rows or the number of columns of the parity check matrix, can be adopted to decoding of the LDPC code. When the architecture in which node operations (check node operations and variable node operations) are simultaneously performed P times, this number being lower than the number of rows or the number of columns of the parity check matrix, is adopted, an operation frequency can be kept in a feasible range and decoding can be performed iteratively a number of times, in comparison to a case in which the node operations are simultaneously performed as many times as the number of rows or the number of columns of the parity check matrix.
The LDPC decoder 166 that constitutes the receiving device 12 of
That is, for the sake of simplified description, if the parity check matrix of the LDPC code output by the LDPC encoder 115 constituting the transmitting device 11 of
Because the parity interleaving corresponds to the column permutation of Expression (12) as described above, it is not necessary to perform the column permutation of Expression (12) in the LDPC decoder 166.
For this reason, in the receiving device 12 of
In
Since the LDPC decoder 166 can be configured without the reception data rearranging unit 310 as described above, a scale thereof can be reduced more than that of the decoding device of
Note that, although the code length N of the LDPC code is set to 90, the information length K to 60, the unit size (the number of rows and the number of columns of the constitutive matrix) P to 5, and the divisor q (=M/P) of the parity length M to 6 for the sake of simplified description in
That is, in the transmitting device 11 of
In addition, when the portion of parity of the decoding result is unnecessary and only information bits of the decoding result are output after decoding the LDPC code by the LDPC decoder 166, the LDPC decoder 166 can be configured without the decoded data rearranging unit 311.
<Example of Configuration of Block Deinterleaver 54>
The block deinterleaver 54 is configured the same as the block interleaver 25 described in
Thus, the block deinterleaver 54 has a storage region called a part 1 and another storage region called a part 2, and the parts 1 and 2 each store 1 bit in the row direction, each of which includes C columns serving as storage regions for storing a predetermined number of bits in the column direction that are arranged in the row direction, and the number C is equal to the number of bits m of a symbol.
The block deinterleaver 54 performs block deinterleaving by writing and reading the LDPC code on and from the parts 1 and 2.
In block deinterleaving, however, writing of the LDPC code (which has become a symbol) is performed in the order in which the block interleaver 25 of
Further, in block deinterleaving, reading of the LDPC code is performed in the order in which the block interleaver of
That is, the LDPC code is written in the column direction and read in the row direction with respect to the parts 1 and 2 in block interleaving by the block interleaver 25 of
<Another Example of Configuration of Bit Deinterleaver 165>
Note that the same reference numerals are given to portions of the drawing corresponding to those in
That is, the bit deinterleaver 165 of
In
That is, targeting the LDPC code from the demapper 164, the block deinterleaver 54 performs block deinterleaving corresponding to block interleaving (inverse processing of block interleaving) performed by the block interleaver 25 of the transmitting device 11, i.e., block deinterleaving of returning the positions of the code bits reordered through the block interleaving to the original positions, and supplies the LDPC code obtained as a result of the processing to the group-wise deinterleaver 55.
The group-wise deinterleaver 55 performs group-wise deinterleaving corresponding to group-wise interleaving performed as rearrangement processing by the group-wise interleaver 24 of the transmitting device 11, targeting the LDPC code from the block deinterleaver 54.
The LDPC code obtained by as a result of the group-wise deinterleaving is supplied to the parity deinterleaver 1011 from the group-wise deinterleaver 55.
The parity deinterleaver 1011 performs parity deinterleaving corresponding to parity interleaving (inverse processing of parity interleaving) performed by the parity interleaver 23 of the transmitting device 11, i.e., parity deinterleaving of returning the code bits of the LDPC code whose arrangement has been changed through the parity interleaving to the original arrangement, targeting the code bits group-wise-deinterleaved by the group-wise deinterleaver 55.
The LDPC code obtained as a result of the parity deinterleaving is supplied to the LDPC decoder 166 from the parity deinterleaver 1011.
Thus, in the bit deinterleaver 165 of
The LDPC decoder 166 performs LDPC decoding on the LDPC code from the bit deinterleaver 165 using the parity check matrix H used by the LDPC encoder 115 of the transmitting device 11 in the LDPC encoding. That is, the LDPC decoder 166 performs LDPC decoding on the LDPC code from the bit deinterleaver 165 using the parity check matrix H (of the DVB method) used by the LDPC encoder 115 of the transmitting device 11 in the LDPC encoding or using a transformed parity check matrix obtained by at least performing column permutation equivalent to parity interleaving on the parity check matrix H (with respect to the ETRI method, the parity check matrix (
Here, in
In addition, when the LDPC decoder 166 performs LDPC decoding on the LDPC code using the transformed parity check matrix obtained by at least performing column permutation equivalent to parity interleaving on the parity check matrix H (of the DVB method) used by the LDPC encoder 115 of the transmitting device 11 in the LDPC encoding (with respect to the ETRI method, the transformed parity check matrix (
Note that, in
<Example of Configuration of Reception System>
In
The acquisition unit 1101 acquires a signal including an LDPC code obtained by at least performing LDPC encoding on LDPC target data such as image data, audio data, or the like of a program through a transmission path (communication path) that is not illustrated, for example, digital terrestrial broadcasting, digital satellite broadcasting, a CATV network, the Internet, and other networks, and supplies the signal to the transmission path decoding processing unit 1102.
Here, when the signal acquired by the acquisition unit 1101 is broadcast from a broadcasting station through, for example, terrestrial waves, satellite waves, a cable television (CATV) network, or the like, the acquisition unit 1101 includes a tuner, a set-top box (STB), or the like. In addition, when the signal acquired by the acquisition unit 1101 is transmitted from, for example, a web server through multicast like an Internet Protocol Television (IPTV), the acquisition unit 1101 includes a network interface (I/F), for example, a network interface card (NIC) or the like.
The transmission path decoding processing unit 1102 corresponds to the receiving device 12. The transmission path decoding processing unit 1102 performs transmission path decoding processing which includes at least a process of correcting an error occurring in a transmission path on the signal acquired by the acquisition unit 1101 through the transmission path, and supplies a signal obtained as a result of the processing to the information source decoding processing unit 1103.
That is to say, the signal acquired by the acquisition unit 1101 through the transmission path is a signal obtained by at least performing error correction encoding for correcting an error occurring on the transmission path, and the transmission path decoding processing unit 1102 performs transmission path decoding processing, for example, error correction processing or the like with respect to the signal.
Here, as the error correction encoding, for example, there are LDPC encoding, BCH encoding, and the like. In this case, at least LDPC encoding is performed as the error correction encoding.
In addition, the transmission path decoding processing may include demodulation of a modulated signal or the like.
The information source decoding processing unit 1103 performs information source decoding processing on the signal that has undergone the transmission path decoding processing, which includes at least a process of decompressing compressed information into original information.
That is to say, there may be cases in which compression encoding for compressing information is performed on the signal acquired by the acquisition unit 1101 via the transmission path in order to reduce the data amount of images, sounds, or the like serving as information, and in such a case, the information source decoding processing unit 1103 performs information source decoding processing including a process of decompressing compressed information into original information (decompression processing) on the signal that has undergone the transmission path decoding processing.
Note that, when compression encoding is not performed on the signal acquired by the acquisition unit 1101 through the transmission path, the information source decoding processing unit 1103 does not perform the process of decompressing compressed information into original information.
Here, as the decompressing processing, for example, there is MPEG decoding or the like. In addition, the transmission path decoding processing may include descrambling or the like in addition to the decompressing processing.
In the reception system configured as described above, the acquisition unit 1101 acquires a signal obtained by performing compression encoding such as MPEG encoding and further performing error correction encoding such as LDPC encoding on, for example, image or audio data through a transmission path, and supplies the signal to the transmission path decoding processing unit 1102.
The transmission path decoding processing unit 1102 performs, for example, the same processing as the receiving device 12 on the signal from the acquisition unit 1101 as transmission path decoding processing, and supplies a signal obtained as a result of the processing to the information source decoding processing unit 1103.
The information source decoding processing unit 1103 performs information source decoding processing such as MPEG decoding on the signal from the transmission path decoding processing unit 1102, and outputs images or sounds that are obtained as a result of the processing.
The reception system of
Note that the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 can each be configured as one independent device (hardware (such as an integrated circuit (IC)) or a software module).
In addition, with the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103, a set of the acquisition unit 1101 and the transmission path decoding processing unit 1102, a set of the transmission path decoding processing unit 1102 and the information source decoding processing unit 1103, and a set of the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 can each be configured as one independent device.
Note that the same reference numerals are given to portions of the drawing corresponding to those in
The reception system of
The output unit 1111 is, for example, a display device which displays images or a speaker which outputs sounds, and outputs images, sounds, and the like that are signals output from the information source decoding processing unit 1103. That is to say, the output unit 1111 displays images or outputs sounds.
The reception system of
Note that, when compression encoding is not performed on a signal acquired by the acquisition unit 1101, the signal output by the transmission path decoding processing unit 1102 is supplied to the output unit 1111.
Note that the same reference numerals are given to portions of the drawing corresponding to those in
The reception system of
The reception system of
The recording unit 1121 records (stores) a signal output by the transmission path decoding processing unit 1102 (for example, a TS packet of an MPEG-TS) on a recording (storage) medium such as an optical disc, a hard disk (magnetic disk), or a flash memory.
The reception system of
Note that, in
<Embodiment of a Computer>
The above-described series of processes can be performed using hardware or software. When the series of processes is performed using software, a program constituting the software is installed in a general-purpose computer or the like.
Thus,
The program can be recorded in advance in a hard disk 705 or a ROM 703 serving as a recording medium built in the computer.
Alternatively, the program can be temporarily or permanently stored (recorded) on a removable recording medium 711 such as a flexible disk, a Compact Disc Read Only Memory (CD-ROM), a magneto optical (MO) disc, a digital versatile disc (DVD), a magnetic disk, or a semiconductor memory. Such a removable recording medium 711 can be provided as so-called package software.
Note that, in addition to being installed in the computer from the removable recording medium 711 described above, the program can be transferred to the computer via a satellite for digital satellite broadcasting in a wireless manner, or transferred to the computer via a network such as a local area network (LAN) or the Internet in a wired manner from a download site, and in the computer, the program transferred as above can be received by a communication unit 708 and installed in the built-in hard disk 705.
The computer includes a central processing unit (CPU) 702. The CPU 702 is connected to an input and output interface 710 via a bus 701, and when a user inputs a command by operating an input unit 707 including a keyboard, a mouse, a microphone, or the like via the input and output interface 710, the CPU 702 executes a program stored in the read only memory (ROM) 703 according to the command. Alternatively, the CPU 702 loads a program stored in the hard disk 705, a program transferred from a satellite or a network, received by the communication unit 708, and installed in the hard disk 705, or a program read from the removable recording medium 711 loaded in a drive 709 and installed in the hard disk 705 in a random access memory (RAM) 704 and executes the program. Accordingly, the CPU 702 performs processing according to the above-described flowcharts or processing performed with the configurations of the above-described block diagrams. Then, the CPU 702 causes a result of the processing to be, for example, output from an output unit 706 including a liquid crystal display (LCD), a speaker, or the like, transmitted from the communication unit 708, or further recorded in the hard disk 705 via the input and output interface 710, as necessary.
In the present specification, it is not necessary to perform processing steps for describing a program which causes a computer to perform various kinds of processing in a time series manner in the orders described as flowcharts, and processing executed separately or in parallel (for example, parallel processing or processing by an object).
In addition, the program may be processed by one computer, or be subject to distributed processing performed by a plurality of computers. Further, the program may be transferred to and executed by a remote computer.
Note that an embodiment of the present technology is not limited to the above-described embodiments, and can be variously modified within a scope not deviating from the gist of the present technology.
That is to say, for example, (the parity check matrix initial value table of) the above-described new LDPC code the communication path 13 (
In addition, the above-described GW pattern can also be applied to codes other than the new LDPC code. Further, a modulation method to which the above-described GW pattern is applied is not limited to 16QAM, 64QAM, 256QAM, and 1024QAM.
Note that the effects described in the present specification are thoroughly illustrative and not limitative, and other effects may be included.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2014-030012 | Feb 2014 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2015/053181 | 2/5/2015 | WO |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2015/125612 | 8/27/2015 | WO | A |
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| Number | Date | Country | |
|---|---|---|---|
| Parent | 14782740 | Feb 2015 | US |
| Child | 16381936 | US |
