1. Technical Field
Embodiments of the present disclosure relate to test technology, and particularly to a data processing device and method for controlling a test process of an electronic device using the data processing device.
2. Description of Related Art
Motherboard testing may include a plurality of preset test items stored in a configuration file, such as a memory test, a central processing unit (CPU) test, a north bridge test, and a south bridge test. However, a test person may modify the configuration file to remove some test items, that the motherboard would otherwise fail, in order to produce false positive results. In other words the test person may cheat. Therefore, a more secure method for controlling a test process of an electronic device is desired.
All of the processes described below may be embodied in, and fully automated via, functional code modules executed by one or more general purpose electronic devices or processors. The code modules may be stored in any type of non-transitory readable medium or other storage device. Some or all of the methods may alternatively be embodied in specialized hardware. Depending on the embodiment, the non-transitory readable medium may be a hard disk drive, a compact disc, a digital video disc, a tape drive or other suitable storage medium.
In block S301, the creation module 200 creates test control data to test the electronic device 13, and stores the test control data in the FRU storage area 14 of the BMC 12. In one embodiment, the test control data include test bits and flag bits, and each of the test bits represents a test item of the electronic device 13. The test bits and the flag bits are binary numbers. For example, the electronic device 13 includes eight test items. As shown in
In one embodiment, the test bits in the test control data are arranged according to a test order of the test items of the electronic device 13. For example, the first test bit represents the first test item of the electronic device 13, and the eighth test bit represents the eighth test item of the electronic device 13. In one embodiment, the test bits in the test control data include at least one test bit which is different from the other test bits. The flag bits in the test control data are not the first bit and the last bit of the test control data. In other embodiments, a number of the flag bits may be increased according to increase of the test bits. For example, if a number of the test bits is twenty, the number of the flag bits is four.
In block S302, the test module 210 reads the test control data from the FRU storage area 14, and sequentially selects test items of the electronic device 13 according to the test bits in the test control data. In one embodiment, the test item of the electronic device 13 is selected sequentially according to the test order of the test items of the electronic device 13.
In block S303, the test module 210 determines if the electronic device 13 passes the selected test item. If the electronic device 13 passes the selected test item, the procedure goes to block S304. If the electronic device 13 fails the selected test item, the procedure goes to block S308.
In block S304, the test module 210 implements a logical NOR operation on a test bit corresponding to the selected test item to obtain modified test control data. The flag bits in the created test control data are invariant. For example, if a test bit corresponding to the selected test item in the created test control data is “1”, the test module 210 changes the test bit from “1” to “0” if the electronic device 13 passes the test item corresponding to the test bit.
In block S305, the test module 210 determines if all the test items of the electronic device 13 have been performed on the electronic device 13. If all the test items of the electronic device 13 have been performed, the procedure goes to block S306. If any test item of the electronic device 13 has not been performed, the procedure returns to block S302, the test module 210 selects the next test item in sequence that has not performed to continue the test process until all the test items have been performed.
In block S306, the comparison module 220 compares the modified test control data with the created test control data to determine if the electronic device 13 passes the test process. If the electronic device 13 passes test process, the procedure goes to block S307. If the electronic device 13 fails test process, the procedure goes to block S308.
In one embodiment, if each of the flag bits in the modified test control data is equal to a corresponding flag bit in the created test control data, and each of the test bits in the modified test control data is different from a corresponding test bit in the created test control data, the comparison module 220 determines that the electronic device 13 passes the test process. For example, as shown in
If one of the flag bits in the modified test control data is different from a corresponding flag bit in the created test control data, or one of the test bits in the modified test control data is equal to a corresponding test bit in the created test control data, the comparison module 220 determines that the electronic device 13 fails the test process.
In block S307, the output module 230 outputs a signal indicating success to a display device of the data processing device 11.
In block S308, the output module 230 outputs a signal indicating failure to the display device of the data processing device 11.
Because the flag bits are allocated in the created test control data randomly, it is hard for the test person to obtain the addresses of the test bits in the created test control data. Thus, it is difficult to for the test person to cheat.
It may be understood that the test control system 10 may be installed in the electronic device 13 if the electronic device 13 has the baseboard management controller (BMC) 12, the storage device 15, and the processor 16. Thus, the data processing device 11 may be removed. If the control system 10 is installed in the electronic device 13, the test module 210 may remove the created test control data stored in the FRU storage area 14 of the BMC 12 when test process is complete.
It should be emphasized that the above-described embodiments of the present disclosure, particularly, any embodiments, are merely possible examples of implementations, merely set forth for a clear understanding of the principles of the disclosure. Many variations and modifications may be made to the above-described embodiment(s) of the disclosure without departing substantially from the spirit and principles of the disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure and the present disclosure and protected by the following claims.
Number | Date | Country | Kind |
---|---|---|---|
201010263716.2 | Aug 2010 | CN | national |