Patent Application
20180293949
The present invention relates to data processing devices connected with display devices which perform so called intermission driving, and to methods for controlling these display devices in these data processing devices.
Power saving in liquid crystal display devices and other display devices is an ongoing challenge. Toward this end, Patent Document 1, for example, discloses a display device driving method in which a refreshing period during which a display image is refreshed by scanning gate lines that serve as scanning signal lines of the liquid crystal display device is followed by a non-refreshing period during which refreshing is stopped by bringing all of the gate lines into a non-scanning state. In this intermission period, it is possible not to supply signals such as control signals to, e.g., a gate driver which serves as a scanning signal line drive circuit and/or a source driver which serves as a data signal line drive circuit. This makes it possible to stop operation of the gate driver and/or the source driver, and therefore to reduce power consumption. The driving method in which a refreshing period is followed by a non-refreshing period (intermission period) as exemplified in Patent Document 1 is called “intermission driving” for example. The intermission driving is also called “low-frequency driving” or “intermittent driving”. Intermission driving as described above is suitable for displaying a still image. Inventions related to intermission driving are disclosed in Patent Document 2 and other publications as well as Patent Document 1.
In a display device in which intermission driving as described above is performed, display image is not refreshed for every frame period when there is no change in the image which is to be displayed. However, display image must be refreshed for every predetermined period which is longer than one frame period. If the display device is provided with a frame buffer which holds display image data to be used for the refreshing, it is possible to carry out the refreshing within the display device by internal operation. In many cases, however, the frame buffer is not provided within the display device for the sake of cost reduction, and in such a case, a frame buffer is provided in a main body of an electronic appliance that has the display device as a component. Hereinafter, such a configuration, in which a frame buffer is provided in the main body of the electronic appliance without providing a frame buffer in a display device, is referred to as “main body frame buffer configuration”.
Patent Document 1: WO/2013/008668
Patent Document 2: WO/2013/140980
In the display device of the intermission driving type, the more the portion stopping operation in the non-refreshing period (hereinafter referred to as “intermission portion”), the greater the power consumption reduction effect becomes. However, when the number of intermission portions increases, the time required for the display device to return from the intermission state to the normal state becomes long. Therefore, when the number of intermission portions is increased, in the main body frame buffer configuration as described above, there may be a case where the image data for refreshing the display image is missing. That is, when updating of image data in the frame buffer of the main body is detected and image data for refreshing is sent to the display device, there may be a case where all the intermission portions of the display device can not return to the normal state and some thereof do not work. In this case, in the display device, image data for refreshing the display image is missing, and normal image display can not be performed.
In this regard, there is considered a method of suppressing the loss of image data by sending a return instruction to the normal state from the main body to the display device a predetermined time before updating the display image. However, in the case where unpredictable updating of image data occurs due to user's operation or the like, such a method can not be used. On the other hand, if the number of intermission potions in the display device is reduced in order to avoid such loss of image data, the effect of reducing power consumption by the intermission driving is small.
It is therefore an object of the present invention to provide a data processing device which is connected with an intermission driving display device and has a frame buffer, and is capable of achieving a satisfactory power saving by means of intermission driving while ensuring a high level of display quality of the display device.
A first aspect of the present invention provides a data processing device connected data-exchangeably with a display device having an intermission driving mode, in which the display device drives a display section in such a manner that a refreshing period during which an image displayed in the display section is refreshed and a non-refreshing period during which an image displayed in the display section is not refreshed are alternated with each other, the data processing device including:
a memory section capable of storing image data for a plurality of frames each representing an image to be displayed in the display section, the memory section having, as an image buffer, a memory area including at least one frame buffer area;
an update detection section configured to detect a data update of image data in the image buffer, the data update being caused by writing of new image data into the image buffer; a data transfer controller configured to transfer image data stored in the image buffer to the display device by a first-in first-out method upon detection of a data update in the image buffer by the update detection section, and assume an intermission state for an intermission period determined as the non-refreshing period at most upon detection of a non-update of the image data in the image buffer for a predetermined period by the update detection section;
wherein the data transfer controller is configured to
extend the memory area of the memory section upon shifting to the intermission state, and
return to a normal state of transferring the image data to the display device in response to a data update by the update detection section as well as to send a return instruction for operating a stopped circuit in the display device to the display device, upon detection of a data update in the image buffer by the update detection section in the intermission state.
A second aspect of the present invention provides the data processing device according to the first aspect of the present invention, wherein, if the memory area of the image buffer has been extended, the data transfer controller counts as a non-update frame period count the number of frame periods during which the update detection section detects a non-update of the image data in the image buffer in the normal state, and releases an extension frame buffer area defined as an extension portion of the image buffer when the non-update frame period count becomes larger than the number of frame periods corresponding to a return time defined as time from sending of the return instruction to the display device till resuming of operation of the stopped circuit in the display device.
A third aspect of the present invention provides the data processing device according to the first aspect of the present invention, wherein the data transfer controller
sends a return instruction for operating the stopped circuit in the display device to the display device when the data transfer controller returns from the intermission state to the normal state,
transfers the image data in the image buffer to the display device at a second transfer rate higher than a first transfer rate predetermined as a standard rate when the data transfer controller receives a return completion notification indicating resumption of operation of the stopped circuit in the display device from the display device after sending the return instruction,
releases the extension frame buffer area and changes a transfer rate of the image data in the image buffer to the first transfer rate when there occurs a frame period in which image data stored in the extension frame buffer area has already been read out and new display image data has not been written into the extension frame buffer area, if the image data in the image buffer is transferred to the display device at the second transfer rate.
A fourth aspect of the present invention provides the data processing device according to the third aspect of the present invention, wherein, upon receiving the return completion notification from the display device, the data transfer controller transfers the image data in the image buffer to the display device at the second transfer rate for time corresponding to the number of frame periods given by the following equation:
Nfast=(Ffast*Ndelay)/(Ffast−Forig)
where Ffast is the second transfer rate, Forig is the first transfer rate, Ndelay is the number of frames for which a delay occurs due to the extension of the memory area of the image buffer causes delay.
A fifth aspect of the present invention provides the data processing device according to the first aspect of the present invention, wherein the data transfer controller
sends a return instruction for operating the stopped circuit in the display device to the display device, upon returning from the intermission state to the normal state,
determines a return time measurement value by measuring time from sending the return instruction till receiving a return completion notification indicating resumption of operation of the stopped circuit in the display device, and determines or changes a size of the extension frame buffer area, upon receiving the return completion notification after sending the return instruction.
A sixth aspect of the present invention provides the data processing device according to the fifth aspect of the present invention, wherein, when the data transfer controller sends the return instruction to the display device after determining the return time measurement value, the data transfer controller starts transferring the image data in the image buffer to the display device at timing based on the return time measurement value without waiting for the return completion notification to be received from the display device after sending the return instruction.
A seventh aspect of the present invention provides the data processing device according to the first aspect of the present invention, wherein the data transfer controller
determines the intermission period based on refreshing-related information obtained from the display device, when the update detection section detects a non-update of the image data in the image buffer for the predetermined period,
shifts to the intermission state if the intermission period is longer than a predetermined reference period,
stops a first circuit defined as a circuit which has time required for resuming operation not longer than a predetermined time among circuits to be stopped in the display device in the intermission state and thereafter shifts to a short intermission state different from the intermission state without extending the memory area of the image buffer, if the intermission period is not longer than the predetermined reference period, and
returns to the normal state and resumes operation of the first circuit in the display device, when the update detection section detects a data update in the image buffer while the data transfer controller is in the short intermission state.
A eighth aspect of the present invention provides the data processing device according to the first aspect of the present invention, wherein the data transfer controller includes:
a first interface circuit configured to transfer image data in the image buffer to the display device, and
a second interface circuit configured to send a return instruction for operating the stopped circuit in the display device to the display device and receive a return completion notification indicating resumption of operation of the stopped circuit in the display device from the display device, when the data transfer controller returns from the intermission state to the normal state,
wherein the second interface circuit is provided as a serial interface having a slower data transfer rate than the first interface circuit.
A ninth aspect of the present invention provides the data processing device according to any one of the first through eighth aspects of the present invention, wherein the display section includes a thin film transistor having a channel etch structure which has a channel layer formed of an oxide semiconductor, as a switching element for forming each pixel constituting an image to be displayed.
A tenth aspect of the present invention provides a method for enabling a data processing device to control a display device which is connected data-exchangeably therewith and has an intermission driving mode, in which the display device drives a display section in such a manner that a refreshing period during which an image displayed in the display section is refreshed and a non-refreshing period during which an image displayed in the display section is not refreshed are alternated with each other, the method including:
an update detection step of detecting an update of image data in an image buffer in a memory section within the data processing device, the memory section being capable of storing image data for a plurality of frames each representing an image to be displayed in the display section, the memory section having, as the image buffer, a memory area including at least one frame buffer area;
an updated-data transfer step of transferring image data stored in the image buffer to the display device by a first-in first-out method, upon detection of a data update in the image buffer;
an intermission step of assuming an intermission state for an intermission period determined as the non-refreshing period at most upon detection of a non-update of the image data in the image buffer for a predetermined period;
a buffer extension step of extending the memory area of the image buffer upon shifting to the intermission state;
a return instruction step of sending a return instruction for operating a stopped circuit in the display device to the display device, upon detection of a data update in the image buffer in the intermission state; and
a return-to-normal-state step of returning to a normal state, in which the image data is transferred to the display device in response to a data update in the update detection step, upon detection of a data update in the image buffer in the intermission state.
A eleventh aspect of the present invention provides a device driver program for enabling a data processing device to control a display device which is connected data-exchangeably therewith and has an intermission driving mode, in which the display device drives a display section in such a manner that a refreshing period during which an image displayed in the display section is refreshed and a non-refreshing period during which an image displayed in the display section is not refreshed are alternated with each other, the program causing a processor in the data processing device to execute:
an update detection step of detecting an update of image data in an image buffer in a memory section within the data processing device, the memory section being capable of storing image data for a plurality of frames each representing an image to be displayed in the display section, the memory section having, as the image buffer, a memory area including at least one frame buffer area;
an updated-data transfer step of transferring image data stored in the image buffer to the display device by a first-in first-out method, upon detection of a data update in the image buffer;
an intermission step of assuming an intermission state for an intermission period determined as the non-refreshing period at most upon detection of a non-update of the image data in the image buffer for a predetermined period;
a buffer extension step of extending the memory area of the image buffer upon shifting to the intermission state;
a return instruction step of sending a return instruction for operating a stopped circuit in the display device to the display device, upon detection of a data update in the image buffer in the intermission state; and
a return-to-normal-state step of returning to a normal state, in which the image data is transferred to the display device in response to a data update in the update detection step, upon detection of the data update in the image buffer in the intermission state.
A twelfth aspect of the present invention provides a computer-readable recording medium containing the program according to the eleventh aspect.
Other aspects of the present invention are clear from the above description of the first through the twelfth aspects of the present invention and from description of each embodiment to be made herein later, and therefore will not be stated here.
According to the first aspect of the present invention, in a data processing device as a host to which a display device performing an intermission driving is connected, when it is detected that image data in an image buffer is not updated for a predetermined period, a data transfer controller assumes an intermission state for an intermission period determined at most as a non-refreshing period in the intermission driving mode. In the intermission state, power consumption in the display device as well as in the host side is reduced by stopping operation of a predetermined circuits in the display device. Upon shifting to such an intermission state, a memory area of the image buffer is extended in the display device. Therefore, even in the case where it takes time to resume operation of the stopped circuit in the display device when returning from the intermission state to the normal state, it is possible to avoid loss of the image data (frame missing) by stopping transfer of the image data from the host to the display device and writing new image data into the image buffer during the returning period. As a result, even in the case where it is impossible to predict the returning point from the intermission state to the normal state, such as when a data update occurs in the image buffer due to a user operation on the data processing device, it is possible to greatly reduce power consumption without degrading the display quality, by stopping many circuits within the display device in the intermission state with preventing frame missing.
According to the second aspect of the present invention, if the memory area of the image buffer has been extended, an extension frame buffer area defined as an extension portion of the image buffer is released when the non-update frame period count becomes larger than the number of frame periods corresponding to a return time of the display device in the normal state. Therefore, it is possible to avoid consuming extra memory in the host in order to prevent frame missing.
According to the third aspect of the present invention, the image data in the image buffer is transferred to the display device at a higher rate than a standard rate when the data transfer controller returns from the intermission state to the normal state, and thereby the memory area of the image buffer which has been extended upon shifting to the intermission state (extension frame buffer area) becomes releasable. Therefore, even in the case of continuing data update in the image buffer, such as in the case of reproducing a moving image, it is possible to certainly release the extension frame buffer area and eliminate delay in refreshing the display image, after a predetermined time since the display device returns to the normal state.
According to the fourth aspect of the present invention, the image data in the image buffer is transferred to the display device at a high speed for time corresponding to the predetermined number of frame periods Nfast=(Ffast*Ndelay)/(Ffast−Forig) when the data transfer controller receives the return completion notification from the display device, and thereby the extension frame buffer area becomes releasable. Therefore, the same advantages as the above third aspect are obtained.
According to the fifth aspect of the present invention, a return time measurement value is determined by measuring time from sending the return instruction till receiving the return completion notification, and a size of the extension frame buffer area is determined based on the return time measurement value. Therefore, it is possible to certainly prevent frame missing in the returning state of the display device without allocating extra memory for the extension frame buffer area.
According to the sixth aspect of the present invention, when the return instruction is sent to the display device after determining the return time measurement value, transfer of the image data in the image buffer to the display device is started at timing based on the return time measurement value without waiting for the return completion notification to be received from the display device after sending the return instruction. This simplifies the operation and configuration for returning from the intermission state to the normal state and makes it possible to reduce delay in refreshing the displayed image.
According to the seventh aspect of the present invention, when it is detected that the image data in an image buffer is not updated for a predetermined period, the data transfer controller shifts to a short intermission state different from the intermission state if the intermission period determined based on refreshing-related information obtained from the display device is not longer than a predetermined reference period, and shifts to the intermission state for stopping many circuits in the display device if the intermission period is longer than the predetermined reference period. In the intermission state, although the power consumption of the display device can be greatly reduced, it takes time to return from the intermission state to the normal state, which causes delay in refreshing the displayed image. Therefore, in the short intermission state, in which the intermission period is comparatively short, it is possible to return to the normal state so as to display a changed image quickly when there is any change found in the image to be displayed, while in the intermission state, in which the intermission period is comparatively long, it is possible to reduce the power consumption of the display device more greatly than in the short intermission state by assuming that the necessity for returning to the normal state is low and stopping many circuits in the display device.
According to the eighth aspect of the present invention, the data transfer controller is provided with, in addition to a first interface circuit which is for transferring image data from the image buffer to the display device, a second interface circuit which is provided as a serial interface having a slower data transfer rate than the first interface, for data exchange between the data processing device as a host and the display device. The second interface circuit is used for sending the return instruction to the display device and receiving the return completion notification indicating resumption of operation of the stopped circuit in the display device. The arrangement decreases power consumption for data transfer between the data processing device and the display device through selective use of the first interface circuit and the second interface circuit as described, depending on the amount of data transfer.
According to the ninth aspect of the present invention, since the display section of the display device employs a thin film transistor having a channel etch structure which has a channel layer formed of an oxide semiconductor, as a switching element for forming each pixel, off-leak current of the thin film transistor is greatly reduced and the intermission driving can be satisfactorily performed.
Advantages provided by other aspects of the present invention will be clear from the first through the ninth aspects of the present invention and from description of the embodiments to be given below, and therefore will not be stated here.
Hereinafter, embodiments of the present invention will be described with reference to the attached drawings. Hereinafter, the term one frame period means a period for refreshing one screen (redrawing a displayed image), and the length of “one frame period” is assumed as long as a commonly utilized length of one frame period (16.67 ms) used in display devices of a refreshing rate of 60 Hz. However, the present invention is not limited to this.
As shown in
The main controller 10 performs procedures and controls necessary for implementing various functions incorporated in the portable terminal, and includes an application processor provided by a central processing device (hereinafter may also be called “CPU”) 101, a RAM (Random Access Memory) 104, and a ROM (Read Only Memory) 105. In other words, the CPU 101 executes programs (such as an operating system 130 which will be described later) stored in the ROM 105 in the main controller 10, thereby performing desired procedures and controls on relevant components to implement various functions of the portable terminal. The main controller 10 also includes a DSI section 106 as a host-side interface circuit for making data exchange with the display device 11 via an interface conforming to DSI (Display Serial Interface) Standards proposed by MIPI (Mobile Industry Processor Interface) Alliance (hereinafter called “MIPI-DSI Standards”).
The input operation section 16 is a section for receiving inputting operations from a user of this portable terminal, and is implemented by a touch panel and so on. The communication section 15 provides the portable terminal with wireless data exchange capability with other portable terminals. The image capture section 14 uses an image sensor to capture images of people and things and supply image signals to the main controller 10. The audio input section 17 captures ambient sounds and supply these audio signals to the main controller 10. The audio output section 18 outputs sounds based on audio data supplied from the main controller 10. The memory section 12 is provided by a memory of a greater capacity than the RAM 104, the ROM 105, etc. which are in the main controller 10, and includes memory areas to be used as an image buffer 12f which is to be described later. The display device 11 displays images represented by image data supplied from the main controller 10. The power supply section 13 supplies electric power necessary for operation of each section in the portable terminal.
The OS 130 includes a video driver 131 as a device driver to control hardware for displaying images in the display device 11. The video driver 131 has an FB access processing section 133 and a DSI controller 135 for respectively controlling an image buffer 12f and a DSI section 106 in the data processing device (host) 100. The DSI section 106 which serves as an interface circuit and a DSI controller 135 which serves as an interface controller constitute a data transfer controller. The image buffer 12f is a memory for storing data (hereinafter called “display image data”) which represents an image to be displayed in the display device 11. The FB access processing section 133 controls updating (writing) of the display image data in the image buffer 12f. By using a video mode of the MIPI-interface which conforms to DSI Standards (hereinafter called “DSI video mode”), the DSI section 106 is capable of transferring a data DAT, which includes one frame-amount of display image data in the image buffer 12f, to the display device 11 for each frame period (16.67 ms) (this applies to all the other embodiments, too). The DSI controller 135 can stop and resume the transfer of the data DAT from the DSI section 106 to the display device 11. It should be noted here that for operation of the DSI controller 135, the video driver 131 further has an update detection section 132 which detects whether or not the display image data in the image buffer 12f is updated by the FB access processing section 133. Detailed operation of the update detection section 132 and the DSI controller 135 will be described later.
The display device 11 connected with the data processing device according to the present embodiment is an LCD module (hereinafter, may also simply called “LCD”) and has a display section 600 which makes use of liquid crystal and an LCD driving section 40. The LCD driving section 40 is connected with the data processing device 100 (i.e., DSI section 106 therein), is capable of exchanging data therewith via the interface conforming to the above-described MIPI-DSI Standards, and drives the display section 600 based on the data DAT received from the host, i.e., the data processing device 100, thereby displaying an image represented by the display image data contained in the data DAT, in the display section 600 (details will be described later).
With the configuration described above and depicted in
The above-described operations and functions of the constituent elements 132 through 135 in the video driver 131 are implemented by the CPU 101 executing programs (hereinafter called “LCD device driver program”) for the video driver 131. The LCD device driver program is installed in the ROM 105, for example, which serves as a storage medium readable by the CPU 101, before the manufacturer of the portable terminal shown in
The display section 600 is formed with a plurality (m) of data signal lines SL1 through SLm, a plurality (n) of scanning signal lines GL1 through GLn, and a plurality (m×n) of pixel formation portions 610 disposed correspondingly to intersections made by the m data signal lines SL1 through SLm and the n scanning signal lines GL1 through GLn. Hereinafter, if these m data signal lines SL1 through SLm are not differentiated from each other, they will simply be called “data signal line SL”, and if these n scanning signal lines GL1 through GLn are not differentiated from each other, they will simply be called “scanning signal lines GL”. The m×n pixel formation portions 610 are formed in a matrix pattern. Each pixel formation portion 610 is constituted by: a TFT 611 which serves as a switching element having its gate terminal, serving as a control terminal, connected to a scanning signal lines GL that passes through a corresponding one of the intersections while having its source terminal connected to the data signal lines SL that passes said intersection; a pixel electrode 612 connected to a drain terminal of the TFT 611; a common electrode 613 provided commonly to the plurality of pixel formation portions 610; and a liquid crystal layer which is sandwiched between the pixel electrode 613 and the common electrode 113 and is common to these pixel formation portions 110. In the above, the pixel electrode 612 and the common electrode 613 form a liquid crystal capacitance, which functions as a pixel capacitance Cp. It should be noted here that typically, an auxiliary capacitance is provided in parallel to the liquid crystal capacitance for ensured voltage holding at the pixel capacitance Cp. Therefore, the pixel capacitance Cp is actually constituted by the liquid crystal capacitance and the auxiliary capacitance.
In the present embodiment, the TFT 611 is provided by a TFT which includes an oxide semiconductor layer as its channel layer (hereinafter called “oxide TFT”) and has a channel etch structure. In this channel-etch-structure TFT, the source electrode and the drain electrode are disposed on the oxide semiconductor layer, at a space from each other, to sandwich a channel region of the transistor, with the source electrode and the drain electrode having their mutually opposed ends in contact with the oxide semiconductor layer. In other words, the source electrode and the drain electrode are disposed to make contact with an upper surface of the oxide semiconductor layer. The oxide semiconductor layer includes an In—Ga—Zn—O semiconductor (oxide semiconductor of an indium, gallium and zinc). It should be noted here that the oxide semiconductor layer may have a laminated structure including two or more layers.
An In—Ga—Zn—O semiconductor includes a ternary oxide containing In (indium), Ga (gallium) and Zn (zinc). There is no specific limitation to proportion (ratio) between In, Ga and Zn, so the ratio may be In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, and so on. In the present embodiment, a semiconductor film which contains In, Ga and Zn at a ratio of 1:1:1 is utilized. A TFT, which includes an In—Ga—Zn—O semiconductor layer, has a high mobility (greater than 20 times as compared to those which make use of an amorphous silicon in its channel layer, or those called a-SiTFT) and low leak current (smaller than 1/100 as compared to an a-SiTFT); and therefore, is suitable as a driving TFT and a pixel TFT. Use of TFT which includes an In—Ga—Zn—O semiconductor layer makes it possible to dramatically reduce power consumption in a display device.
The oxide semiconductor layer may be made from whichever one of amorphous, crystalline and microcrystalline materials. If the oxide semiconductor layer has a laminated layer structure, these materials may be used in whichever combinations. When crystalline In—Ga—Zn—O semiconductors are utilized, it is preferable that the crystalline In—Ga—Zn—O semiconductors have their c axis substantially vertical to the layer surface. Crystal structures of the In—Ga—Zn—O semiconductors described above are disclosed in JP-A 2012-134475 Gazette. The entire contents disclosed in JP-A 2012-134475 Gazette are incorporated herein by reference.
The oxide semiconductor layer may include other oxide semiconductors in place of the In—Ga—Zn—O semiconductors. For example, the layer may contain In (indium), Sn (tin), Zn (zinc) in the form of an In—Sn—Zn—O semiconductor (such as In2O3—SnO2—ZnO). Other examples include Zn—O semiconductors (ZnO), In—Zn—O semiconductors, Zn—Ti—O semiconductors, Cd—Ge—O semiconductors, Cd—Pb—O semiconductors, CdO (Cadmium oxide), Mg—Zn—O semiconductors, and In—Ga—Sn—O semiconductors. It should be noted here that use of an oxide TFT as the TFT 611 represents one example; a silicon TFT may be used instead.
The display control circuit 200 is implemented typically as an IC (Integrated Circuit). The display control circuit 200 receives data DAT from the host 100 via an FPC 70, and in response to this, generates and outputs a data-side control signal SCT, a scanning-side control signal GCT, and a common voltage Vcom. The data-side control signal SCT is supplied to the data signal line drive circuit 310. The scanning-side control signal GCT is supplied to the scanning signal line drive circuit 320. The common voltage Vcom is supplied to the common electrode 613. In the present embodiment sending/receiving of the data DAT between the host 100 and the display control circuit 200 is performed via an interface which conforms to MIPI-DSI Standards as has been described. The interface conforming to MIPI-DSI Standards enables high-speed data transfer.
The data signal line drive circuit 310 generates and outputs data signal to be supplied to the signal lines SL, based on the data-side control signal SCT. The data-side control signal SCT contains, for example, a digital image signal corresponding to RGB data RGBD, a source start pulse signal, a source clock signal, a latch strobe signal, and a polarity switching signal. In accordance with the source start pulse signal, the source clock signal and the latch strobe signal, the data signal line drive circuit 310 operates its unillustrated shift register, sampling latch circuit, etc., obtains digital signals based on the digital image signal, converts the obtained digital signals with an unillustrated DA conversion circuit, and thereby generates data signals.
The scanning signal line drive circuit 320 repeats application of active scanning signals to the scanning lines GL in accordance with the scanning-side control signal GCT at a predetermined cycle. The scanning-side control signal GCT contains, for example, a gate clock signal and a gate start pulse signal. The scanning signal line drive circuit 320 operates its unillustrated shift register, etc. in accordance with the gate clock signal and gate start pulse signal, and thereby generates scanning signals.
The backlight unit 50 is on a back side of the liquid crystal display panel 60, and irradiate the back surface of the liquid crystal display panel 60 with backlight. The backlight unit 50 typically includes a plurality of LEDs (Light Emitting Diodes). The backlight unit 50 may be controlled by the display control circuit 200, or controlled by other method. If the liquid crystal display panel 60 is of a reflection type, then it is not necessary to have the backlight unit 50.
As described above, the data signals are applied to the data signal lines SL, the scanning signals are applied to the scanning signal lines GL and the backlight unit 50 is driven, whereby an image represented by display image data sent from the host 100 is displayed in the display section 600 of the liquid crystal display panel 60.
The display device 11 which is connected with a data processing device according to the present embodiment has a normal driving mode and an intermission driving mode as driving modes of the display section 600. In the normal driving mode, the display device 11 repeats sequential scanning of the scanning signal lines GL1 through GLn using one frame period (1 vertical scanning period) as a cycle while driving the data signal lines SL1 through SLm, whereby a display image in the display section 600 is refreshed every frame period.
In the intermission driving mode, on the other hand, the display control circuit 200 controls the data signal line drive circuit 310 and the scanning signal line drive circuit 320 in such a manner that that a refreshing period (hereinafter may also called “RF period”) in which a display image is refreshed and a non-refreshing period (hereinafter also called NRF period”) in which all the scanning signal lines GL1 through GLn are brought into a de-selected state are alternated with each other.
As has been described, “one frame period” is a period for refreshing one screen, and the length of one frame period in the present embodiment is equal to a commonly utilized length of one frame period (16.67 ms) used in display devices of a refreshing rate of 60 Hz. In
Next, a configuration of the display control circuit 200 will be described. The display control circuit 200 in the display device 11 connected with the data processing device according to the present embodiment utilizes a DSI video mode and does not have a RAM which serves as a frame buffer.
The DSI communication section 31a which conforms to MIPI-DSI Standards receives data DAT from the host 100 in the video mode. The data DAT contains RGB data RGBD which represents image-related data, a vertical synchronization signal VSYNC and horizontal synchronization signal HSYNC serving as synchronization signals, a data enable signal DE, a clock signal CLK and command data CM. The command data CM contains data related to various controls. Upon receiving the data DAT from the host 100, the DSI communication section 31a supplies the RGB data RGBD which is contained in the data DAT to the latch circuit 34 via the checksum circuit 32; supplies the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the data enable signal DE, and the clock signal CLK to the timing generator 35, and supplies the command data CM to the command register 37. It should be noted here that the command data CM may be sent from the host 100 to the command register 37 via an interface which conforms to I2C (Inter Integrated Circuit) Standards or SPI (Serial Peripheral Interface) Standards. In this case, the interface section 31 includes a receiver section which conforms to I2C Standards or SPI Standards. The RGB data RGBD will also be called “image data”; the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the data enable signal DE, and other signals may be collectively called “timing signals”.
The interface section 31 is configured to transfer information which is related to LCD driving and is held in the display control circuit 200, to the data processing device 100, i.e., to the host, via the interface conforming to MIPI-DSI Standards or an interface conforming to I2C Standards or SPI Standards, upon issuance of a predetermined command from the host. Examples of the information include counter values such as a non-refreshing count which will be described later, a polarity imbalance count, and command data such as non-refreshing frame count NREF which will be described later. Further, the interface section 31 is configured to stop or start specific circuits within the display control circuit 200 upon issuance of a predetermined command from the host, and turn off power supply to said specific circuits. For example, when a command instructing a return from Intermission State 2 to be described later to Normal State is issued from the host as the predetermined command, the interface section 31 starts the stopped circuits (not only first circuits but also second circuits which will be described later), and sends a return completion notification to the host at the time when resumption of operation of the circuits being stopped is confirmed.
In addition, the interface section 31 measures time (hereinafter referred to as “return time”) from receiving of the return instruction to the sending of the return completion notification, and holds this as a return time measurement value in the command register 37. When the power is turned off, the return time measurement value is stored in an NVM 38 described later by the command register 37. When the power supply is turned on, the return time measurement value is read out from the NVM 38 by the command register 37, held in the command register 37, and updated by the interface section 31 according to the measurement of the return time. Also, instead of measuring the return time, a return time assumption value may be stored in advance in the NVM 38. In a fourth embodiment to be described later, the interface section 31 reads the return time measurement value from the NVM 38 via the command register 37 in response to a request from the host at the time of turning on the power, and sends it to the host.
The checksum circuit 32 is configured to perform an arithmetic operation (checksum) to obtain a checksum value and store the obtained checksum value in the memory 32a each time it receives one screen-ful of RGB data RGBD. Specifically, the checksum circuit 32 obtains a checksum value of a set of RGB data RGBD for a given frame (preceding frame), stores the obtained checksum value in the memory 32a, and then obtain a checksum of a set of RGB data RGBD for the frame that follows immediately after (current frame or subsequent frame). The checksum value of the current frame and the checksum value of the preceding frame stored in the memory 32a are compared to each other. If the two values are equal to each other, it is determined that the two images are identical with each other; if the two values are different from each other, it is determined that the two images are different from each other. The result is a checksum result data CRC, which is then sent to the timing generator 35. The checksum circuit 32 is utilized as described above because it is easy to reliably determine whether or not the RGB data RGBD is updated, and the method does not require a memory of a large capacity. The checksum circuit 32 may also be called “image-change detection circuit”. Alternative arithmetic operations other than checksum may be utilized to determine whether or not the images are identical. In such a case, the checksum circuit 32 is replaced with a different circuit for such an arithmetic operation. Hereinafter, description will assume that the checksum value is a result of checksumming a set of one screen-ful of image data and is a value obtained for each frame. However, a checksum value may be obtained from predetermined lines or a predetermined block for example.
The command register 37 holds command data CM. The command register 37 has three registers 37a through 37c, each storing a value for a different setting from others. An example is a non-refreshing frame count NREF which determines the number of frames for which refreshing is not performed.
The NVM 38 holds setting data SET for various kinds of control. The command register 37 reads the setting data SET which is held in the NVM 38, and also updates the setting data SET in response to command data CM. The command register 37 supplies the timing control signal TS and the setting values stored in the registers 37a through 37c to the timing generator 35, and a voltage setting signal VS to the built-in power supply circuit 39 in response to the command data CM and the setting data SET.
The timing generator 35 receives the checksum result data CRC from the checksum circuit 32. If the checksum result data CRC indicates that the RGB data RGBD is not been changed, the timing generator 35 increments the value of the counter 35a, and then compares said value of the counter 35a with the non-refreshing frame count NREF which is stored in the register 37c. If the value of the counter 35a is smaller than the non-refreshing frame count NREF, refreshing is not performed. As a result, the same image is continuously displayed in the display section 600. On the other hand, if the value of the counter 35a is greater than the non-refreshing frame count NREF, a control signal necessary to perform screen refreshing is supplied to the latch circuit 34 and the counter 35a is reset.
The timing generator 35 generates control signals for controlling the latch circuit 34, the data-side control signal output section 36 and the scanning-side control signal output section 42 based on the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the data enable signal DE, the clock signal CLK and a built-in clock signal ICK which is generated in the OSC 41, and provides the signals to respective components.
When performing refreshing, there can be a case where the timing generator 35 requests the host 100 to send data DAT. In this case, a request signal REQ is generated based on vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC, data enable signal DE, clock signal CLK, timing control signal TS, and built-in clock signal ICK generated in the OSC 41, and the generated request signal REQ is sent to the host 100. Upon receiving the request signal REQ, the host 100 sends the data DAT to the DSI communication section 31a of the display control circuit 200. It should be noted here that the OSC 41 is not an essential constituent element if the display control circuit 200 has a Video Mode RAM Through configuration.
The latch circuit 34 provides the data-side control signal output section 36 with RGB data RGBD for each line based on a control signal from the timing generator 35. As described above, screen refreshing is performed at a necessary timing, thereby replacing an image which is currently displayed in the display section 600 with the same or a changed image.
The built-in power supply circuit 39 generates and outputs a power voltage, and a common voltage Vcom, for use at the data-side control signal output section 36 and the scanning-side control signal output section 42, based on electric power from the host 100 and a voltage setting signal VS from the command register 37.
The data-side control signal output section 36 generates the data-side control signal SCT based on the RGB data RGBD from the latch circuit 34, the control signal from the timing generator 35, and a power source voltage from the built-in power supply circuit 39; and provides this signal to the data signal line drive circuit 310.
The scanning-side control signal output section 42 generates the scanning-side control signal GCT based on the control signal from the timing generator 35 and the power source voltage from the built-in power supply circuit 39; and provides this signal to the scanning signal line drive circuit 320.
It should be noted here that since the display device 11 is provided by an LCD module, AC driving is utilized to drive the display section 600 to avoid deterioration of the liquid crystal. In other words, polarity (voltage polarity at the pixel electrode 612 with respect to the voltage Vcom at the common electrode 613 as a baseline) of data signal supplied to each pixel formation portion 610 in the display section 600 is inversed for every predetermined period (hereinafter, this predetermined period will be called “inversion cycle”) for a purpose that the voltage applied to the liquid crystal in the display section 600 will have a time average value or an integral value of “zero”. In an intermission driving mode, however, the inversion cycle is significantly longer than in normal driving mode. Because of this, impurity ions distributed unevenly in the liquid crystal of the display section 600 can create a large accumulation of charge (hereinafter simply called “charge imbalance”), and there can be cases where power supply to the display device is turned OFF while the charge imbalance is large. To solve this, there is an arrangement that a total time for which a positive-polarity data voltage was applied to a specific pixel formation portion in the display section 600 and a total time for which a negative-polarity data voltage was applied to the same specific pixel formation portion are monitored; a difference between the two values is held by a predetermined counter; and the value in the counter is updated as the polarity inversion goes on (hereinafter this counter will be called “polarity imbalance counter”). In this case, the value of the polarity imbalance counter is another consideration in determining the refreshing timing of display image.
Next, operation of the data processing device (host) 100 for displaying an image in the display device 11 configured as described above will be described with reference to
As has been described, when updating a display image, each application Appi (i=1, 2, 3, . . . ) writes new display image data into the image buffer 12f (display image data updating) by using the FB access processing section 133 via the surface flinger 121 in the AP frame work 120 (see
The image buffer 12f is implemented as a memory area allocated in the memory section 12, and its size changes in accordance with extension of its memory area and release of the extension as described later. The image buffer 12f can be extended in units of a memory area (hereinafter referred to as “frame buffer area” or “FB area”) for storing display image data for one frame. Hereinafter, a configuration and operation of the image buffer 12f will be described with reference to
As shown in
As shown in
Of the four FB areas 12fA, 12fB, 12fC, and 12fD constituting the image buffer 12f in the extension state in the present embodiment, one FB area serves as a front buffer, the other three FB areas serve as back buffers, and the three back buffers are ranked (hereinafter referred to as “first back buffer”, “second back buffer”, “third back buffer” in descending order of higher back buffers). When new display image data is supplied to the image buffer 12f in a state in which reading of the display image data from the front buffer is incomplete, the new display image data is written into the first back buffer. When new image data is further supplied to the image buffer 12f, this new display image data is written into the second back buffer. In this way, when sets of new display image data are sequentially supplied to the image buffer 12f in a state in which reading of the display image data in the front buffer is not completed, the sets of new display image data are sequentially written into the back buffers in order from the one with the highest ranking.
The update detection section 132 is implemented as a timer interrupt handler which is activated by the timer interruption generated by the above-described period timer at intervals of one frame period (16.67 ms in the present embodiment).
First, presence or absence of the above-described access event notification is checked to determine if display image data in the image buffer 12f is updated, that is, if new display image data is written into a back buffer in the image buffer 12f (Step S12). For this determination, a function of the OS 130 (e.g. a system function such as “wait”) for receiving the access event is utilized.
If the result of determination in Step S12 indicates that the display image data in the image buffer 12f is updated, the CPU proceeds to Step S14 and sends a signal to notify the update of the display image data (hereinafter called “update signal”), to the DSI controller 135 (Step S14). Thereafter, a variable which indicates a length of the periods during which the display image data has not been updated (hereinafter called “first non-update variable”) Inup is reset to “0” (Step S16), and then this timer interrupt handler is terminated.
If the result of determination in Step S12 does not indicate an update of the display image data in the image buffer 12f, the CPU proceeds to Step S18 and increases the value of the first non-update variable Inup by “1” (Step S18), and thereafter, checks whether or not the first non-update variable Inup is greater than a predetermined criterion value Nnup (“2” for example) (Step S20). If the result of determination shows that the first non-update variable Inup is not greater than the criterion value Nnup, this timer interrupt handler is terminated. If the result of determination shows that the first non-update variable Inup is greater than the criterion value Nnup, a signal which indicates that updating of the display image data in the image buffer 12f has not been performed for a predetermined time (hereinafter called “non-update signal”) is sent to the DSI controller 135 (Step S22). However, sending of the non-update signal is not executed or is ignored if the DSI controller 135 is in an intermission state (Intermission State 1 or 2, with Video OFF) (in other words, from an execution time point of Step S45, through steps shown in
Once the non-update signal is sent, the first non-update variable Inup is reset to “0” (Step S24), and this timer interrupt handler is terminated. The criterion value Nnup is a value selected for a judgment that the display image should be regarded as a still image if the first non-update variable Inup is greater than the criterion value Nnup. Therefore, the criterion value Nnup is not limited to “2”; rather, any appropriate value greater than “1” may be selected as a criterion to see whether an image to be displayed is a changed image. The first non-update variable Inup is initialized to “0” when the data processing device 100 is started.
This timer interrupt handler is started every frame period as has been described, but once started, it is terminated within a much shorter period than one frame period as will be understood from
Next, operation of the DSI controller 135 in the video driver 131 will be described. In the DSI video mode, display image data is transferred from the host, i.e., the data processing device 100, to the display device 11 for each frame period. In the present embodiment, however, in order to reduce power consumed by the host in the intermission driving mode, the DSI controller 135 has two operation states, i.e., Normal State (Video ON) in which display image data is transferred to the display device 11 for each frame period, and Intermission State (Vide OFF) in which transfer of display image data to the display device 11 is stopped when there is no need for updating the display image in the display device 11. The DSI controller 135 is implemented as a process (including threads) which operates as part of the OS 130 in the kernel space, or in other words implemented as a system process, and this system process enters a sleep state in the above-described Intermission State, under a process management by the OS 130 (a system function such as “sleep” is utilized for this).
Specifically, when the data processing device 100 is started, the CPU 101 determines whether or not display image data in the image buffer 12f is updated (Step S32). The determination in Step S32, that is, whether or not display image data in the image buffer 12f is updated is made by receiving an update signal or a non-update signal from the timer interrupt handler (see Steps S14 and S22 in
The image buffer 12f can store display image data for a plurality of frames (see
If a non-update signal is determined to be received in Step S32, it means that display the image data in the image buffer 12f is not updated for a predetermined amount of time. In this case, the process proceeds to Step S36 to determine whether or not the image buffer 12f is extended. As a result of this determination, if the image buffer 12f is not extended, the process proceeds to Step S39. On the other hand, if the image buffer 12f is extended, it is determined whether the second no-update variable Jnup is greater than or equal to a preset number (hereinafter referred to as “the number of return time frames)” Nrt, which is the number of frame periods corresponding to the return time (Step S37). As a result of this determination, if the second no-update variable Jnup is smaller than the number of return time frames Nrt, the process proceeds to Step S39. If the second no-update variable Jnup is greater than or equal to the number of return time frames Nrt, the extension portion of the image buffer 12f is released (Step S38), and then the process proceeds to Step S39. However, if there is a possibility that one of the display image data stored in the FB areas 12fC and 12fD as the extension portion is possibly read out, the image buffer 12f remains in the extension state without releasing the extension portion, and releases it when all the unread display image data in the extension portion has been read out. That is, at the time point when all the display image data stored in the FB areas 12fC, 12fD as the extension portion has been transferred to the LCD and neither of the FB areas 12fC, 12fD serves as a front buffer, the FB areas 12fC, 12fD are released. Here, in the case of releasing the extension portion of the image buffer 12f, memory management function provided by the OS 130 is used. As a result, in the present embodiment, among the four FB regions 12fA to 12fD constituting the image buffer 12f in the extension state (see
In Step S39, there is obtained driver status information, i.e., information regarding driving state at the display device 11 (hereinafter called “LCD driving information”). This LCD driving information contains a count of the frames in the non-refreshing period (value in the counter 35a); a value which indicates a difference between a total time for which a positive-polarity data voltage was applied to a specific pixel formation portion in the display section 600 and a total time for which a negative-polarity data voltage was applied to the same specific pixel formation portion (value in the polarity imbalance counter); etc., and therefore can be understood as information regarding determination on refreshing timing of display image in the display device 11 (hereinafter called “refreshing-related information”). In the present embodiment, at least a value in the counter 35a (hereinafter called “non-refreshing count”) in the display control circuit 200 (
The above-described LCD driving information from the display device 11 is obtained by using commands conforming to MIPI-DSI Standards, via an interface conforming to MIPI-DSI Standards. Alternatively, the information from the display device 11 may be obtained via an interface which conforms to I2C Standards or SPI Standards (see
Next, the CPU determines whether or not this refreshing start preceding frame count REF_F is “1” (Step S40). If the result of determination indicates that the refreshing start preceding frame count REF_F is “1”, the CPU proceeds to Step S34 to cause the DSI section 106 to transfer display image data stored in the image buffer 12f to the display device 11. Thereafter, the CPU returns to Step S32. The display device 11 refreshes the display image using this display image data. On the other hand, if the result of determination indicates that the refreshing start preceding frame count REF_F is not “1”, i.e., is “2” or a greater number, the CPU proceeds to Step S45 in
Moving to Step S45 in
In the present embodiment, the intermission state of the DSI controller 135 consists of two levels, i.e., Intermission State 1 and Intermission State 2. Depending on a driving state of the display device 11 at a time point when a determination is made to shift from Normal State to Intermission State, selection is made as to which of the Intermission State 1 and Intermission State 2 the shifting should be made to. Intermission State 2 is selected if it is possible to stop a greater number of circuits in the display device 11 or to turn off a greater number of power supplies for greater power saving than in Intermission State 1. In Step S48 CPU 101 determines which of Intermission State 1 and Intermission State 2 should be selected. In the present embodiment, Intermission State 1 is selected if the refreshing start preceding frame count REF_F calculated in Step S39 is not greater than “10”, whereas Intermission State 2 is selected if the number is greater than “10”. The Intermission State 1 can be considered as “short intermission state” because the time to start of the next refresh in the Intermission State 1 is shorter than in the Intermission State 2. It should be noted here that the selection criteria is not limited to whether or not the refreshing start preceding frame count REF_F is not greater than “10”, but selection may be made by taking characteristics, operating conditions, etc. of the display device 11 into consideration.
If the result of determination in Step S48 shows that the refreshing start preceding frame count REF_F is not greater than 10, shifting should be made to Intermission State 1, so the CPU proceeds to Step S52. In Step S52, the host (DSI controller 135 therein) assumes a sleep state. Specifically, under the process management by the OS 130, the CPU 101 executes system functions for bringing the process which is working as the DSI controller 135 into the sleep state. The process which assumes the sleep state, i.e., the process which is now stopped, is resumed (brought back to an active state) when the refreshing start timer times out as the earlier-mentioned length of time (REF_F*16) ms has elapsed. However, even before the elapse of the time (REF_F*16) ms, the process management is configured to resume the process if it receives an update signal (Step S14 in
Step S35 causes the DSI section 106 to resume its operation for transferring display image data to the display device 11. In other words, video signal output from the data processing device 100 to the display device 11 is started. Thereafter, the CPU proceeds to Step S34 to cause the DSI section 106 to transfer display image data in the image buffer 12f to the display device 11 (to be exact, the display image data in the front buffer described later), and then the CPU returns to Step S32. It should be noted here that the DSI communication section 31a in the display control circuit 200 is configured to resume its operation if it receives a video signal (specifically, the vertical synchronization signal VSYNC) from the host in the intermission state (power saving state).
If the result of determination in Step S48 indicates the condition for shifting to Intermission State 2 is satisfied (if the refreshing start preceding frame count REF_R is greater than 10 in the present embodiment), the CPU proceeds to Step S54 and extends the image buffer 12f by FB areas of two frames (
Thereafter, LCD driving information is obtained as driver status information from the display device 11 (Step S56) by using commands based on MIPI-DSI Standards. The LCD driving information contains not only counter information such as the non-refreshing count, but also information for resuming various circuits (specific circuits called “driver engine”) within the display control circuit 200 which is to be stopped in the next Step S58 (see Step S67).
After the LCD driving information is obtained, predetermined various circuits in the display control circuit 200 of the display device 11 are stopped by using commands based on MIPI-DSI Standards, etc., and instructions for turning OFF logic power sources and analog power sources used by these circuits, namely, a pause instruction is sent to the display device 11 (Step S58). Circuits which are stopped in the display control circuit 200 in Intermission State 1 (hereinafter referred to as “first circuits”) are those each having a relatively short time required for resuming operation from the stopped state (this required time is equal to or shorter than a predetermined time), the first circuits being hatched with slanted dot lines drawn in one direction in
Thereafter, the DSI controller 135 assumes a sleep state (Step S60). Specifically, under the process management by the OS 130, the CPU 101 executes system function for bringing the process which is working as the DSI controller 135 into the sleep state. The process which is in the sleep state and therefore is a non-operating process resumes its operation once the time (RER_F*16) ms which was set in Step S46 has elapsed and the refreshing start timer times out. It should be noted here that, the process management by the OS 130 is configured such that even when the above time (REF_F*16) ms has not elapsed yet, the process is restarted upon receiving the update signal (Step S14 in
In Step S62, corrections are performed to logic information related to those circuits in the display control circuit 200 which were stopped in Intermission State 2. In the present embodiment, corrections are made to the non-refreshing count and the polarity imbalance count which were obtained in Step S56, based on the refreshing start preceding frame count REF_F (length of the period of Intermission State) so as to compensate for the circuit stoppage.
Next, power supply is resumed to each of the circuits which were stopped in the display control circuit 200, and instructions for starting these stopped circuits are sent as a return instruction to the display device 11 (Step S64) using commands based on MIPI-DSI Standards. Thereafter, the process waits until it receives a return completion notification from the display device 11 (step S65), and upon receiving the return completion notification, it proceeds to Step S67.
In Step S67, using commands which are based on MIPI-DSI Standards, LCD driving information which contains logic information after the correction is sent to the display device 11 so that this LCD driving information is re-set in the display control circuit 200 of the display device 11.
After transmitting the LCD drive information to the display device 11, the process proceeds to Step S35 of resetting the second no-update variable Jnup to “0”, and then proceeds to Step S35 corresponding to Normal State, in which the CPU causes the DSI section 106 to resume its operation for transferring display image data to the display device 11 (Start video signal output). Thereafter, the process proceeds to Step S34 to cause the DSI section 106 to transfer display image data stored in the image buffer 12f to the display device 11, and then the CPU returns to Step S32.
Next, a basic operation of the above-described present embodiment will be described with reference to
(A) of
If the refreshing start preceding frame count REF_F is greater than “1”, video signal output from the DSI section 106 is stopped (Step S40 and S45), and a determination is made based on this refreshing start preceding frame count REF_F as to whether or not conditions for shifting to Intermission State 2 are met (Step S48; (2) in (A) of
Thereafter, when the refreshing start timer times out, video signal output by the DSI section 106 is resumed (Step S35), and in order to refresh the display image in the LCD, refreshing frame data (data representing the display image A) is transferred from the host to the LCD (Step S34; (4) in (A) of
As described above, if the LCD displays the Image A as a still image (if the image to be displayed is not changed), and the refreshing start preceding frame count REF_F which is calculated from LCD driving information obtained from the LCD is not greater than “10”, the data representing the Image A is transferred as refreshing frame data to the LCD for each length of time equal to the refreshing start preceding frame count REF_F; and in those periods in which the transfer is not made, the DSI controller 135 in the video driver 131 of the host assumes a sleep state, namely, the host and the LCD assume Intermission State 1.
(B) of
In this example shown in (B) of
Thereafter, when the refreshing start timer times out, information necessary for the next refreshing of the display image in the LCD, i.e., information and instructions for bringing the LCD back into Normal State, are sent to the LCD and the host waits until it receives a return completion from the LCD (Steps S62 through S65; (5) and (6) in (B) of
Upon receiving the return completion notification from the display device 11 ((6) in (B) of
As has been described above, if the LCD displays the Image A as a still image and if the refreshing start preceding frame count REF_F calculated from LCD driving information obtained from the LCD is greater than “10”, the LCD is brought into Intermission State 2 and the predetermined circuits in the LCD are stopped or their power supply is turned off until the next refreshing of the display image in the LCD, for further reduction in power consumption in the LCD (see
In the basic operation shown in
First, for comparison, assuming a configuration in which the image buffer 12f is not extended (hereinafter referred to as “image buffer non-extended configuration”), there will be made a description of operation of returning from Intermission State 2 to Normal State through the returning state due to a data update in the image buffer 12f caused by a user operation on the input operation section 16 in the image buffer non-extended configuration, before a description of the above operation in the present embodiment.
In the example shown in
From the fifth frame period to the 50th frame period, no new display image data is supplied to the image buffer 12f. Therefore, after the display image data D5 in the FB area 12fA serving as the front buffer in the fifth frame period is transferred to the LCD and the display image is refreshed in the LCD, transfer of the display image data to the LCD stops and the display image on the LCD is not refreshed until the 50th frame period. In this example, the host and the LCD shift to Intermission State 2 at the sixth frame period (Steps S36 through S48 and S54 through S60), and the host and LCD are in Intermission State 2 until the 50th frame period.
In the 51st frame period, new display image data D6 is supplied to the image buffer 12f due to a user operation on the input operation section 16 and written into the FB area 12fA as the back buffer, which is detected as a data update in the image buffer 12f, and a return instruction is transmitted from the host to the LCD (Step S64). In the 52nd frame period, the FB area 12fA in which the display image data D6 is stored becomes the front buffer, display image data D7 newly supplied to the image buffer 12f is written into the FB area 12fB as the back buffer while the display image data D6 is read from the FB area 12fA and transferred to the LCD. However, in the LCD, all the circuits can not resume their operations immediately and at this point it is in the returning state. As a result, the display image data D6 is missing during this transfer (occurrence of frame missing). In the image buffer non-extended configuration, since the image buffer 12f is full at this point, Step S65 of receiving the return completion notification is not executed.
As shown in
At the beginning of the 54th frame period, the LCD is in Normal State, and each circuit in the LCD resumes its operation. Therefore, the display image data D8 in the FB area 12fA as the front buffer is transferred to the LCD without missing, and the display image is refreshed by the display image data D8 in the LCD. Also in the 54th frame period, new display image data D9 is written into the FB region 12fB as the back buffer, and also in the 55th frame period, new display image data D10 is written into the FB region 12fA as the back buffer. The display image data D9 and D10 are sequentially transferred to the LCD without missing in the same manner and are used for refreshing the display image on the LCD.
It should be noted here that if the time point of returning from Intermission State 2 to Normal State is known beforehand, it is possible to avoid the frame missing as described above. That is, as shown in
In the example shown in
During any of the eighth and ninth frame periods, new display image data is not written into the back buffer, but the display image data D5 stored in the front buffer is transferred to the LCD to be used for refreshing the display image in the LCD. When the 10th frame period starts, the update detection section 132 serving as an interrupt handler sends a no-update signal to the DSI controller 135 (Step S22 in
The host is set to be in Intermission State 2 until the refresh start timer times out according to the refreshing start preceding frame count REF_F after the 10th frame period (Steps S46 and S60). However, in the example shown in
Thereafter, (video driver 131 of) the host is in a waiting state until operation of the stopped circuits in the LCD is resumed and a return completion notification is received from the LCD. During the 52nd frame period in the waiting state, the FB area 12fA having the display image data D6 stored therein serves as the front buffer, and new display image data D7 is written into the FB area 12fB as the first back buffer due to a user operation on the input operation section 16. Also during the 53rd frame period, new display image data D8 is written into the FB area 12fC as the second back buffer due to a user operation on the input operation section 16.
Also, during the 53rd frame period, operation of each circuit in the LCD is resumed and a return completion notification is sent from the LCD to the host (Step S65). As a result, during the 54th frame period, the display image data D6 stored in the FB region 12fA as the front buffer is transferred to the LCD, and the display image of the LCD is refreshed with this display image data D6 (Steps S35, S34). Here, although a delay corresponding to the period of the returning state occurs with respect to the refreshment of the display image on the LCD, no frame missing occurs. Furthermore, during the 54th frame period, new display image data D9 is written into the FB area 12fD as the third back buffer due to a user operation on the input operation section 16.
Thereafter, while sets of new display image data are supplied to the image buffer 12f by user operations on the input operation section 16, for each frame period a set of display image data Dj is written into the image buffer 12f including the four FB areas 12fA to 12fD and a set of display image data Dj−3 is read from the same (j=10, 11, 12, . . . ) by the first-in first-out method.
As described above, according to the present embodiment, the image buffer 12f is extended in the host when shifting to Intermission State 2 (Step S54;
As described above, in the present embodiment, the image buffer 12f is extended when the host and the LCD shift from Normal State to Intermission State 2 ((1) in
In the example shown in
In the third frame period, new display image data D2 supplied to the image buffer 12f due to a user operation on the input operation section 16 is written into the FB area 12fA as the back buffer, which is detected as a data update in the image buffer 12f, so that a return instruction is sent from the host to the LCD (Steps S60 through S64). After that, (video driver 131 of) the host is in a waiting state until operation of the stopped circuit in the LCD is resumed and a return completion notification is received from the LCD. The host measures duration of this waiting state, that is, time from sending of the return instruction till receiving of the return completion notification.
During the fourth frame period in the waiting state, the FB area 12fA having the display image data D2 stored therein serves as the front buffer, and new display image data D3 is written into the FB area 12fB as the first back buffer due to a user operation on the input operation section 16. During the fifth frame period as well, new display image data D4 is written into the FB area 12fC as the second back buffer due to a user operation on the input operation section 16.
During the fifth frame period, the return completion notification from the LCD is received by the host (Step S65). As a result, during the sixth frame period, the display image data D2 in the FB area 12fA as the front buffer is transferred to the LCD, and the display image of the LCD is refreshed with the display image data D2 (Steps S35, S34). Also during the sixth frame period, new display image data D5 is written into the FB area 12fD as the third back buffer due to a user operation on the input operation unit 16.
During the seventh frame period, new display image data D6 is written into the FB region 12fA as the first back buffer, and the display image data D3 in the FB region 12fB as the front buffer is transferred to the LCD.
During the eighth frame period, the display image data D4 is read out from the FB region 12fC as the front buffer and is transferred to the LCD, but no new display image data is supplied to the image buffer 12f. The host counts the number of frame periods (hereinafter referred to as “non-update frame periods”) during which there is no data update in the image buffer 12f such as the eighth frame period by using the above-described second no-update variable Jnup (See Step S18 in
During the ninth through fifteenth frame periods, sets of new display image data are supplied to the image buffer 12f due to user operations on the input operation section 16, and for each frame period a set of display image data Dj is written into the image buffer 12f including the four FB areas 12fA to 12fD and a set of display image data Dj−2 is read from the same (j=7 to 13) by the first-in first-out method.
During the sixteenth frame period, the display image data D12 is read out from the FB region 12fC as the front buffer and transferred to the LCD. During the seventeenth frame period, the display image data D13 is read out from the FB region 12fD as the front buffer and transferred to the LCD. During any of the sixteenth and seventeenth frame periods, no new display image data is supplied to the image buffer 12f. Therefore, the number of no-update frame periods (the count value by the host), that is, the second no-update variable Jnup becomes equal to or larger than the number of return time frames Nrt (“2” in the present embodiment) and writing into the FB areas 12fC and 12fD is temporarily terminated ((2) in
During the eighteenth frame period, new display image data D14 is written into the FB area 12fA as the back buffer due to a user operation on the input operation section 16, and the display image data 1D13 in the FB area 12fD as the front buffer is transferred to the LCD. As a result of this transfer, access to the FB areas 12fC, 12fD as the extension portion of the image buffer 12f is completed, and therefore the FB areas 12fC, 12fD are released after this transfer ((3) in
During each frame period after the nineteenth frame period, new display image data Di+1 is written into the back buffer and display image data Di written into the back buffer during the preceding frame period is transferred to the LCD (i=14, 15, 16, . . . ), while new display image data are being supplied to the image buffer 12f due to user operations on the input operation section 16. Since the image buffer 12f is composed of the two FB areas 12fA and 12fB in the 19th frame period and thereafter, the FB area as the back buffer and the FB area as the front buffer are alternately switched between the two FB areas 12fA and 112fB. It is to be noted that the access to such an unextended image buffer 12f is also in accordance with the first-in first-out method like the access to the image buffer 12f in the extension state.
According to the above configuration of the present embodiment, the extension portion of the image buffer 12f extended to prevent the frame missing in the returning state of the LCD is released, when the no-update frame period occurs the number of times which corresponds to the return time (the number of return time frames Nrt) in Normal State. For this reason, it is possible to avoid consuming extra memory in the host in order to prevent frame missing.
As shown in
Thereafter, when there is no more user operation made to the input operation section 16 and therefore there is no more data update in the image buffer 12f, then shifting to Intermission State (Intermission State 1 or 2) is determined; whereupon LCD driving information is obtained from the LCD, and the refreshing start preceding frame count REF_F is calculated from the LCD driving information (more specifically, from a non-refreshing count, etc. contained in the information) (Steps S32 and S39; (1) and (2) in
Next, based on the refreshing start preceding frame count REF_F, determination is made as to whether or not conditions are met for shifting to Intermission State 2 (Step S48; (3) in
Thereafter, when the refreshing start timer times out, video signal output by the DSI section 106 is resumed; the host and the LCD return to Normal State; and in order to refresh the display image in the LCD, refreshing frame data (data representing the display image C) is sent from the host to the LCD (Steps S35 and S34; (4) in
Thereafter, it is determined again whether or not a data update occurs in the image buffer 12f; but at this point again, there is no user operation made into the input operation section 16, so it is determined to shift to Intermission State (Intermission State 1 or 2), and the refreshing start preceding frame count REF_F is calculated from the LCD driving information obtained from the LCD (Steps S32 and S39; (5) and (6) in
Next, based on the refreshing start preceding frame count REF_F, determination is made as to whether or not conditions are met for shifting to Intermission State 2 (Step S48) ((7) in
Thereafter, when the refreshing start timer times out, the DSI controller 135 in the host returns to an active state, and information necessary for the next refreshing of the display image in the LCD (information and instructions for bringing the LCD back into Normal State) are sent to the LCD (Steps S62, S64; (7c) in
After the return instruction is sent from the host to the LCD, the host assumes a waiting state until receiving a return completion notification from the LCD (Step S65). Thereafter, upon receiving the return completion notification from the LCD ((8) in
Further thereafter, video signal output by the DSI section 106 is resumed; the host and the LCD return to Normal State; and in order to refresh the display image in the LCD, refreshing frame data (data representing the display image C) is transferred from the host to the LCD (Steps S35 and S34; (9) in
In the present operation example, when this transfer of the refreshing frame data is coming to its end, the user begins to make operation on the input operation section 16, and so it is determined that a data update in the image buffer 12f occurs (Step S32; (10) in
According to the present embodiment described above, if the display device 11 (LCD) which is connected with the data processing device 100 (host) is operating in the intermission driving mode, the next refreshing timing is determined based on the refreshing start preceding frame count REF_F which is calculated from LCD driving information such as a non-refreshing count, obtained from the LCD, and the host (DSI controller 135 thereof) assumes a sleep state until the next refreshing (Steps S32, S39, S46 and S52; see
Also, according to the present embodiment, the host determines whether or not to shift to Intermission State, i.e., whether or not the image to be displayed is changed or not, based on a data update monitoring at the image buffer 12f (see
Further, in the present embodiment, each time a shift is made to the Intermission State, the next refreshing start timing of the display image is determined based on LCD driving information from the LCD. This makes it possible to significantly reduce power consumption at the host even in comparison with the conventional example in which data for refreshing is sent from the host to the LCD at a predetermined time interval if there is non-update in display image.
According to the present embodiment, Intermission State of the LCD consists of two levels, i.e., Intermission State land Intermission State 2. If the refreshing start preceding frame count REF_F which is calculated from LCD driving information is not greater than a predetermined value (“10” in the present embodiment), Intermission State 1 is selected (Step S52) which allows for quick return to Normal State when there is any change found in the image to be displayed and the changed image must be displayed in the LCD. If the refreshing start preceding frame count REF_F is greater than the predetermined value, it is assumed that there will be a lower probability for bringing the sleeping LCD back to Normal State, and the LCD is shifted to Intermission State 2 (Step S48, S54 through S60; see (B) of
According to the present embodiment, when shifting to Intermission State 2, the image buffer 12f is extended in the host (step S54;
Next, description will cover a data processing device according to a second embodiment of the present invention. Like the first embodiment, this data processing device is also used in a portable terminal configured as shown in
Thereafter, when there is no data update in the image buffer 12f and therefore shifting to Intermission State (Intermission State 1 or 2) is determined again, then LCD driving information is obtained from the LCD not via the DSI interface but via the I2C/SPI interface (Steps S32 and S39; (5) and (6) in
Thereafter, when the refreshing start timer times out, information necessary for the next refreshing of the display image in the LCD (namely, information and instructions for bringing the LCD back into Normal State) are sent to the LCD, the host waits until it receives a return completion notification from the display device 11 (Steps S62 through S65; (6c) in
Other than the above-described differences, specifics in the present operation example are identical with those in the operation example of the first embodiment shown in
As understood from the description made above, exchange of data (information and instructions) are made entirely via the DSI interface in the first embodiment, but in the present embodiment, transfer of instructions and setting information to the LCD, and obtainment of driving information from the LCD are made via the I2C/SPI interface (see (3), (6), (6b), (6c), and (7) in
Next, description will cover a data processing device according to a third embodiment of the present invention. Like the first embodiment, this data processing device is also used in a portable terminal configured as shown in
In the first embodiment, the LCD's display control circuit 200 includes the counter 35a which counts the number of frames having an image which has no change, i.e., the number of frames of a still image, as the non-refreshing frame count (see
The counter setting parameters are thus obtained and then, if a user makes an operation on the input operation section 16 (such as touch panel) whereby a data update occurs in the image buffer 12f, the host and the LCD assume Normal State, and the video driver 131 which includes the DSI controller 135 and the update detection section 132 operates basically as shown in the flow charts in
Also, the non-refreshing count is updated or reset based on the counter setting parameters at the DSI controller 135 or the update detection section 132 in the video driver 131. If the host shifts to Intermission State, the non-refreshing count is corrected when returning from Intermission State to Normal State (Step S62). As has been described, the refreshing counter is implemented by software in the video driver 131 of the host. Therefore, the present embodiment does not require Steps S39 and S56 in the operation of the DSI controller 135 for obtaining the non-refreshing count as LCD driving information.
Next, reference to such drawings as
Thereafter, when there is no data update in the image buffer 12f and therefore shifting to Intermission State (Intermission State 1 or 2) is determined again, then LCD driving information including the non-refreshing count is not obtained from the LCD but the refreshing start preceding frame count REF_F is calculated ((6) in
Thereafter, when the refreshing start timer times out, information necessary for the next refreshing of the display image in the LCD (information and instructions for bring the LCD back into Normal State) are sent to the LCD (Steps S62 through S66; (7c) in
Other than the above-described differences, specifics in the present operation example are substantially the same as those in the operation example of the first embodiment shown in
According to the present embodiment described above, since the host has a function of the refreshing counter, it is possible to obtain the timing of the next refreshing of the display image in the LCD at the host as shown in
Also, according to the present embodiment, counter setting parameters which specify operation of the refreshing counter to match the LCD connected with the host are obtained by the host in an initialization sequence. This makes it possible to refresh the display image in a manner suitable for characteristics and driving state of the LCD while allowing the host to centrally manage the display image refreshing in the LCD.
In the present embodiment, the function of the refreshing counter is implemented in the host by means of software. In addition to this, there may be an arrangement in which the function of the polarity imbalance counter is also implemented in the host by means of software. This makes it possible to determine the next refreshing timing of the display image while taking the polarity imbalance count into consideration, in addition to the non-refreshing count.
Next, description will cover a data processing device according to a fourth embodiment of the present invention. Like the first embodiment, this data processing device is also used in the portable terminal having the configuration shown in
In the first embodiment described above, a size of the extension portion of the image buffer 12f extended to prevent frame missing in the returning state of the display device 11 (LCD) is determined in advance (in the example shown in
When the first method is adopted in the present embodiment, as shown in (A) of
Next, with reference to (B) of
Thereafter, during the 81st frame period, new display image data D6 supplied to the image buffer 12f due to a user operation on the input operation section 16 is written into the FB area 12fA as a back buffer, and a return instruction is sent from the host to the LCD (Steps S60 through S64). Thereafter, the host waits until it receives a return completion notification from the LCD (Step S65).
Here, (the DSI controller 135 of) the host measures duration of the waiting state, that is, time from sending of the return instruction till receiving of the return completion notification, as a return time. For example, when the return instruction is sent to the LCD in Step S64 of
In the example shown in (B) of
In the 84th frame period, transfer of the display image data from the host to the LCD is restarted. While sets of new display image data are supplied to the image buffer 12f due to user operations on the input operation section 16 after the 84th frame period, for each one frame period a set of display image data Dj is written into the image buffer 12f including the four FB areas 12fA to 12fD (the image buffer 12f including the extension portion of two frames) and a set of display image data Dj−3 is read from the same (j=9, 10, 11, . . . ) by the first-in first-out method.
According to the present embodiment as described above, the size of the extension portion of the image buffer 12f extended to prevent frame missing in the returning state of the display device 11 (LCD) is determined based on the measurement result of duration of the returning state. Therefore, it is possible to reliably prevent frame missing without allocating an extra memory area (buffer area).
Next, description will cover a data processing device according to a fifth embodiment of the present invention. Like the first embodiment, this data processing device is also used in the portable terminal having the configuration shown in
In the first embodiment, as shown in
During the third frame period, new display image data D2 supplied to the image buffer 12f due to a user operation on the input operation section 16 is written into the FB area 12fA as a back buffer, and a return instruction is sent from the host to the LCD (Steps S60 through S64). Thereafter, the host waits until it receives a return completion notification from the LCD (Step S65).
In the example shown in
In the sixth frame period, transfer of the display image data from the host to the LCD is restarted. While sets of new display image data are supplied to the image buffer 12f due to user operations on the input operation section 16 in and after the sixth frame period, display image data Dj is written into the image buffer 12f including the four FB areas 12fA to 12fD (the image buffer 12f including the extension portion of two frames) and display image data Dj−3 is read from the same (j=5, 6, 7, . . . ) by the first-in first-out method.
In the present embodiment, upon receiving a restart completion notification from the LCD, the host increases the transfer rate of the display image data to the LCD and the refreshing rate of the display image from the next frame period (the sixth frame period in this example). In the present embodiment, the transfer rate and refreshing rate are changed from 60 [frames/sec] to 80 [frames/sec]. However, the writing rate of new display image data into the image buffer 12f is maintained at 60 [frames/sec] and is not changed. For this reason, during the six frame periods from the sixth through eleventh frame periods, while sets of display image data supplied to the image buffer 12f and written into back buffers are data D5 through D10 of six frames, sets of display image data transferred to the LCD and used for refreshing the display image in the LCD are data D2 through D9 of 8 frames. As a result, it is possible to reduce the number of FB areas in the image buffer 12f from four to two at the end of the eleventh frame period. During the eleventh frame period, new display image data D10 is written into the FB area 12fA as a back buffer, and the transfer of the display image data D9 in the FB area 12fD as a front buffer to the LCD is completed.
In this way, in the example of
In the present embodiment, the number of frame periods Nfast during which the transfer rate to the LCD and the display image refresh on the LCD should be performed at a rate (80 frames/second) higher than the standard rate (60 frames/second), that is, the number of frame periods Nfast during which high speed driving is to be performed can be generally obtained by the following equation:
Nfast=(Ffast*Ndelay)/(Ffast−Forig) (1)
where Ffast is a frequency of the high speed driving, Forig is a frequency when the LCD is driven at the standard rate (a frequency of standard speed driving), and Ndelay is the number of frames for which the extension of the image buffer 12f causes delay. In the above equation (1), “*” is a symbol indicating multiplication. In the example shown in
During the 12th frame period and each frame period thereafter, while sets of new display image data are supplied to the image buffer 12f due to user operations on the input operation section 16, new display image data Di+1 is written into a back buffer and also the display image data Di written into a back buffer during the preceding frame period is transferred to the LCD (i=10, 11, 12, . . . ). It should be noted here that since the image buffer 12f is composed of the two FB regions 12fA and 12fB, one FB area as a back buffer and the other FB area as a front buffer are alternately switched between the two FB areas 12fA and 112fB.
Next, the processing procedure of the DSI controller 135 (see
In the processing procedure of the DSI controller 135 in the present embodiment, there are introduced a drive frequency control variable Ihs for controlling switching between the high-speed driving and the standard speed driving as described above and an extension state flag Fex indicating whether or not the image buffer 12f is in an extension state, and the drive frequency control variable Ihs and the extension state flag Fex are initialized to “0” at starting of the data processing device 100.
As shown in
As a result of the determination in Step S32, if the display image data is not updated in the image buffer 12f (more accurately, when the display image data has not been updated for a predetermined time), the process proceeds to Step S39, obtains driver status information (LCD drive information) in the display device 11 and calculates the number of frames preceding the next refreshing of the display image, that is, the refreshing start preceding frame count REF_F, based on the acquired LCD drive information.
Next, it is determined whether or not the refreshing start preceding frame count REF_F is “1” (Step S40). As a result of this determination, if the refreshing start preceding frame count REF_F is “1”, the process proceeds to the aforementioned Step S80. On the other hand, as a result of this determination, if the refreshing start preceding frame count REF_F is not “1”, that is, if it is “2” or more, the process proceeds to Step S45 in
If the process proceeds to step S45 in
In the processing procedure shown in
According to the above-described Step S66, in the present embodiment, the value of the drive frequency control variable Ihs is equal to the number of frame periods Nfast and the value of the extension state flag Fex is “1” at the time of returning from Intermission State 2 to Normal State.
In the present embodiment, when returning from Intermission State 1 or Intermission State 2 to Normal State, the processing proceeds from Step S52 or S67 shown in
When returning from Intermission State 1 to the normal state, both the values of the driving frequency control variable and the extension state flag Fex are normally “0”, and therefore operation after Step S80 is as described above.
When returning from Intermission State 2 to Normal State, the driving frequency control variable Ihs=Nfast≠0 (see Step S66), and therefore the process proceeds to Step S83, in which the value of the driving frequency control variable Ihs is decremented by 1. Subsequently, the display image data in (a front buffer of) the image buffer 12f is transferred to the display device 11 at the high speed (80 frames/second) (Step S84), and then the process returns to Step S32. Thereafter, when a data update in the image buffer 12f continues due to user operations on the input operation section 16 on the host side, writing of moving image data into the image buffer 12f, etc., Steps S32→S80→S83→S84 (transfer of display image data at the high speed) are repeatedly executed until the drive frequency control variable Ihs becomes “0”. When the drive frequency control variable Ihs becomes “0”, the process proceeds to Step S82.
Since the value of the extension state flag Fex is “1” at this time point (see Step S66), the process proceeds to Step S86, and it is determined whether or not the extension portion of the image buffer 12f extended in Step S54 in Intermission State 2 (the FB areas 12fC and 12fD in the present embodiment (see
If the extension portion of the image buffer 12f is releasable as a result of the determination in Step S86, the FB areas 12fC, 12fD as the extension portion are released (release of the extension state), and the extension state flag Fex is set to “0” (Step S88). Thereafter, the process proceeds to Step S34, and the display image data in (a front buffer of) the image buffer 12f is transferred to the LCD at the standard rate (60 frames/second), and the process returns to Step S32. Thereafter, since Ihs=Fex=0 until the next transition to Intermission State 2, display image data in the image buffer 12f is transferred to the LCD at the standard rate (60 frames/second) every time display image data is updated in the image buffer 12f (Step S32→S80→S82→S34).
According to the present embodiment as described above, as shown in
In each of the above-described embodiments, the intermission state of the host 100 and the display device 11 (LCD) is provided as an intermission state of two stages consisting of the Intermission State 1 and Intermission State 2. However, the present invention is applicable to a case where the LCD requires time (for example, one frame period or more) to return from the intermission state to the normal state even in a configuration in which the intermission state is changed to only one stage in each of the above embodiments. Therefore, in the following, an example of a data processing device having such a configuration will be described as a sixth embodiment of the present invention.
The data processing device according to the present embodiment is also used in a portable terminal configured as shown in
The present embodiment is configured to have only one intermission state corresponding to Intermission State 2 in the first embodiment as an intermission state of the data processing device 100 (host) and the display device 11 (LCD). Therefore, in the present embodiment, the processing procedure of the DSI controller 135 for the intermission state is a procedure shown in
Operation in the present embodiment is also the same as in the first embodiment except for the difference due to having only the intermission state corresponding to Intermission State 2 in the first embodiment as an intermission state of the host and the LCD. Therefore,
Also in the present embodiment as described above, the image buffer 12f is extended (
The present invention is not limited to any of the embodiments described above, but may be varied in many ways within the scope of the present invention. The present invention also includes any combinations of a plurality of the embodiments described thus far, as far as there is no conflict arising from the combination.
For example, although the image buffer 12f is composed of one front buffer and one or more back buffers (
In the case of measuring duration of a returning state of the LCD as return time like the fourth embodiment, when returning from Intermission State (Intermission State 2) to Normal State, transfer of the display image data from the host to the LCD may be resumed at timing based on the return time measurement value without waiting for a return completion notification from the LCD. This simplifies the operation and configuration for returning from Intermission State 2 to Normal State and makes it possible to reduce the delay in refreshing the displayed image on the LCD.
In each of the above embodiments, the interface based on the MIPI-DSI standard, or the interface conforming to the I2C standard or the SPI standard is used for a return completion notification to the host when the LCD returns from Intermission State 2 to Normal State (
In each of the embodiments, means for managing the next refreshing timing of display image in the LCD based on monitoring presence/absence of display image data update in the image buffer 12f is implemented in the host as a component of the video driver 131 which operates in the kernel space, as shown in
Although each embodiment has been described by using a portable terminal as an example (
The present application claims priority based on Japanese Patent Application No. 2015-205672 filed on Oct. 19, 2015 entitled “DATA PROCESSING DEVICE TO WHICH DISPLAY DEVICE IS CONNECTED, AND CONTROL METHOD FOR DISPLAY DEVICE”, the contents of which are incorporated herein by reference.
The present invention is applicable to data processing devices connected with display devices which perform so called intermission driving, and to method for controlling these display devices in these data processing devices.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-205672 | Oct 2015 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2016/080217 | 10/12/2016 | WO | 00 |
