Patent Application
20250125906
This application relates to the communications field, and in particular, to a data processing method and a data processing apparatus.
Continuously driven by 5G, cloud computing, big data, artificial intelligence, and the like, a high-speed optical transmission network is developing towards a large capacity, packetization, and intelligentization. Performing forward error correction (FEC) encoding on transmitted data for error correction can resolve the problem of transmission bit errors, to restore, from received data, original data sent by a transmitter.
Currently, a concatenated FEC transmission solution is proposed. A transmitter device and a transmitter processing module are connected through an attachment unit interface (AUI). The transmitter device performs first FEC encoding on to-be-transmitted data, and sends first-FEC encoded data to the transmitter processing module. The transmitter processing module then performs second FEC encoding on the first-FEC encoded data; performs modulation and mapping on a second-FEC encoded bit sequence, to generate a corresponding modulation symbol sequence; and finally transmits the generated symbol sequence to a receiver through an optical transmission network. The receiver may obtain, by demodulating and decoding the received modulation symbol sequence, information sent by the transmitter.
Generally, concatenated encoding and interleaving are performed before the second FEC encoding, and the first-FEC encoded data is disordered, to enhance error correction performance of the overall FEC solution. In addition, in an actual transmission process of the modulation symbol sequence, a transmission link is affected by a burst factor. Consequently, errors occur in several consecutive symbols in the modulation symbol sequence, and the receiver receives the modulation symbol sequence subject to the burst factor. Because there are a large quantity of consecutive errors, it is difficult to accurately perform error correction through FEC encoding. Consequently, a bit error rate of information transmission is high.
Embodiments of this application provide a data processing method and a data processing apparatus, so that a concatenated FEC transmission solution has a strong burst resistance capability, and can be applied to a large quantity of transmission scenarios, particularly an actual coherent transmission scenario in which there is colored noise on a channel.
According to a first aspect, this application provides a data processing method. The method includes the following steps. First, inner-code encoding is separately performed on n first data streams to obtain n second data streams, where outer-code encoding is performed on all of the n first data streams, both the inner-code encoding and the outer-code encoding are FEC encoding, the n second data streams at least include n inner-code codewords, the n inner-code codewords are from the n second data streams, the n inner-code codewords include n/m codeword sets, each codeword set includes m inner-code codewords, each of the inner-code codewords includes N bits, the N bits include K information bits and P parity bits, n is an integer greater than 1, and n is divisible by m. Then, bit interleaving is separately performed on the n/m codeword sets to obtain n/m target bit sets, where each of the target bit sets includes m×N bits. Further, the m×N bits in each of the target bit sets are separately mapped to obtain m×N/L modulation symbols, to obtain a total of n×N/L modulation symbols, where every L bits are mapped to one modulation symbol, m is divisible by L, and the L bits mapped to the modulation symbol are from L inner-code codewords. If the L bits mapped to the modulation symbol are all from information bits in the inner-code codewords, any two of the L bits mapped to the modulation symbol are from two different locations in two different inner-code codewords.
In this embodiment, a concatenated-FEC transmission solution is used. That is, the outer-code encoding and the inner-code encoding are sequentially performed on the data streams. On this basis, this application designs a bit interleaving and mapping method, so that both bits in an outer-code codeword and bits in an inner-code codeword are discretely and evenly mapped to modulation symbols. In this way, the concatenated-FEC transmission solution has a strong burst resistance capability. Particularly, a burst error with a small length may be directly corrected through inner-code decoding. The concatenated-FEC transmission solution is widely applicable to transmission scenarios, particularly an actual coherent transmission scenario in which there is colored noise on a channel.
In some embodiments, N is divisible by L, the N bits in each inner-code codeword are mapped to N modulation symbols, the N bits in the inner-code codeword include L first bit subsets, bits in a same first bit subset are separately mapped to same bits in different modulation symbols, and bits in different first bit subsets are separately mapped to different bits in different modulation symbols. For example, one modulation symbol includes a bit b0, a bit b1, . . . , and a bit bL-1, and quantities of bits that are in the N bits in the inner-code codeword and that are mapped to the bit b0, the bit b1, . . . , and the bit bL-1 are all N/L. It should be understood that, probabilities that errors occur in the L bits in transmission are not necessarily equal. Bits in one inner-code codeword are more evenly mapped to modulation symbols, so that a burst resistance capability of the concatenated-FEC solution in actual transmission can be improved.
In some embodiments, that the bit interleaving is performed on the codeword set to obtain the target bit set includes: First location transformation is performed on the K information bits in each inner-code codeword in the codeword set to obtain a first bit set. Second location transformation is performed on bits at a same location in the first bit set to obtain the target bit set. For example, the codeword set is represented as a bit matrix. The first location transformation may be understood as performing location transformation on bits in each row, and the second location transformation may be understood as performing location transformation on bits in each column. This implementation provides a specific implementation of the bit interleaving, so that this solution has the strong anti-burst capability.
In some embodiments, that first location transformation is performed on the K information bits in each inner-code codeword in the codeword set includes: Left circular shift or right circular shift is performed on the K information bits in each inner-code codeword in the codeword set. This implementation provides a specific implementation of the first location transformation, and has a good practical effect.
In some embodiments, both the codeword set and the first bit set are represented as bit matrixes, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix includes m rows and N columns of bits, the one-dimensional array includes the m×N bits, and the bits at the same location in the first bit set are a total of m bits in one column in the bit matrix corresponding to the first bit set.
In some embodiments, the first location transformation satisfies a first condition, and the first condition includes:
In some embodiments, each same location in the first bit set includes m/L second bit subsets, each second bit subset includes L bits, and that second location transformation is performed on bits at a same location in the first bit set includes: Upward circular shift or downward circular shift is performed on the m/L second bit subsets at each same location in the first bit set. This implementation provides a specific implementation of the second location transformation, and has a good practical effect.
In some embodiments, the second location transformation satisfies a second condition, and the second condition includes:
In some embodiments, the second location transformation satisfies a third condition, and the third condition includes:
In some embodiments, the second location transformation satisfies a fourth condition, and the fourth condition includes:
In some embodiments, the codeword set is represented as a bit matrix, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix includes m rows and N columns of bits, and the one-dimensional array includes the m×N bits.
In some embodiments, the target bit set is the bit matrix, the bit interleaving satisfies a fifth condition, and the fifth condition includes:
In some embodiments, the target bit set is the one-dimensional array, the bit interleaving satisfies a sixth condition, and the sixth condition includes:
In some embodiments, the target bit set is the bit matrix, the bit interleaving satisfies a seventh condition, and the seventh condition includes:
In some embodiments, the target bit set is the one-dimensional array, the bit interleaving satisfies an eighth condition, and the eighth condition includes:
In some embodiments, that the m×N bits in each target bit set are mapped to obtain m×N/L modulation symbols includes: every L consecutive bits at a same location in each target bit set are mapped to one modulation symbol, to obtain the m×N/L modulation symbols.
In some embodiments, a modulation symbol stream includes the m×N/L modulation symbols obtained through the mapping, and m/L modulation symbols obtained through mapping of m bits at the same location in each target bit set are consecutive in the modulation symbol stream, where when the target bit set is represented as the bit matrix, the m bits at the same location in the target bit set are m bits in one column in the bit matrix; or when the target bit set is represented as the one-dimensional array, the m bits at the same location in the target bit set are m consecutive bits in the one-dimensional array.
In some embodiments, a modulation symbol stream includes the m×N/L modulation symbols obtained through the mapping, each target bit set is represented as the bit matrix including the m rows and the N columns of bits, m bits in one column in each target bit set are mapped to obtain m/L first modulation symbols, every T consecutive first modulation symbols in the m/L first modulation symbols are consecutive in the modulation symbol stream, m bits in another column in each target bit set are mapped to obtain m/L second modulation symbols, every T consecutive second modulation symbols in the m/L second modulation symbols are consecutive in the modulation symbol stream, the column is adjacent to the another column, the T consecutive first modulation symbols in the m/L first modulation symbols and the T consecutive second modulation symbols in the m/L second modulation symbols are consecutive in the modulation symbol stream, and m/L is divisible by T.
In some embodiments, alignment marker lock and lane de-skew processing are performed on all of the n first data streams; and when W×L bits in W consecutive modulation symbols are all information bits in an inner-code codeword, the W×L bits are from more than two outer-code codewords obtained through the outer-code encoding, where W≥2.
In some embodiments, each modulation symbol is a dual-polarization quadrature amplitude modulation (DP-16QAM) modulation symbol, and each modulation symbol includes eight bits; or each modulation symbol is a pulse amplitude modulation (PAM4) modulation symbol, and each modulation symbol includes two bits.
According to a second aspect, this application provides a data processing method. The method includes the following steps. First, inner-code encoding is separately performed on n first data streams to obtain n second data streams, where outer-code encoding is performed on all of the n first data streams, both the inner-code encoding and the outer-code encoding are FEC encoding, the n second data streams at least include n inner-code codewords, the n inner-code codewords are from the n second data streams, the n inner-code codewords include n/m codeword sets, each codeword set includes m inner-code codewords, each of the inner-code codewords includes N bits, the N bits include K information bits and P parity bits, n is an integer greater than 1, and n is divisible by m. Then, bit interleaving is separately performed on the n/m codeword sets to obtain n/m target bit sets, where each of the target bit sets includes m×N bits, and the bit interleaving includes performing location transformation on the K information bits in each inner-code codeword in the codeword set. Further, the m×N bits in each of the target bit sets are separately mapped to obtain m×N/L modulation symbols, to obtain a total of n×N/L modulation symbols, where every L bits are mapped to one modulation symbol, m is divisible by L, the L bits mapped to the modulation symbol are from Lr inner-code codewords, Lc bits in each of the Lr inner-code codewords are mapped to the modulation symbol, 2L bits mapped to two consecutive modulation symbols are from 2Lr inner-code codewords, L=Lr×Lc, and Lc>1.
In some embodiments, that location transformation is performed on the K information bits in each inner-code codeword in the codeword set includes: Left circular shift or right circular shift is performed on the K information bits in each inner-code codeword in the codeword set.
In some embodiments, the codeword set is represented as a bit matrix, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix includes m rows and N columns of bits, and the one-dimensional array includes the m×N bits.
In some embodiments, the location transformation satisfies a target condition, and the target condition includes:
In some embodiments, each target bit set includes the m rows and the N columns of bits, and a total of L bits in every Lr rows and Lc columns in the target bit set are mapped to one modulation symbol.
In some embodiments, a modulation symbol stream includes the m×N/L modulation symbols obtained through the mapping, m/Lr modulation symbols obtained through mapping of every Lc columns of bits in the target bit set are consecutive in the modulation symbol stream, and m×N/L modulation symbols obtained through mapping of every N columns of bits in the target bit set are consecutive in the modulation symbol stream.
In some embodiments, a modulation symbol stream includes the m×N/L modulation symbols obtained through the mapping, bits in Lc columns in each target bit set are mapped to obtain m/Lr first modulation symbols, every T consecutive first modulation symbols in the m/Lr first modulation symbols are consecutive in the modulation symbol stream, bits in Lc other columns in each target bit set are mapped to obtain m/Lr second modulation symbols, every T consecutive second modulation symbols in the m/Lr second modulation symbols are consecutive in the modulation symbol stream, the Lc columns are adjacent to the Lc other columns, the T consecutive first modulation symbols in the m/Lr first modulation symbols and the T consecutive second modulation symbols in the m/Lr second modulation symbols are consecutive in the modulation symbol stream, and m/Lr is divisible by T.
In some embodiments, each modulation symbol is a dual-polarization quadrature amplitude modulation (DP-16QAM) modulation symbol, and each modulation symbol includes eight bits; or each modulation symbol is a pulse amplitude modulation (PAM4) modulation symbol, and each modulation symbol includes two bits.
According to a third aspect, this application provides a data processing apparatus. The data processing apparatus includes an encoding module, a bit interleaving module, and a bit mapping module. The encoding module is configured to separately perform inner-code encoding on n first data streams to obtain n second data streams, where outer-code encoding is performed on all of the n first data streams, both the inner-code encoding and the outer-code encoding are forward error correction FEC encoding, the n second data streams at least include n inner-code codewords, the n inner-code codewords are from the n second data streams, the n inner-code codewords include n/m codeword sets, each codeword set includes m inner-code codewords, each of the inner-code codewords includes N bits, the N bits include K information bits and P parity bits, n is an integer greater than 1, and n is divisible by m. The bit interleaving module is configured to separately perform bit interleaving on the n/m codeword sets to obtain n/m target bit sets, where each of the target bit sets includes m×N bits. The bit mapping module is configured to map the m×N bits in each of the target bits set to obtain m×N/L modulation symbols, to obtain a total of n×N/L modulation symbols, where every L bits are mapped to one modulation symbol, m is divisible by L, and the L bits mapped to the modulation symbol are from L inner-code codewords. If the L bits mapped to the modulation symbol are all from information bits in the inner-code codewords, any two of the L bits mapped to the modulation symbol are from two different locations in two different inner-code codewords.
In some embodiments, N is divisible by L, the N bits in each inner-code codeword are mapped to N modulation symbols, the N bits in the inner-code codeword include L first bit subsets, bits in a same first bit subset are separately mapped to same bits in different modulation symbols, and bits in different first bit subsets are separately mapped to different bits in different modulation symbols.
In some embodiments, the bit mapping module is configured to: perform first location transformation on the K information bits in each inner-code codeword in the codeword set to obtain a first bit set; and perform second location transformation on bits at a same location in the first bit set to obtain the target bit set.
In some embodiments, the bit mapping module is configured to perform left circular shift or right circular shift on the K information bits in each inner-code codeword in the codeword set.
In some embodiments, both the codeword set and the first bit set are represented as bit matrixes, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix includes m rows and N columns of bits, the one-dimensional array includes the m×N bits, and the bits at the same location in the first bit set are a total of m bits in one column in the bit matrix corresponding to the first bit set.
In some embodiments, the first location transformation satisfies a first condition, and the first condition includes:
In some embodiments, each same location in the first bit set includes m/L second bit subsets, each second bit subset includes L bits, and the bit mapping module is configured to perform upward circular shift or downward circular shift on the m/L second bit subsets at each same location in the first bit set.
In some embodiments, the second location transformation satisfies a second condition, and the second condition includes:
In some embodiments, the second location transformation satisfies a third condition, and the third condition includes:
In some embodiments, the second location transformation satisfies a fourth condition, and the fourth condition includes:
In some embodiments, the codeword set is represented as a bit matrix, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix includes m rows and N columns of bits, and the one-dimensional array includes the m×N bits.
In some embodiments, the target bit set is the bit matrix, the bit interleaving satisfies a fifth condition, and the fifth condition includes:
In some embodiments, the target bit set is the one-dimensional array, the bit interleaving satisfies a sixth condition, and the sixth condition includes:
In some embodiments, the target bit set is the bit matrix, the bit interleaving satisfies a seventh condition, and the seventh condition includes:
In some embodiments, the target bit set is the one-dimensional array, the bit interleaving satisfies an eighth condition, and the eighth condition includes:
In some embodiments, the bit mapping module is configured to map every L consecutive bits at a same location in each target bit set to one modulation symbol, to obtain the m×N/L modulation symbols.
In some embodiments, a modulation symbol stream includes the m×N/L modulation symbols obtained through the mapping, and m/L modulation symbols obtained through mapping of m bits at the same location in each target bit set are consecutive in the modulation symbol stream, where when the target bit set is represented as the bit matrix, the m bits at the same location in the target bit set are m bits in one column in the bit matrix; or when the target bit set is represented as the one-dimensional array, the m bits at the same location in the target bit set are m consecutive bits in the one-dimensional array.
In some embodiments, a modulation symbol stream includes the m×N/L modulation symbols obtained through the mapping, each target bit set is represented as the bit matrix including the m rows and the N columns of bits, m bits in one column in each target bit set are mapped to obtain m/L first modulation symbols, every T consecutive first modulation symbols in the m/L first modulation symbols are consecutive in the modulation symbol stream, m bits in another column in each target bit set are mapped to obtain m/L second modulation symbols, every T consecutive second modulation symbols in the m/L second modulation symbols are consecutive in the modulation symbol stream, the column is adjacent to the another column, the T consecutive first modulation symbols in the m/L first modulation symbols and the T consecutive second modulation symbols in the m/L second modulation symbols are consecutive in the modulation symbol stream, and m/L is divisible by T.
In some embodiments, alignment marker lock and lane de-skew processing are performed on all of the n first data streams; and when W×L bits in W consecutive modulation symbols are all information bits in an inner-code codeword, the W×L bits are from more than two outer-code codewords obtained through the outer-code encoding, where W≥2.
In some embodiments, each modulation symbol is a DP-16QAM modulation symbol, and each modulation symbol includes eight bits; or each modulation symbol is a PAM4 modulation symbol, and each modulation symbol includes two bits.
According to a fourth aspect, this application provides a data processing apparatus. The data processing apparatus includes an encoding module, a bit interleaving module, and a bit mapping module. The encoding module is configured to separately perform inner-code encoding on n first data streams to obtain n second data streams, where outer-code encoding is performed on all of the n first data streams, both the inner-code encoding and the outer-code encoding are forward error correction FEC encoding, the n second data streams at least include n inner-code codewords, the n inner-code codewords are from the n second data streams, the n inner-code codewords include n/m codeword sets, each codeword set includes m inner-code codewords, each of the inner-code codewords includes N bits, the N bits include K information bits and P parity bits, n is an integer greater than 1, and n is divisible by m. The bit interleaving module is configured to separately perform bit interleaving on the n/m codeword sets to obtain n/m target bit sets, where each of the target bit sets includes m×N bits, and the bit interleaving includes performing location transformation on the K information bits in each inner-code codeword in the codeword set. The bit mapping module is configured to map the m×N bits in each of the target bit sets to obtain m×N/L modulation symbols, to obtain a total of n×N/L modulation symbols, where every L bits are mapped to one modulation symbol, m is divisible by L, the L bits mapped to the modulation symbol are from Lr inner-code codewords, Lc bits in each of the Lr inner-code codewords are mapped to the modulation symbol, 2L bits mapped to two consecutive modulation symbols are from 2Lr inner-code codewords, L=Lr×Lc, and Lc>1.
In some embodiments, the bit interleaving module is configured to perform left circular shift or right circular shift on the K information bits in each inner-code codeword in the codeword set.
In some embodiments, the codeword set is represented as a bit matrix, the target bit set is represented as a bit matrix or a one-dimensional array, the bit matrix includes m rows and N columns of bits, and the one-dimensional array includes the m×N bits.
In some embodiments, the location transformation satisfies a target condition, and the target condition includes:
In some embodiments, each target bit set includes the m rows and the N columns of bits, and a total of L bits in every Lr rows and Lc columns in the target bit set are mapped to one modulation symbol.
In some embodiments, a modulation symbol stream includes the m×N/L modulation symbols obtained through the mapping, m/Lr modulation symbols obtained through mapping of every Lc columns of bits in the target bit set are consecutive in the modulation symbol stream, and m×N/L modulation symbols obtained through mapping of every N columns of bits in the target bit set are consecutive in the modulation symbol stream.
In some embodiments, a modulation symbol stream includes the m×N/L modulation symbols obtained through the mapping, bits in Lc columns in each target bit set are mapped to obtain m/Lr first modulation symbols, every T consecutive first modulation symbols in the m/Lr first modulation symbols are consecutive in the modulation symbol stream, bits in Lc other columns in each target bit set are mapped to obtain m/Lr second modulation symbols, every T consecutive second modulation symbols in the m/Lr second modulation symbols are consecutive in the modulation symbol stream, the Lc columns are adjacent to the Lc other columns, the T consecutive first modulation symbols in the m/Lr first modulation symbols and the T consecutive second modulation symbols in the m/Lr second modulation symbols are consecutive in the modulation symbol stream, and m/Lr is divisible by T.
In some embodiments, each modulation symbol is a DP-16QAM modulation symbol, and each modulation symbol includes eight bits; or each modulation symbol is a PAM4 modulation symbol, and each modulation symbol includes two bits.
According to a fifth aspect, this application provides a data processing method. The method includes the following steps. First, interleaving and encoding processing is separately performed on every n1 first data streams in n0 first data streams to obtain one second data stream, to obtain a total of n2 second data streams, where n2=n0/n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. Then, every two bits in the n2 second data streams are separately mapped to one PAM4 symbol, to obtain a total of n2 PAM4 symbol data streams. In an embodiment, the interleaving and encoding processing includes the following steps. a0 first bit sets are obtained from each of the n1 first data streams to obtain a total of m=n1×a0 first bit sets, where outer-code encoding is performed on all of the n1 first data streams, each of the first bit sets includes K bits, and n1, a0, and K are all integers greater than 1. Inner-code encoding is separately performed on the m first bit sets to obtain m inner-code codewords, where both the inner-code encoding and the outer-code encoding are forward error correction FEC encoding, each of the inner-code codewords includes one first bit set and one parity bit set that participate in the inner-code encoding and that have a total of N bits, N=K+P, each parity bit set includes P bits, and P is an integer greater than or equal to 1. Circular shift is separately performed on the m inner-code codewords to obtain m third bit sets, where each third bit set includes the one parity bit set and one second bit set that is obtained by performing the circular shift on the first bit set. Two bits are obtained from each third bit set through round robin to obtain a fourth bit set, where the fourth bit set includes m×N bits, a total of m×K bits that are from m second bit sets and that are in the fourth bit set are consecutive, and a total of m×P bits that are from m parity bit sets and that are in the fourth bit set are consecutive. It should be understood that each of the second data streams includes a plurality of fourth bit sets, a total of m×N/2 PAM4 symbols are obtained through the mapping of each of the fourth bit sets, and m×2 bits mapped to m consecutive PAM4 symbols in the m×N/2 PAM4 symbols are from the m inner-code codewords.
In some embodiments, the outer-code encoding is performed on each of the first data streams at least 10 PAM4 symbols are obtained through the interleaving and encoding processing and the mapping of 20 consecutive bits in the first data stream, the 20 consecutive bits are from two outer-code symbols in one outer-code codeword, and any two of the at least 10 PAM4 symbols are separated by at least two PAM4 symbols in the PAM4 symbol data stream.
In some embodiments, quantities of bits by which the circular shift is performed on any two of the m first bit sets are different.
In some embodiments, both the m inner-code codewords and the m third bit sets are represented as bit matrixes, and the bit matrix includes m rows and N columns of bits.
In some embodiments, the second bit set is obtained by performing left circular shift on the first bit set by φi bits, the left circular shift satisfies a first condition, and the first condition includes:
In some embodiments, the second bit set is obtained by performing right circular shift on the first bit set by δi bits, the right circular shift satisfies a second condition, and the second condition includes:
In some embodiments, the m third bit sets and the fourth bit set satisfy a third condition, and the third condition includes:
In some embodiments, K=120, m=8, an ith second bit set is obtained by performing the left circular shift on an ith first bit set by φi bits, 0≤i<8, a value of φi satisfies any one of first value items {φ0, φ1, φ2, φ3, φ4, φ5, φ6, φ7}, and the first value items {φ0, φ1, φ2, φ3, φ4, φ5, φ6, φ7} include:
In some embodiments, K=120, m=8, an ith second bit set is obtained by performing the right circular shift on an ith first bit set by δi bits, 0≤i<8, a value of δi satisfies any one of second value items {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7}, and the second value items {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} include:
According to a sixth aspect, this application provides a data processing method. The method includes the following steps. First, interleaving and encoding processing is separately performed on every n1 first data streams in n0 first data streams to obtain one second data stream, to obtain a total of n2 second data streams, where n2=n0/n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. Then, every two bits in the n2 second data streams are separately mapped to one PAM4 symbol, to obtain a total of n2 PAM4 symbol data streams. In an embodiment, the interleaving and encoding processing includes the following steps. a0 first bit sets are obtained from each of the n1 first data streams to obtain a total of m=n1×a0 first bit sets, where outer-code encoding is performed on all of the n1 first data streams, each of the first bit sets includes K bits, and n1, a0, and K are all integers greater than 1. Circular shift is separately performed on the m first bit sets to obtain m second bit sets, and inner-code encoding is separately performed on the m first bit sets to obtain m parity bit sets, where both the inner-code encoding and the outer-code encoding are forward error correction FEC encoding, each of the second bit sets includes K bits, each of the parity bit sets includes P bits, and P is an integer greater than or equal to 1. Two bits are obtained from each second bit set through round robin to obtain a total of m×K consecutive bits, and two bits are obtained from each parity bit set through round robin to obtain a total of m×P consecutive bits, to obtain a third bit set including m×N bits, where N=K+P. It should be understood that each second data stream includes a plurality of third bit sets, each of the third bit sets includes the m×K bits in the second bit sets and the m×P bits in the parity bit sets, a total of m×K/2 PAM4 symbols are obtained through the mapping of the m×K bits that are from the second bit sets and that are in each of the third bit sets, a total of m×P/2 PAM4 symbols are obtained through the mapping of the m×P bits that are from the parity bit sets and that are in each of the third bit sets, and m×2 bits mapped to m consecutive PAM4 symbols in a total of m×N/2 PAM4 symbols are from the m second bit sets and/or the m parity bit sets.
In some embodiments, the outer-code encoding is performed on each of the first data streams, at least 10 PAM4 symbols are obtained through the interleaving and encoding processing and the mapping of 20 consecutive bits in the first data stream, the 20 consecutive bits are from two outer-code symbols in one outer-code codeword, and any two of the at least 10 PAM4 symbols are separated by at least two PAM4 symbols in the PAM4 symbol data stream.
In some embodiments, quantities of bits by which the circular shift is performed on any two of the m first bit sets are different.
In some embodiments, both the m first bit sets and the m second bit sets are represented as bit matrixes, and the bit matrix includes m rows and K columns of bits.
In some embodiments, the second bit set is obtained by performing left circular shift on the first bit set by φi bits, the left circular shift satisfies a first condition, and the first condition includes:
In some embodiments, the second bit set is obtained by performing right circular shift on the first bit set by δi bits, the right circular shift satisfies a second condition, and the second condition includes:
In some embodiments, K=120, m=8, an ith second bit set is obtained by performing the left circular shift on an ith first bit set by φi bits, 0≤i<8, a value of φi satisfies any one of first value items {φ0, φ1, φ2, φ3, φ4, φ5, φ6, φ7}, and the first value items {φ0, φ1, φ2, φ3, φ4, φ5, φ6, φ7} include:
In some embodiments, K=120, m=8, an ith second bit set is obtained by performing the right circular shift on an ith first bit set by δi bits, 0≤i<8, a value of δi satisfies any one of second value items {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7}, and the second value items {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} include:
According to a seventh aspect, this application provides a data processing method. The method includes the following steps. First, interleaving and encoding processing is separately performed on every n1 first data streams in n0 first data streams to obtain one second data stream, to obtain a total of n2 second data streams, where n2=n0/n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. Then, every two bits in the n2 second data streams are separately mapped to one PAM4 symbol, to obtain a total of n2 PAM4 symbol data streams. In an embodiment, the interleaving and encoding processing includes the following steps. a0 first bit sets are obtained from each of the n1 first data streams to obtain a total of m=n1×a0 first bit sets, where outer-code encoding is performed on all of the n1 first data streams, each of the first bit sets includes K bits, and n1, a0, and K are all integers greater than 1. Circular shift is separately performed on the m first bit sets to obtain m second bit sets, where each of the second bit sets includes K bits. Inner-code encoding is separately performed on the m second bit sets to obtain m inner-code codewords, where both the inner-code encoding and the outer-code encoding are forward error correction FEC encoding, each of the inner-code codewords includes one second bit set and one parity bit set that participate in the inner-code encoding and that have a total of N bits, N=K+P, each parity bit set includes P bits, and P is an integer greater than or equal to 1. Two bits are obtained from each inner-code codeword through round robin to obtain a third bit set, where the third bit set includes m×N bits, a total of m×K bits that are from the m second bit sets and that are in the third bit set are consecutive, and a total of m×P bits that are from m parity bit sets and that are in the third bit set are consecutive. It should be understood that each second data stream includes a plurality of third bit sets, a total of m×N/2 PAM4 symbols are obtained through the mapping of each of the third bit sets, and m×2 bits mapped to m consecutive PAM4 symbols in the m×N/2 PAM4 symbols are from the m inner-code codewords.
In some embodiments, the outer-code encoding is performed on each of the first data streams, at least 10 PAM4 symbols are obtained through the interleaving and encoding processing and the mapping of 20 consecutive bits in the first data stream, the 20 consecutive bits are from two outer-code symbols in one outer-code codeword, and any two of the at least 10 PAM4 symbols are separated by at least two PAM4 symbols in the PAM4 symbol data stream.
In some embodiments, quantities of bits by which the circular shift is performed on any two of the m first bit sets are different.
In some embodiments, both the m first bit sets and the m second bit sets are represented as bit matrixes, and the bit matrix includes m rows and K columns of bits.
In some embodiments, the second bit set is obtained by performing left circular shift on the first bit set by p bits, the left circular shift satisfies a first condition, and the first condition includes:
In some embodiments, the second bit set is obtained by performing right circular shift on the first bit set by δi bits, the right circular shift satisfies a second condition, and the second condition includes:
In some embodiments, the m inner-code codewords are represented as a bit matrix including m rows and N columns, the m inner-code codewords and the third bit set satisfy a third condition, and the third condition includes:
In some embodiments, K=120, m=8, an ith second bit set is obtained by performing the left circular shift on an ith first bit set by φi bits, 0≤i<8, a value of φi satisfies any one of first value items {φ0, φ1, φ2, φ3, φ4, φ5, φ6, φ7}, and the first value items {φ0, φ1, φ2, φ3, φ4, φ5, φ6, φ7} include:
In some embodiments, K=120, m=8, an ith second bit set is obtained by performing the right circular shift on an ith first bit set by δi bits, 0≤i<8, a value of δi satisfies any one of second value items {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7}, and the second value items {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} include:
According to an eighth aspect, this application provides a data processing method. The method includes the following steps. First, interleaving and encoding processing is separately performed on every n1 first data streams in n0 first data streams to obtain one second data stream, to obtain a total of n2 second data streams, where n2=n0/n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. Then, every two bits in the n2 second data streams are separately mapped to one PAM4 symbol, to obtain a total of n2 PAM4 symbol data streams. In an embodiment, the interleaving and encoding processing includes the following steps. a0 first bit sets are obtained from each of the n1 first data streams to obtain a total of m=n1×a0 first bit sets, where outer-code encoding is performed on all of the n1 first data streams, each of the first bit sets includes K bits, and n1, a0, and K are all integers greater than 1. Inner-code encoding is separately performed on the m first bit sets to obtain m inner-code codewords, where both the inner-code encoding and the outer-code encoding are forward error correction FEC encoding, each of the inner-code codewords includes one first bit set and one parity bit set that participate in the inner-code encoding and that have a total of N bits, N=K+P, each parity bit set includes P bits, and P is an integer greater than or equal to 1. The m inner-code codewords are separately interleaved to obtain one second bit set, where the second bit set includes m×N bits, a (└j/2┘×(m×2)+(i×2)+(j %2))th bit in the second bit set satisfies a first condition or a second condition, 0≤i<m, and 0≤j<N.
The first condition includes:
The second condition includes:
It should be understood that each second data stream includes a plurality of second bit sets, a total of m×N/2 PAM4 symbols are obtained through the mapping of each of the second bit sets, and m×2 bits mapped to m consecutive PAM4 symbols in the m×N/2 PAM4 symbols are from the m inner-code codewords.
In some embodiments, K=120, m=8, a value of φi satisfies any one of first value items {φ0, φ1, φ2, φ3, φ4, φ5, φ6, φ7}, and the first value items {φ0, φ1, φ2, φ3, φ4, φ5 φ6, φ7} include:
According to a ninth aspect, this application provides a data processing apparatus. The data processing apparatus includes an interleaving and encoding module and a bit mapping module. The interleaving and encoding module is configured to separately perform interleaving and encoding processing on every n1 first data streams in n0 first data streams to obtain one second data stream, to obtain a total of n2 second data streams, where n2=n0/n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. The bit mapping module is configured to separately map every two bits in the n2 second data streams to one PAM4 symbol, to obtain a total of n2 PAM4 symbol data streams. The interleaving and encoding module is configured to: obtain a0 first bit sets from each of the n1 first data streams to obtain a total of m=n1×a0 first bit sets, where outer-code encoding is performed on all of the n1 first data streams, each of the first bit sets includes K bits, and n1, a0, and K are all integers greater than 1; separately perform inner-code encoding on the m first bit sets to obtain m inner-code codewords, where both the inner-code encoding and the outer-code encoding are forward error correction FEC encoding, each of the inner-code codewords includes one first bit set and one parity bit set that participate in the inner-code encoding and that have a total of N bits, N=K+P, each parity bit set includes P bits, and P is an integer greater than or equal to 1; separately perform circular shift on the m inner-code codewords to obtain m third bit sets, where each of the third bit sets includes the one parity bit set and one second bit set that is obtained by performing the circular shift on the first bit set; and obtain a fourth bit set through 2-bit round robin in each of the third bit sets, where the fourth bit set includes m×N bits, a total of m×K bits that are from m second bit sets and that are in the fourth bit set are consecutive, and a total of m×P bits that are from m parity bit sets and that are in the fourth bit set are consecutive. It should be understood that each of the second data streams includes a plurality of fourth bit sets, a total of m×N/2 PAM4 symbols are obtained through the mapping of each of the fourth bit sets, and m×2 bits mapped to m consecutive PAM4 symbols in the m×N/2 PAM4 symbols are from the m inner-code codewords.
In some embodiments, the outer-code encoding is performed on each of the first data streams, at least 10 PAM4 symbols are obtained through the interleaving and encoding processing and the mapping of 20 consecutive bits in the first data stream, the 20 consecutive bits are from two outer-code symbols in one outer-code codeword, and any two of the at least 10 PAM4 symbols are separated by at least two PAM4 symbols in the PAM4 symbol data stream.
In some embodiments, quantities of bits by which the circular shift is performed on any two of the m first bit sets are different.
In some embodiments, both the m inner-code codewords and the m third bit sets are represented as bit matrixes, and the bit matrix includes m rows and N columns of bits.
In some embodiments, the second bit set is obtained by performing left circular shift on the first bit set by φi bits, the left circular shift satisfies a first condition, and the first condition includes:
In some embodiments, the second bit set is obtained by performing right circular shift on the first bit set by δi bits, the right circular shift satisfies a second condition, and the second condition includes:
In some embodiments, the m third bit sets and the fourth bit set satisfy a third condition, and the third condition includes:
In some embodiments, K=120, m=8, an ith second bit set is obtained by performing the left circular shift on an ith first bit set by φi bits, 0≤i<8, a value of φi satisfies any one of first value items {φ0, φ1, φ2, φ3, φ4, φ5 φ6, φ7}, and the first value items {φ0, φ1, φ2, φ3, φ4, φ5, φ6, φ7} include:
In some embodiments, K=120, m=8, an ith second bit set is obtained by performing the right circular shift on an ith first bit set by δi bits, 0≤i<8, a value of δi satisfies any one of second value items {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7}, and the second value items {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} include:
According to a tenth aspect, this application provides a data processing apparatus. The data processing apparatus includes an interleaving and encoding module and a bit mapping module. The interleaving and encoding module is configured to separately perform interleaving and encoding processing on every n1 first data streams in n0 first data streams to obtain one second data stream, to obtain a total of n2 second data streams, where n2=n0/n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. The bit mapping module is configured to separately map every two bits in the n2 second data streams to one PAM4 symbol, to obtain a total of n2 PAM4 symbol data streams. The interleaving and encoding module is configured to: obtain a0 first bit sets from each of the n1 first data streams to obtain a total of m=n1×a0 first bit sets, where outer-code encoding is performed on all of the n1 first data streams, each of the first bit sets includes K bits, and n1, a0, and K are all integers greater than 1; separately perform circular shift on the m first bit sets to obtain m second bit sets, and separately perform inner-code encoding on the m first bit sets to obtain m parity bit sets, where both the inner-code encoding and the outer-code encoding are forward error correction FEC encoding, each of the second bit sets includes K bits, each of the parity bit sets includes P bits, and P is an integer greater than or equal to 1; and obtain, through round robin, two bits from each second bit set to obtain a total of m×K consecutive bits, and obtain, through round robin, two bits from each parity bit set to obtain a total of m×P consecutive bits, to obtain a third bit set including m×N bits, where N=K+P. It should be understood that each second data stream includes a plurality of third bit sets, each of the third bit sets includes the m×K bits in the second bit sets and the m×P bits in the parity bit sets, a total of m×K/2 PAM4 symbols are obtained through the mapping of the m×K bits that are from the second bit sets and that are in each of the third bit sets, a total of m×P/2 PAM4 symbols are obtained through the mapping of the m×P bits that are from the parity bit sets and that are in each of the third bit sets, and m×2 bits mapped to m consecutive PAM4 symbols in a total of m×N/2 PAM4 symbols are from the m second bit sets and/or the m parity bit sets.
In some embodiments, the outer-code encoding is performed on each of the first data streams, at least 10 PAM4 symbols are obtained through the interleaving and encoding processing and the mapping of 20 consecutive bits in the first data stream, the 20 consecutive bits are from two outer-code symbols in one outer-code codeword, and any two of the at least 10 PAM4 symbols are separated by at least two PAM4 symbols in the PAM4 symbol data stream.
In some embodiments, quantities of bits by which the circular shift is performed on any two of the m first bit sets are different.
In some embodiments, both the m first bit sets and the m second bit sets are represented as bit matrixes, and the bit matrix includes m rows and K columns of bits.
In some embodiments, the second bit set is obtained by performing left circular shift on the first bit set by φi bits, the left circular shift satisfies a first condition, and the first condition includes:
In some embodiments, the second bit set is obtained by performing right circular shift on the first bit set by δi bits, the right circular shift satisfies a second condition, and the second condition includes:
In some embodiments, K=120, m=8, an ith second bit set is obtained by performing the left circular shift on an ith first bit set by φi bits, 0≤i<8, a value of φi satisfies any one of first value items {φ0, φ1, φ2, φ3, φ4, φ5 φ6, φ7}, and the first value items {φ0, φ1, φ2, φ3, φ4, φ5, φ6, φ7} include:
In some embodiments, K=120, m=8, an ith second bit set is obtained by performing the right circular shift on an ith first bit set by δi bits, 0≤i<8, a value of δi satisfies any one of second value items {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7}, and the second value items {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} include:
According to an eleventh aspect, this application provides a data processing apparatus. The data processing apparatus includes an interleaving and encoding module and a bit mapping module. The interleaving and encoding module is configured to separately perform interleaving and encoding processing on every n1 first data streams in n0 first data streams to obtain one second data stream, to obtain a total of n2 second data streams, where n2=n0/n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. The bit mapping module is configured to separately map every two bits in the n2 second data streams to one PAM4 symbol, to obtain a total of n2 PAM4 symbol data streams. The interleaving and encoding module is configured to: obtain a0 first bit sets from each of the n1 first data streams to obtain a total of m=n1×a0 first bit sets, where outer-code encoding is performed on all of the n1 first data streams, each of the first bit sets includes K bits, and n1, a0, and K are all integers greater than 1; separately perform circular shift on the m first bit sets to obtain m second bit sets, where each of the second bit sets includes K bits; separately perform inner-code encoding on the m second bit sets to obtain m inner-code codewords, where both the inner-code encoding and the outer-code encoding are forward error correction FEC encoding, each of the inner-code codewords includes one second bit set and one parity bit set that participate in the inner-code encoding and that have a total of N bits, N=K+P, each parity bit set includes P bits, and P is an integer greater than or equal to 1; and obtain, through round robin, two bits from each inner-code codeword to obtain a third bit set, where the third bit set includes m×N bits, a total of m×K bits that are from the m second bit sets and that are in the third bit set are consecutive, and a total of m×P bits that are from m parity bit sets and that are in the third bit set are consecutive. It should be understood that each second data stream includes a plurality of third bit sets, a total of m×N/2 PAM4 symbols are obtained through the mapping of each of the third bit sets, and m×2 bits mapped to m consecutive PAM4 symbols in the m×N/2 PAM4 symbols are from the m inner-code codewords.
In some embodiments, the outer-code encoding is performed on each of the first data streams, at least 10 PAM4 symbols are obtained through the interleaving and encoding processing and the mapping of 20 consecutive bits in the first data stream, the 20 consecutive bits are from two outer-code symbols in one outer-code codeword, and any two of the at least 10 PAM4 symbols are separated by at least two PAM4 symbols in the PAM4 symbol data stream.
In some embodiments, quantities of bits by which the circular shift is performed on any two of the m first bit sets are different.
In some embodiments, both the m first bit sets and the m second bit sets are represented as bit matrixes, and the bit matrix includes m rows and K columns of bits.
In some embodiments, the second bit set is obtained by performing left circular shift on the first bit set by φi bits, the left circular shift satisfies a first condition, and the first condition includes:
In some embodiments, the second bit set is obtained by performing right circular shift on the first bit set by δi bits, the right circular shift satisfies a second condition, and the second condition includes:
In some embodiments, the m inner-code codewords are represented as a bit matrix including m rows and N columns, the m inner-code codewords and the third bit set satisfy a third condition, and the third condition includes:
In some embodiments, K=120, m=8, an ith second bit set is obtained by performing the left circular shift on an ith first bit set by φi bits, 0≤i<8, a value of φi satisfies any one of first value items {φ0, φ1, φ2, φ3, φ4, φ5, φ6, φ7}, and the first value items {φ0, φ1, φ2, φ3, φ4, φ5, φ6, φ7} include:
In some embodiments, K=120, m=8, an ith second bit set is obtained by performing the right circular shift on an ith first bit set by δi bits, 0≤i<8, a value of δi satisfies any one of second value items {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7}, and the second value items {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} include:
According to a twelfth aspect, this application provides a data processing apparatus. The data processing apparatus includes an interleaving and encoding module and a bit mapping module. The interleaving and encoding module is configured to separately perform interleaving and encoding processing on every n1 first data streams in n0 first data streams to obtain one second data stream, to obtain a total of n2 second data streams, where n2=n0/n1, n0 is an integer greater than 1, and n1 is an integer greater than 0. The bit mapping module is configured to separately map every two bits in the n2 second data streams to one PAM4 symbol, to obtain a total of n2 PAM4 symbol data streams. The interleaving and encoding module is configured to: obtain a0 first bit sets from each of the n1 first data streams to obtain a total of m=n1×a0 first bit sets, where outer-code encoding is performed on all of the n1 first data streams, each of the first bit sets includes K bits, and n1, a0, and K are all integers greater than 1; separately perform inner-code encoding on the m first bit sets to obtain m inner-code codewords, where both the inner-code encoding and the outer-code encoding are forward error correction FEC encoding, each of the inner-code codewords includes one first bit set and one parity bit set that participate in the inner-code encoding and that have a total of N bits, N=K+P, each parity bit set includes P bits, and P is an integer greater than or equal to 1; and separately interleave the m inner-code codewords to obtain one second bit set, where the second bit set includes m×N bits, a ([j/2]×(m×2)+(i×2)+(j %2))th bit in the second bit set satisfies a first condition or a second condition, 0≤i<m, and 0≤j<N.
The first condition includes:
The second condition includes:
It should be understood that each second data stream includes a plurality of second bit sets, a total of m×N/2 PAM4 symbols are obtained through the mapping of each of the second bit sets, and m×2 bits mapped to m consecutive PAM4 symbols in the m×N/2 PAM4 symbols are from the m inner-code codewords.
In some embodiments, K=120, m=8, a value of φi satisfies any one of first value items {φ0, φ1, φ2, φ3, φ4, φ5, φ6, φ7}, and the first value items {φ0, φ1, φ2, φ3, φ4, φ5, φ6, φ7} include:
In embodiments of this application, the concatenated-FEC transmission solution is used. That is, the outer-code encoding and the inner-code encoding are sequentially performed on the data streams. On this basis, this application designs the bit interleaving and mapping method, so that both the bits in the outer-code codeword and the bits in the inner-code codeword are discretely and evenly mapped to the modulation symbols. In this way, the concatenated-FEC transmission solution has the strong burst resistance capability. Particularly, the burst error with the small length may be directly corrected through the inner-code decoding. The concatenated-FEC transmission solution is widely applicable to transmission scenarios, particularly the actual coherent transmission scenario in which there is colored noise on a channel.
Embodiments of this application provide a data processing method and a data processing apparatus, so that a concatenated-FEC transmission solution has a strong burst resistance capability, can be applied to a large quantity of transmission scenarios, particularly an actual coherent transmission scenario in which there is colored noise on a channel. It should be noted that in the specification, claims, and the foregoing accompanying drawings of this application, the terms “first” and “second” are intended to distinguish between similar objects but do not limit a specific order or sequence. It should be understood that the foregoing terms may be interchanged in proper cases, so that embodiments described in this application can be implemented in an order other than the content described in this application. In addition, the terms “include”, “have”, and any variant thereof are intended to cover a non-exclusive inclusion. For example, processes, methods, systems, products, or devices that include a series of steps or units are not limited to the steps or the units that are clearly listed, and may include other steps and units that are not clearly listed or that are inherent to the processes, methods, products, or devices.
It should be understood that “inner” in an inner code and “outer” in an outer code are distinguished based only on a distance between an execution body that performs an operation on data and the channel transmission medium 03. An execution body that performs an operation on the inner code is closer to the channel transmission medium, and an execution body that performs an operation on the outer code is farther away from the channel transmission medium. In embodiments of this application, after being sent from the transmitter device 01, the data is transmitted to the channel transmission medium 03 via the transmitter processing module 02, and then is transmitted from the channel transmission medium 03 to the receiver device 05 via the receiver processing module 04. The data obtained through the encoding performed by the transmitter device 01 is farther away from the channel transmission medium 03 than the data obtained through the encoding performed by the transmitter processing module 02, and data obtained through the decoding performed by the receiver device 05 is farther away from the channel transmission medium 03 than the data obtained through the decoding performed by the receiver processing module 04. Therefore, the data obtained through the encoding performed by the transmitter device 01 is referred to as the outer-code encoded data, the data obtained through the encoding performed by the transmitter processing module 02 is referred to as the inner-code encoded data, the data obtained through the decoding performed by the receiver device 05 is referred to as outer-code decoded data, and the data obtained through the decoding performed by the receiver processing module 04 is referred to as the inner-code decoded data. In an embodiment, both the inner-code encoding and the outer-code encoding use an FEC encoding manner, to form a concatenated-FEC transmission solution. For example, the transmitter device 01 may perform the outer-code encoding by using an RS code, and the transmitter processing module 02 may perform the inner-code encoding by using a Hamming code. For another example, the transmitter device 01 may perform the outer-code encoding by using an RS code, and the transmitter processing module 02 may perform the inner-code encoding by using a Bose-Chaudhuri-Hocquenghem (BCH) code.
It should be noted that the foregoing content is example description of an application scenario of the data processing method provided in embodiments of this application, and does not constitute any limitation on the application scenario of the data processing method. A person of ordinary skill in the art may learn that, as a service requirement changes, the application scenario of the data processing method may be adjusted based on an application requirement. Application scenarios are not enumerated in embodiments of this application.
301: Separately perform inner-code encoding on n first data streams to obtain n second data streams.
In this embodiment, a physical medium attachment (PMA) sublayer of the transmitter processing module performs first data processing on data from a plurality of synchronous client lanes to obtain the n first data streams, where n is an integer greater than 1. The first data processing may include alignment marker lock (or alignment lock), lane de-skew processing, lane reorder processing, concatenated interleaving processing, or the like. The foregoing n first data streams are all outer-code encoded data streams. For example, an RS code may be used for the outer-code encoding, and the n outer-code encoded data streams may include a plurality of RS codewords. In actual application, another encoding scheme may alternatively be for performing the outer-code encoding. For ease of description, in the following descriptions, the RS codeword is uniformly for representing a codeword generated through the outer-code encoding. It should be noted that, in this application, a code length of an outer code is measured in outer-code symbols, where the symbol may include one or more bits. For example, the outer code is a used KP4 RS(544,514) code, a code length is 544 symbols, and one outer-code symbol includes 10 bits.
An inner-code encoder performs the inner-code encoding on every K bits in each first data stream, and then adds P parity bits to obtain an inner-code codeword including a total of N bits. Herein, the K bits may be referred to as an inner-code information sequence, and K+P=N. Generally, K is a multiple of 10, and the K bits correspond to K/10 outer-code symbols. In some scenarios, the K/10 outer-code symbols corresponding to the K information bits are from K/10 different outer-code codewords.
It should be understood that each second data stream obtained through the inner-code encoding includes at least one inner-code codeword. One inner-code codeword is separately obtained from each second data stream to obtain a total of n inner-code codewords, where the n inner-code codewords include n/m codeword sets, namely, a codeword set 0, a codeword set 1, . . . , and a codeword set n/m−1. Each codeword set includes m inner-code codewords. A codeword set h (0≤h<n/m) includes a codeword m×h, a codeword m×h+1, . . . , and a codeword m×h+m−1. n is divisible by m.
It should be noted that the foregoing codeword set is merely a concept introduced for ease of description. In actual application, the second data stream is an integrate part without division. Each codeword set may be considered as a plurality of bits in the second data stream.
302: Separately perform bit interleaving on the n/m codeword sets to obtain n/m target bit sets.
It should be understood that both a quantity of bits in the codeword set and a quantity of bits in the target bit set are m×N. This step is performing location transformation on the bits in the codeword set to obtain the target bit set. In an example, the target bit set may be represented as a bit matrix with m rows and N columns. In another example, the target bit set may alternatively be represented as a one-dimensional array including m×N bits. It should be noted that, in an example in which the codeword set is represented as a bit matrix, the bit interleaving provided in this application includes but is not limited to performing location transformation (row transformation for short) on bits in each row in the codeword set, performing the location transformation (column transformation for short) on bits in each column in the codeword set, and performing the location transformation (row-column transformation for short) on bits in each row and each column in the codeword set. The row-column transformation includes first the row transformation and then the column transformation, first the column transformation and then the row transformation, and simultaneous row transformation and column transformation. The following describes the bit interleaving in detail with reference to several specific implementations.
For ease of description, m×N codeword bits in the codeword set h (0≤h<n/m) are represented by using a first matrix H1 with m rows and N columns, where each row in the first matrix H1 includes N bits in one inner-code codeword. A bit in an ith (0≤i<m) row and a jth (0≤j<N) column in the first matrix H1 is denoted as H1[i][j]. More specifically, H1[i][j] represents a jth bit in an ith inner-code codeword in the codeword set h, and also represents a jth in a codeword m×h+i from a second data stream m×h+i. It should be noted that the n/m codeword sets correspond to n/m first matrixes H1. That is, the codeword set h (0≤h<n/m) corresponds to an hth first matrix H1. For ease of description, the following briefly describes the hth first matrix H1 as the first matrix H1.
A total of K bits in the 0th column to a (K−1)th column in each row in the first matrix H1 correspond to information bits whose length is K in the one inner-code codeword; and a total of m×K bits in the 0th column to the (K−1)th column in the first matrix H1 correspond to m×K information bits in m inner-code codewords. Similarly, a total of P bits in a Kth column to an (N−1)th column in each row in the first matrix H1 correspond to a parity bit whose length is P in the one inner-code codeword; and a total of m×P bits in the Kth column to the (N−1)th column in the first matrix H1 correspond to m×P parity bits in the m inner-code codewords.
The following first describes specific manners in which the row transformation and the column transformation are separately implemented.
Implementation 1 of the bit interleaving: the row transformation (which may also be referred to as first location transformation).
In an embodiment, the first location transformation is performed on K information bits in each inner-code codeword in the codeword set. Alternatively, this may be described as “the first location transformation is performed on K information bits in each row in the first matrix H1”. In an embodiment, the first location transformation is performing left circular shift or right circular shift on the K information bits in each row in the first matrix H1. The left circular shift is used as an example. The left circular shift is performed on K information bits in the ith (0≤i<m) row in the first matrix H1 by i×Δ bits, where the non-zero integer Δ is a row offset constraint factor. It should be noted that the left circular shift is performed on the K information bits (u0, u1, u2, u3, . . . , uK-2, uK-1) by the i×Δ bits to obtain K bits (u(i×Δ)% K, u(1+i×Δ)% K, U(2+i×Δ)% K, . . . , u(K−2+i×Δ)% K, u(K-1+i×Δ)% K) obtained through the shift.
More specifically, circular shift manners used for the first location transformation are described by using the following formulas.
In an example, the left circular shift is used for the first location transformation, and the first location transformation satisfies a formula (1.1):
It should be noted that performing the left circular shift on the K information bits by i×Δ bits is equivalent to performing the left circular shift on the K information bits by (i×Δ)% K bits. That is, the foregoing formula (1.1) may be written as the following formula (1.2):
The left circular shift is performed on the K information bits in the ith row in the first matrix H1 by i×Δ bits to obtain K bits in the 0th column to a (K−1)th column in an ith row in a second matrix H2. Equivalently, the right circular shift is performed on K information bits in the 0th column to the (K−1)th column in the ith row in the first matrix H1 by i×(K−Δ) bits to obtain the K bits in the 0th column to the (K−1)th column in the ith row in the second matrix H2. As shown in the example in (a) in
In another example, the right circular shift is used for the first location transformation, and the first location transformation satisfies a formula (1.3):
In some specific formula expressions, for ease of description, the formula (1.3) is briefly expressed as a formula (1.4):
It should be further noted that performing the circular shift on the K information bits in the 0th column to the (K−1)th column in each row in the first matrix H1 is performing an operation only on the information bits in the first matrix H1. Therefore, it may also be described as performing the circular shift on the K information bits in the 0th column to the (K−1)th column in each row in the first matrix H1 to obtain a fourth matrix H4 with m rows and K columns. In an embodiment, the left circular shift is used for the first location transformation, and the first location transformation satisfies a formula (3.1):
Meanings of the parameters in the formula (3.1) are similar to those in the formula (1.1). Details are not described herein again.
Implementation 2 of the bit interleaving: the column transformation (which may also be referred to as second location transformation).
It should be noted that the column transformation described in this implementation is described based on performing the row transformation on the first matrix H1 to obtain the second matrix H2. In some scenarios, the column transformation may alternatively be first performed on the first matrix H1 in this implementation. Details are not described herein again.
In an embodiment, the second location transformation is performed on bits at a same location in the second matrix H2 to obtain a third matrix H3. It should be understood that the bits at the same location in the second matrix H2 may be understood as m bits in a same column in the second matrix H2. In other words, the location transformation is performed on the m bits in the same column. Alternatively, the bits at the same location in the second matrix H2 may be understood as G×m bits in G same columns in the second matrix H2, where G is an integer greater than 1. In other words, up-down location transformation is performed per G bits in the G same columns in each row. For ease of description, the following provides descriptions by using an example in which the same location is the same column.
In an embodiment, the second matrix H2 is divided into m/L first submatrixes, and each first submatrix includes L rows and N columns. Upward circular shift or downward circular shift is performed on L bits in each column in each first submatrix, to implement location transformation of bits in each first submatrix. The upward circular shift is used as an example. The upward circular shift is performed on L bits in a jth (0≤j<N) column in each first submatrix by θ×(j % L) bits, where the non-zero integer 0 is a column offset constraint factor. Herein, performing the upward circular shift on the L bits in the jth (0≤j<N) column in each first submatrix by θ×(j % L) bits is alternatively equivalent to performing the upward circular shift by θ×j bits. This can be known by a person of ordinary skill in the art. Details are not described herein again. The upward circular shift is performed on L bits
by θ×(j % L) bits to obtain L bits
obtained through the shift.
in the jth column by two bits to obtain eight bits
obtained through the shift. As shown in an example in (b) in
More specifically, circular shift manners used for the second location transformation are described by using the following formulas.
In an example, the upward circular shift is used for the second location transformation, and the second location transformation satisfies a formula (2.1):
It should be understood that the foregoing formula (2.1) may alternatively be written as: H3[i][j]=H2[(i+θ×j) % L+└i/L┘×L][j].
Performing the upward circular shift on the L bits in the jth column in the first submatrix in the second matrix H2 by θ×(j % L) bits is equivalent to performing the downward circular shift by (L−θ)×(j % L) bits. As shown in the example in (a) in
In another example, the downward circular shift is used for the second location transformation, and the second location transformation satisfies a formula (2.2):
In some specific formula expressions, for ease of description, the formula (2.2) is briefly expressed as a formula (2.3):
In another embodiment, different from the second location transformation for which a manner of the foregoing upward circular shift or downward circular shift is used, the second location transformation satisfies a formula (2.4):
It should be noted that, when the integer L is a power of 2, the second location transformation may further satisfy a formula (2.5):
It should be further noted that the foregoing first location transformation is location transformation performed on only the information bits, but the second location transformation is location transformation performed on both the information bits and parity bits. The foregoing descriptions are for only the fourth matrix H4 with only the m rows and the K columns of information bits, the second location transformation is further expressed in the following another manner.
In an embodiment, the fourth matrix H4 with the m rows and the K columns and the Kth column to the (N−1)th column in the first matrix H1, that is, a total of m rows and N columns, are divided into a plurality of second submatrixes, where each second submatrix includes L rows and N columns. The location transformation is performed on L bits in each column in each second submatrix to obtain the third matrix H3 with m rows and N columns.
In a specific implementation, the upward circular shift is performed on L bits in a jth (0≤j<N) column in each second submatrix by θ×(j % L) bits. More specifically, for 0≤i<m, the second location transformation may further satisfy a formula (4.1):
The integer θ is the column offset constraint factor. The formula (4.1) may alternatively be briefly expressed as:
In another specific implementation, for 0≤i<m, the second location transformation may further satisfy a formula (4.2):
When L is the power of 2, for 0≤i<m, the second location transformation may further satisfy a formula (4.3):
It should be understood that the foregoing describes the specific manners in which the row transformation and the column transformation are separately implemented. That is, the bit interleaving includes two steps of operations. In some scenarios, the row transformation and the column transformation may alternatively be implemented using one step of operation. The following describes this implementation in detail.
Implementation 3 of the bit interleaving: The row transformation and the column transformation are implemented using one step of operation.
In a specific implementation, for 0≤i<m, the bit interleaving satisfies a formula (5):
The formula (5) may alternatively be briefly expressed as:
In another specific implementation, for 0≤i<m, the bit interleaving satisfies a formula (6):
When L is a power of 2, for 0≤i<m, the bit interleaving satisfies a formula (7):
It should be noted that when the integer Δ is a multiple of 10, and one outer-code symbol in the outer-code codeword includes 10 bits, the K information bits may be considered as the K/10 symbols, where each symbol corresponds to 10 information bits. Performing circular shift on K information bits in the ith (0≤i<m) row in the first matrix H1 by i×Δ bits may be considered as performing the circular shift on K/10 symbols in the ith (0≤i<m) row in the first matrix H1 by
symbols. A specific implementation thereof is known to a person of ordinary skill in the art. Details are not described herein again.
When specific values of parameters such as Δ, θ, m, and L are given, an interleaving correspondence for performing the bit interleaving on the first matrix H1 to obtain the third matrix H3 may be described by using a table. A specific implementation thereof is known to a person of ordinary skill in the art. Details are not described herein again.
When specific values of parameters such as Δ, θ, m, and L are given, the foregoing formula (5) or (6) may be simply transformed into another formula. For example, when m=L, the formula (5) may be simplified as follows:
The formula (6) may be transformed as follows:
It should be understood that a specific implementation of other simple transformation is known to a person of ordinary skill in the art. Details are not described herein again.
It should be noted that the foregoing codeword set, bit matrix, and submatrix are merely concepts introduced for ease of description. In actual application, the data stream is an integrate part without division. Each codeword set, bit matrix, and submatrix may be considered as one or more bits in the data stream. In addition, in actual application, the first matrix, the second matrix, the third matrix, the fourth matrix, and the like may alternatively not be presented in a form of a matrix. For example, the first matrix H1 is presented as a first bit set, the first bit set includes m first bit subsets, and each first bit subset includes bit elements in one row and N columns in the corresponding first matrix H1.
It should be noted that, in the foregoing implementations, the target bit set obtained through the bit interleaving of the m codewords is represented by using the third matrix H3 with the m rows and the N columns. In addition, the target bit set may alternatively be represented by using the one-dimensional array (array) that is denoted as an array A and that includes the m×N bits. A tth (0≤t<m×N) bit in the array A is denoted as A[t]. Performing the bit interleaving on the first matrix H1 to obtain the array A including the m×N bit elements may alternatively be represented in the following manner.
In an example, for 0≤i<m, the bit interleaving satisfies a formula (8):
In another example, for 0≤i<m, the bit interleaving satisfies a formula (9):
When L is the power of 2, for 0≤i<m, the bit interleaving satisfies a formula (10):
303: Separately map m×N bits in each of the target bit sets to obtain m×N/L modulation symbols, to obtain a total of n×N/L modulation symbols.
In this embodiment, m is divisible by L. Every L bits in the target bit set are mapped to one modulation symbol. That is, the modulation symbol includes the L bits. L bits in each modulation symbol are from L inner-code codewords. In addition, if the L bits mapped to the modulation symbol are all from information bits in the inner-code codewords, any two of the L bits mapped to the modulation symbol are from two different locations in two different inner-code codewords.
It should be understood that the n×N/L modulation symbols obtained through the mapping of all target bit sets may be represented as one modulation symbol stream. Alternatively, the m×N/L modulation symbols obtained through the mapping of each target bit set may be represented as one modulation symbol stream, to obtain a total of n/m modulation symbol streams. Then, the modulation symbol stream may further undergo other data processing, and then be sent to a channel transmission medium for transmission. The other data processing may include polarization distribution (polarization distribution), DSP framing (framing) processing, or the like.
In an embodiment, when N is divisible by L, the N bits in each inner-code codeword are mapped to N modulation symbols, the N bits in the inner-code codeword include L first bit subsets, bits in a same first bit subset are separately mapped to same bits in different modulation symbols, and bits in different first bit subsets are separately mapped to different bits in different modulation symbols. For example, one modulation symbol includes a bit b0, a bit b1, . . . , and a bit bL-1, and quantities of bits that are in the N bits in the inner-code codeword and that are mapped to the bit b0, the bit b1, . . . , and the bit bL-1 are all N/L. It should be understood that, probabilities that errors occur in the L bits in transmission are not necessarily equal. Bits in one inner-code codeword are more evenly mapped to modulation symbols, so that a burst resistance capability of a concatenated-FEC solution in actual transmission can be improved.
It should be noted that, in some scenarios, alignment marker lock and lane de-skew processing are performed on all of the n first data streams; and when W×L bits in W consecutive modulation symbols are all information bits in an inner-code codeword, the W×L bits are from more than two outer-code codewords obtained through the outer-code encoding, where W≥2.
In some implementations applied to coherent optical communication, the foregoing modulation scheme is dual-polarization quadrature amplitude modulation (Dual-polarization quadrature amplitude modulation, DP-QAM), for example, DP-QPSK or DP-16QAM. For DP-QPSK modulation, one DP-QPSK modulation symbol corresponds to L=4 bits. For DP-16QAM modulation, one DP-16QAM modulation symbol corresponds to L=8 bits.
In some implementations applied to direct-detection optical communication, the foregoing modulation scheme is pulse amplitude modulation (Pulse amplitude modulation, PAM), for example, PAM4. For PAM4 modulation, one PAM4 modulation symbol corresponds to L=2 bits.
The following describes a specific implementation of the mapping by using an example in which the target bit set is represented as the third matrix H3.
Every L consecutive bits in m bits in each column in the third matrix H3 are mapped to one modulation symbol. Each third matrix H3 is mapped to m×N/L modulation symbols.
In an embodiment, m/L modulation symbols obtained through the mapping of the m bits in each column in the third matrix H3 are consecutive in the modulation symbol stream. In other words, the m/L modulation symbols obtained through the mapping of each column in the third matrix H3 are used as m/L consecutive modulation symbols in the modulation symbol stream, and the m×N/L modulation symbols obtained through the mapping of the N columns in the third matrix H3 are used as m×N/L consecutive modulation symbols in the modulation symbol stream.
In another embodiment, m bits in a column B in the third matrix H3 are mapped to obtain m/L first modulation symbols, every T consecutive first modulation symbols in the m/L first modulation symbols are consecutive in the modulation symbol stream, m bits in a column C in the third matrix H3 are mapped to obtain m/L second modulation symbols, every T consecutive second modulation symbols in the m/L second modulation symbols are consecutive in the modulation symbol stream, the column B is adjacent to the column C, the T consecutive first modulation symbols in the m/L first modulation symbols and the T consecutive second modulation symbols in the m/L second modulation symbols are consecutive in the modulation symbol stream, and m/L is divisible by T.
L bits in each modulation symbol are from Lr inner-code codewords. Lc bits in each of the Lr inner-code codewords, namely, a total of Lr×Lc bits, are mapped to one modulation symbol. 2L bits in two consecutive modulation symbols are from 2Lr inner-code codewords. Lc bits in each of the 2Lr inner-code codewords are mapped to the two consecutive modulation symbols. L=Lr×Lc, and Lc>1. In other words, a total of Lr×Lc=L bits in Lc columns in every Lr rows in the third matrix H3 are mapped to one modulation symbol, where Lc>1. For example, L inner-code bits respectively corresponding to a bit b0, a bit b1, . . . , and a bit bL-1 in one modulation symbol are from Lr different inner-code codewords, and each inner-code codeword provides Lc bits. For the third matrix H3, a total of m×Lc bits in every Lc columns are mapped to m/Lr modulation symbols. Each third matrix H3 is mapped to m×N/L modulation symbols, to obtain m×N/L consecutive modulation symbols in the modulation symbol data stream.
In an embodiment, the m/Lr modulation symbols obtained through the mapping of the every Lc columns in the third matrix H3 are used as m/Lr consecutive modulation symbols in the modulation symbol stream, and the m×N/L modulation symbols obtained through the mapping of the N columns are used as the m×N/L consecutive modulation symbols in the modulation symbol stream.
the total of m×Lc bits in the every Lc columns in the third matrix H3 are mapped to
modulation symbols that are respectively represented by using S(0,j) and S(1,j), where 0≤j<N/Lc.
In another embodiment, bits in a column B in the third matrix H3 are mapped to obtain m/Lr first modulation symbols, every T consecutive first modulation symbols in the m/Lr first modulation symbols are consecutive in the modulation symbol stream, bits in a column C in each target bit set are mapped to obtain m/Lr second modulation symbols, every T consecutive second modulation symbols in the m/Lr second modulation symbols are consecutive in the modulation symbol stream, the column B includes Lc columns, the column C also includes Lc columns, the column B is adjacent to the column C, the T consecutive first modulation symbols in the m/Lr first modulation symbols and the T consecutive second modulation symbols in the m/Lr second modulation symbols are consecutive in the modulation symbol stream, and m/Lr is divisible by T.
and T=2, the total of m×Lc bits in the every Lc columns in the third matrix H3 are mapped to
modulation symbols that are respectively represented by using S(0,j), S(1,j), S(2,j), and S(3,j), where 0≤j<N/Lc. It can be learned that the first T modulation symbols in the m/Lr modulation symbols obtained through the mapping of the every Lc columns are used as T consecutive modulation symbols in the first modulation symbol stream. Correspondingly, a total of T×N/Lc modulation symbols in the N columns are used as T×N/Lc consecutive modulation symbols in the modulation symbol stream. Next T modulation symbols in the m/Lr modulation symbols obtained through the mapping of the every Lc columns are used as T consecutive modulation symbols in the first modulation symbol stream. Correspondingly, a total of T×N/Lc modulation symbols in the N columns are used as next T×N/Lc consecutive modulation symbols in the modulation symbol stream. By analogy, m×N/L consecutive modulation symbols in the modulation symbol stream may be obtained.
In this embodiment of this application, a concatenated-FEC transmission solution is used. That is, the outer-code encoding and the inner-code encoding are sequentially performed on the data streams. On this basis, this application designs a bit interleaving and mapping method, so that both bits in an outer-code codeword and bits in an inner-code codeword are discretely and evenly mapped to modulation symbols. In this way, the concatenated-FEC transmission solution has a strong burst resistance capability. Particularly, a burst error with a small length may be directly corrected through inner-code decoding. The concatenated-FEC transmission solution is widely applicable to transmission scenarios, particularly an actual coherent transmission scenario in which there is colored noise on a channel.
With reference to some specific embodiments, the following further describes a procedure of the data processing method described in
A physical medium attachment (PMA) sublayer of a transmitter processing module processes data from a plurality of synchronous client lanes to obtain n=32 first data streams. The 32 first data streams are separately sent to inner-code encoders for inner-code encoding to obtain 32 second data streams. BCH(176,160) is used for the inner-code encoding. That is, a codeword bit length N=176, an information bit length K=160, and a parity bit length P=16. 160 information bits in each inner-code codeword are from 16 symbols in 16 different outer-code RS codewords.
32 codewords obtained through the inner-code encoding are grouped into h=2 codeword sets, and each codeword set includes m=16 BCH(176,160) codewords. In consideration of DP-16QAM modulation, every L=8 bits are mapped to one DP-16QAM symbol. 352 DP-16QAM symbols may be obtained through bit interleaving and mapping of the 16 BCH(176,160) codewords in each codeword set.
A total of 2816 bits in the foregoing 16 BCH(176,160) codewords are represented by using a first matrix H1 with 16 rows and 176 columns, where each row in the first matrix H1 includes 176 bits in one inner-code BCH(176,160) codeword. The bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with 16 rows and 176 columns. An interleaving correspondence between the first matrix H1 and the third matrix H3 is: for 0; i<16,
In the foregoing third matrix H3 with the 16 rows and the 176 columns, each column includes 16 bits. Every eight bits in the 16 bits are mapped to one DP-16QAM symbol. Each column is separately mapped to two modulation symbols. In a specific implementation, in each column, the 0th row to the 7th row are mapped to one DP-16QAM symbol, and the 8th row to the 15th row are mapped to the other DP-16QAM symbol. Each third matrix H3 is mapped to 352 DP-16QAM symbols. The two DP-16QAM symbols obtained through the mapping of each column are used as two consecutive DP-16QAM symbols in a first modulation symbol stream, and 352 DP-16QAM symbols obtained through the mapping of the 176 columns are used as 352 consecutive DP-16QAM symbols in the first modulation symbol stream.
Every 16 codewords in the 32 codewords undergo the bit interleaving, and then are mapped to 352 DP-16QAM symbols. The 32 codewords undergo the bit interleaving, and then are mapped to a total of 704 DP-16QAM symbols, and the 704 DP-16QAM symbols are used as 704 consecutive DP-16QAM symbols in the first modulation symbol stream.
In this embodiment, when there is colored noise in actual transmission, and the colored noise has a width of four DP-16QAM symbols, 32 error bits can be scattered to a plurality of inner-code BCH(176,160) codewords, and a quantity of error bits corresponding to each inner-code BCH(176,160) codeword is not greater than 2. Because the inner code BCH(176,160) can correct two bits is considered, colored noise with a width of two or three DP-16QAM symbols can be effectively corrected by the inner code. In addition, according to the designed bit interleaving and mapping method, an overall concatenated-FEC solution can resist a burst error with a length greater than 1500 bits. That is, according to the designed bit interleaving and mapping method, the overall concatenated-FEC solution can effectively resist the colored noise with the width of up to the four DP-16QAM symbols, and can resist the burst error with the length greater than 1500 bits. According to the designed bit interleaving and mapping method, the overall concatenated-FEC solution can effectively resist the colored noise with the width of up to the four DP-16QAM symbols, and can resist the burst error with the length greater than 1500 bits.
Based on the solution in Embodiment 1, a total of 2816 bits in 16 BCH(176,160) codewords are represented by using a first matrix H1 with 16 rows and 176 columns, and data obtained through bit interleaving of the first matrix H1 is not represented by using the third matrix H3 with the 16 rows and the 176 columns shown in Embodiment 1, but is represented by using an array A with a length of 2816 bits. The bit interleaving is performed on the first matrix H1 to obtain the array A with the length of 2816 bits. An interleaving correspondence between the first matrix H1 and array A is: for 0; i<16,
Every eight consecutive bits in the first array A that includes the 2816 bits are mapped to one DP-16QAM symbol, to obtain 352 DP-16QAM symbols, and the 352 DP-16QAM symbols are used as 352 consecutive DP-16QAM symbols in a first modulation symbol stream.
Every 16 codewords in the 32 codewords undergo the bit interleaving, and then are mapped to 352 DP-16QAM symbols. The 32 codewords undergo the bit interleaving, and then are mapped to a total of 704 DP-16QAM symbols, and the 704 DP-16QAM symbols are used as 704 consecutive DP-16QAM symbols in the first modulation symbol stream.
It should be noted that, when values of the row offset constraint factor Δ and the column offset constraint factor θ in Embodiment 1 are respectively equal to values of Δ and θ in Embodiment 2, the 704 DP-16QAM symbols that are the same as those in Embodiment 2 are obtained through the bit interleaving and the mapping of the 32 codewords in Embodiment 2.
In this embodiment, according to the designed bit interleaving and mapping method, an overall concatenated-FEC solution can effectively resist colored noise with a width of up to four DP-16QAM symbols, and can resist a burst error with a length greater than 1500 bits.
Based on the solution in Embodiment 1, 32 codewords obtained through inner-code encoding are not grouped into two codeword sets shown in Embodiment 1, but are grouped into four codeword sets, where each codeword set includes m=8 BCH(176,160) codewords. In consideration of DP-16QAM modulation, every L=8 bits are mapped to one DP-16QAM symbol. 176 DP-16QAM symbols may be obtained through bit interleaving and mapping of the eight BCH(176,160) codewords in each codeword set.
A total of 1408 bits in the foregoing eight BCH(176,160) codewords are represented by using a first matrix H1 with eight rows and 176 columns, where each row in the first matrix H1 includes 176 bits in one inner-code BCH(176,160) codeword. The bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with eight rows and 176 columns. An interleaving correspondence between the first matrix H1 and the third matrix H3 is: for 0≤i<8,
The foregoing formula can be simplified as:
In the foregoing third matrix H3 with the eight rows and the 176 columns, each column includes eight bits. The eight bits in each column are mapped to one DP-16QAM symbol. Each third matrix H3 is mapped to 176 DP-16QAM symbols. The 176 DP-16QAM symbols obtained through the mapping of the 176 columns are used as 176 consecutive DP-16QAM symbols in a first modulation symbol stream.
Every eight codewords in the 32 codewords undergo the bit interleaving, and then are mapped to 176 DP-16QAM symbols. The 32 codewords undergo the bit interleaving, and then are mapped to a total of 704 DP-16QAM symbols, and the 704 DP-16QAM symbols are used as 704 consecutive DP-16QAM symbols in the first modulation symbol stream.
In this embodiment, according to the designed bit interleaving and mapping method, an overall concatenated-FEC solution can effectively resist colored noise with a width of up to two DP-16QAM symbols, and can resist a burst error with a length greater than 2000 bits.
Based on the solution in Embodiment 3, a total of 1408 bits in eight BCH(176,160) codewords are represented by using a first matrix H1 with eight rows and 176 columns, and data obtained through bit interleaving of the first matrix H1 is not represented by using the third matrix H3 with the eight rows and the 176 columns shown in Embodiment 1, but is represented by using an array A with a length of 1408 bits. The bit interleaving is performed on the first matrix H1 to obtain the array A with the length of 1408 bits. An interleaving correspondence between the first matrix H1 and array A is: for 0; i<8,
Every eight consecutive bits in the first array A that includes the 1408 bits are mapped to one DP-16QAM symbol, to obtain 176 DP-16QAM symbols, and the 176 DP-16QAM symbols are used as 176 consecutive DP-16QAM symbols in a first modulation symbol stream.
Every eight codewords in the 32 codewords undergo the bit interleaving, and then are mapped to 176 DP-16QAM symbols. The 32 codewords undergo the bit interleaving, and then are mapped to a total of 704 DP-16QAM symbols.
It should be noted that, when values of the row offset constraint factor Δ and the column offset constraint factor θ in Embodiment 4 are respectively equal to values of Δ and θ in Embodiment 3, the 704 DP-16QAM symbols that are the same as those in Embodiment 3 are obtained through the bit interleaving and the mapping of the 32 codewords in Embodiment 4.
In this embodiment, according to the designed bit interleaving and mapping method, an overall concatenated-FEC solution can effectively resist colored noise with a width of up to two DP-16QAM symbols, and can resist a burst error with a length greater than 2000 bits.
Based on the solution in Embodiment 1, 32 codewords obtained through inner-code encoding are not grouped into two codeword sets shown in Embodiment 1, but are used as one codeword set including m=32 BCH(176,160) codewords. In consideration of DP-16QAM modulation, every L=8 bits are mapped to one DP-16QAM symbol. 704 DP-16QAM symbols may be obtained through bit interleaving and mapping of the 32 BCH(176,160) codewords.
A total of 5632 bits in the foregoing 32 BCH(176,160) codewords are represented by using a first matrix H1 with 32 rows and 176 columns, where each row in the first matrix H1 includes 176 bits in one inner-code BCH(176,160) codeword. The bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with 32 rows and 176 columns. An interleaving correspondence between the first matrix H1 and the third matrix H3 is: for 0; i<32,
In the foregoing third matrix H3 with the 32 rows and the 176 columns, each column includes 32 bits. The 32 bits in each column are mapped to four DP-16QAM symbols. The 32 codewords undergo the bit interleaving, and then are mapped to a total of 704 DP-16QAM symbols, and 704 consecutive DP-16QAM symbols in a first modulation symbol stream consist of the 704 DP-16QAM symbols.
In a specific implementation, in terms of the first T=1 DP-16QAM symbol in the four DP-16QAM symbols obtained through the mapping of each column (namely, the 0th DP-16QAM symbol obtained through the mapping of each column), a total of 176 DP-16QAM symbols in the 176 columns are used as 176 consecutive DP-16QAM symbols in the first modulation symbol stream; in terms of next T=1 DP-16QAM symbol in the four DP-16QAM symbols obtained through the mapping of each column (namely, the 1St DP-16QAM symbol obtained through the mapping of each column), a total of 176 DP-16QAM symbols in the 176 columns are used as next 176 consecutive DP-16QAM symbols in the first modulation symbol stream; and by analogy, the 704 consecutive DP-16QAM symbols in the first modulation symbol stream may be obtained.
In this embodiment, according to the designed bit interleaving and mapping method, an overall concatenated-FEC solution can effectively resist colored noise with a width of up to two DP-16QAM symbols, and can resist a burst error with a length greater than 2000 bits.
Based on the solution in Embodiment 5, 32 codewords undergo bit interleaving, then are mapped to a total of 704 DP-16QAM symbols, and 704 consecutive DP-16QAM symbols in a first modulation symbol stream consist of the 704 DP-16QAM symbols. This embodiment provides another specific implementation: In terms of the first two DP-16QAM symbols in four DP-16QAM symbols obtained through the mapping of each column (namely, the 0th and the 1st DP-16QAM symbols obtained through the mapping of each column), a total of 352 DP-16QAM symbols in 176 columns are used as 352 consecutive DP-16QAM symbols in the first modulation symbol stream; in terms of the last two DP-16QAM symbols in the four DP-16QAM symbols obtained through the mapping of each column (namely, the 2nd and the 3rd DP-16QAM symbols obtained through the mapping of each column), a total of 352 DP-16QAM symbols in the 176 columns are used as next 352 consecutive DP-16QAM symbols in the first modulation symbol stream; and finally, the 704 consecutive DP-16QAM symbols in the first modulation symbol stream are obtained.
In this embodiment, according to the designed bit interleaving and mapping method, an overall concatenated-FEC solution can effectively resist colored noise with a width of up to four DP-16QAM symbols, and can resist a burst error with a length greater than 1500 bits.
A physical medium attachment (PMA) sublayer of a transmitter processing module processes data from a plurality of synchronous client lanes to obtain n=16 first data streams. The 16 first data streams are separately sent to inner-code encoders for inner-code encoding to obtain 16 second data streams. BCH(176,160) is used for the inner-code encoding. That is, a codeword bit length N=176, an information bit length K=160, and a parity bit length P=16. 160 information bits in each inner-code codeword are from 16 symbols in 16 different outer-code RS codewords.
The foregoing 16 inner-code codewords are used as one codeword set, and include m=16 BCH(176,160) codewords. In consideration of DP-16QAM modulation, every L=8 bits are mapped to one DP-16QAM symbol. 352 DP-16QAM symbols may be obtained through bit interleaving and mapping of the 16 BCH(176,160) codewords.
A total of 2816 bits in the foregoing 16 BCH(176,160) codewords are represented by using a first matrix H1 with 16 rows and 176 columns, where each row in the first matrix H1 includes 176 bits in one inner-code BCH(176,160) codeword. The bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with 16 rows and 176 columns. An interleaving correspondence between the first matrix H1 and the third matrix H3 is: for 0; i<16,
In the foregoing third matrix H3 with the 16 rows and the 176 columns, each column includes 16 bits. The 16 bits in each column are mapped to two DP-16QAM symbols. In a specific implementation, in each column, the 0th row to the 7th row are mapped to one DP-16QAM symbol, and the 8th row to the 15th row are mapped to the other DP-16QAM symbol. The 16 codewords undergo the bit interleaving, and then are mapped to a total of 352 DP-16QAM symbols, and 352 consecutive DP-16QAM symbols in a first modulation symbol stream consist of the 352 DP-16QAM symbols. In a specific implementation, the two DP-16QAM symbols obtained through the mapping of each column are used as two consecutive DP-16QAM symbols in the first modulation symbol stream, and 352 DP-16QAM symbols obtained through the mapping of the 176 columns are used as the 352 consecutive DP-16QAM symbols in the first modulation symbol stream.
It should be noted that 2816-bit interleaved data obtained through the bit interleaving of the first matrix H1 is represented by using the third matrix H3 with the 16 rows and the 176 columns, or may be represented by using an array with a length of 2816 bits as shown in Embodiment 2 and Embodiment 4. A specific implementation thereof is known to a person of ordinary skill in the art. Details are not described herein again.
In this embodiment, according to the designed bit interleaving and mapping method, an overall concatenated-FEC solution can effectively resist colored noise with a width of up to four DP-16QAM symbols, and can resist a burst error with a length greater than 1500 bits.
It should be noted that, an operation procedure of the transmitter processing module may alternatively be as shown in
A physical medium attachment (PMA) sublayer of a transmitter processing module processes data from a plurality of synchronous client lanes to obtain n=8 first data streams. The eight first data streams are separately sent to inner-code encoders for inner-code encoding to obtain eight second data streams. A Hamming code Hamming(128,120) is used for the inner-code encoding. That is, a codeword bit length N=128, an information bit length K=120, and a parity bit length P=8. 120 information bits in each inner-code codeword are from 12 symbols in 12 different outer-code RS codewords.
The foregoing eight inner-code codewords are used as one codeword set, and include m=8 Hamming code Hamming(128,120) codewords. In consideration of PAM4 modulation, every L=2 bits are mapped to one PAM4 symbol. 512 PAM4 symbols may be obtained through bit interleaving and mapping of the eight Hamming(128,120) codewords.
A total of 1024 bits in the foregoing eight Hamming(128,120) codewords are represented by using a first matrix H1 with eight rows and 128 columns, where each row in the first matrix H1 includes 128 bits in one inner-code Hamming(128,120) codeword. The bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with eight rows and 128 columns. An interleaving correspondence between the first matrix H1 and the third matrix H3 is: for 0; i<8,
In the foregoing third matrix H3 with the eight rows and the 176 columns, each column includes eight bits. The eight bits in each column are mapped to four PAM4 symbols. In a specific implementation, in each column, two bits in the 0th row and the 1st row are mapped to one PAM4 symbol, two bits in the 2nd row and the 3rd row are mapped to another PAM4 symbol, two bits in the 4th row and the 5th row are mapped to still another PAM4 symbol, and two bits in the 6th row and the 7th row are mapped to yet another PAM4 symbol. The eight codewords undergo the bit interleaving, and then are mapped to a total of 512 PAM4 symbols, and 512 consecutive PAM4 symbols in a first modulation symbol stream consist of the 512 PAM4 symbols. In a specific implementation, the four PAM4 symbols obtained through the mapping of each column are used as four consecutive PAM4 symbols in the first modulation symbol stream, and 512 PAM4 symbols obtained through the mapping of the 128 columns are used as the 512 consecutive PAM4 symbols in the first modulation symbol stream.
In this embodiment, according to the designed bit interleaving and mapping method, an overall concatenated-FEC solution can effectively resist colored noise with a width of up to four PAM4 symbols, and can resist a burst error with a length greater than 1200 bits.
A physical medium attachment (PMA) sublayer of a transmitter processing module processes data from a plurality of synchronous client lanes to obtain n=32 first data streams.
One Hamming(128,120) codeword is obtained from each second data stream above. A total of 1024 bits in a total of eight Hamming(128,120) codewords are represented by using a first matrix H1 with eight rows and 128 columns, where each row in the first matrix H1 includes 128 bits in one inner-code Hamming(128,120) codeword. Bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with eight rows and 128 columns. An interleaving correspondence between the first matrix H1 and the third matrix H3 is: for 0≤i<8,
Another interleaving mapping relationship is:
In the foregoing third matrix H3 with the eight rows and the 176 columns, each column includes eight bits. The eight bits in each column are mapped to four PAM4 symbols. In a specific implementation, in each column, two bits in the 0th row and the 1st row are mapped to one PAM4 symbol, two bits in the 2nd row and the 3rd row are mapped to another PAM4 symbol, two bits in the 4th row and the 5th row are mapped to still another PAM4 symbol, and two bits in the 6th row and the 7th row are mapped to yet another PAM4 symbol. The eight codewords undergo the bit interleaving, and then are mapped to a total of 512 PAM4 symbols, and 512 consecutive PAM4 symbols in a first modulation symbol stream consist of the 512 PAM4 symbols.
In this embodiment, according to the designed bit interleaving and mapping method, an overall concatenated-FEC solution can effectively resist colored noise with a width of up to eight PAM4 symbols on each channel, and can resist a burst error with a length greater than 1100 bits.
It should be noted that, an operation procedure of the transmitter processing module may alternatively be as shown in
A physical medium attachment (PMA) sublayer of a transmitter processing module processes data from a plurality of synchronous client lanes to obtain n=32 first data streams. The 32 first data streams are separately sent to inner-code encoders for inner-code encoding to obtain 32 second data streams. BCH(176,160) is used for the inner-code encoding. That is, a codeword bit length N=176, an information bit length K=160, and a parity bit length P=16. 160 information bits in each inner-code codeword are from 16 symbols in 16 different outer-code RS codewords.
32 codewords obtained through the inner-code encoding are grouped into four codeword sets, and each codeword set includes m=8 BCH(176,160) codewords. In consideration of DP-16QAM modulation, every L=8 bits are mapped to one DP-16QAM symbol. 176 DP-16QAM symbols may be obtained through bit interleaving and mapping of the eight BCH(176,160) codewords in each codeword set.
A total of 1408 bits in the foregoing eight BCH(176,160) codewords are represented by using a first matrix H1 with eight rows and 176 columns, where each row in the first matrix H1 includes 176 bits in one inner-code BCH(176,160) codeword. The bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with eight rows and 176 columns. An interleaving correspondence between the first matrix H1 and the third matrix H3 is: for 0≤i<8,
In the foregoing third matrix H3 with the eight rows and the 176 columns, each column includes eight bits. In consideration of Lr=4 and Lc=2, a total of eight bits in two columns in every four rows are mapped to one DP-16QAM symbol. In the third matrix H3, 2 modulation symbols obtained through the mapping of every 2 columns are used as 2 consecutive modulation symbols in a first modulation symbol stream, and 176 modulation symbols obtained through the mapping of the 176 columns are used as 176 consecutive modulation symbols in the first modulation symbol stream, and are used as 176 consecutive DP-16QAM symbols in the first modulation symbol stream.
Every eight codewords in the 32 codewords undergo the bit interleaving, and then are mapped to 176 DP-16QAM symbols. The 32 codewords undergo the bit interleaving, and then are mapped to a total of 704 DP-16QAM symbols, and the 704 DP-16QAM symbols are used as 704 consecutive DP-16QAM symbols in the first modulation symbol stream.
A physical medium attachment (PMA) sublayer of a transmitter processing module processes data from a plurality of synchronous client lanes to obtain n=32 first data streams. The 32 first data streams are separately sent to inner-code encoders for inner-code encoding to obtain 32 second data streams. BCH(176,160) is used for the inner-code encoding. That is, a codeword bit length N=176, an information bit length K=160, and a parity bit length P=16. 160 information bits in each inner-code codeword are from 16 symbols in 16 different outer-code RS codewords.
32 codewords obtained through the inner-code encoding are grouped into two codeword sets, and each codeword set includes m=16 BCH(176,160) codewords. In consideration of DP-16QAM modulation, every L=8 bits are mapped to one DP-16QAM symbol. 352 DP-16QAM symbols may be obtained through bit interleaving and mapping of the 16 BCH(176,160) codewords in each codeword set.
A total of 1408 bits in the foregoing 16 BCH(176,160) codewords are represented by using a first matrix H1 with 16 rows and 176 columns, where each row in the first matrix H1 includes 176 bits in one inner-code BCH(176,160) codeword. The bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with 16 rows and 176 columns. An interleaving correspondence between the first matrix H1 and the third matrix H3 is: for 0≤i<16,
In the foregoing third matrix H3 with the 16 rows and the 176 columns, each column includes 16 bits. In consideration of Lr=4 and Lc=2, a total of eight bits in two columns in every four rows are mapped to one DP-16QAM symbol. Every 2 columns in the third matrix H3 are mapped to obtain 4 DP-16QAM symbols.
In terms of the first two DP-16QAM symbols in the four DP-16QAM symbols obtained through the mapping of the every two columns (namely, the 0th and the 1st DP-16QAM symbols obtained through the mapping of the every two columns) in the third matrix H3, a total of 176 DP-16QAM symbols in the 176 columns are used as 176 consecutive DP-16QAM symbols in a first modulation symbol stream; in terms of the last two DP-16QAM symbol in the four DP-16QAM symbols obtained through the mapping of the every two columns (namely, the 2nd and the 3rd DP-16QAM symbols obtained through the mapping of the every two columns), a total of 176 DP-16QAM symbols in the 176 columns are used as next 176 consecutive DP-16QAM symbols in the first modulation symbol stream; and finally, 352 consecutive DP-16QAM symbols in the first modulation symbol stream are obtained.
Every 16 codewords in the 32 codewords undergo the bit interleaving, and then are mapped to 352 DP-16QAM symbols. The 32 codewords undergo the bit interleaving, and then are mapped to a total of 704 DP-16QAM symbols, and the 704 DP-16QAM symbols are used as 704 consecutive DP-16QAM symbols in the first modulation symbol stream.
A physical medium attachment (PMA) sublayer of a transmitter processing module processes data from a plurality of synchronous client lanes to obtain n=32 first data streams. The 32 first data streams are separately sent to inner-code encoders for inner-code encoding to obtain 32 second data streams. BCH(126,110) is used for the inner-code encoding. That is, a codeword bit length N=126, an information bit length K=110, and a parity bit length P=16. 110 information bits in each inner-code codeword are from 11 symbols in 11 different outer-code RS codewords.
32 codewords obtained through the inner-code encoding are grouped into h=2 codeword sets, and each codeword set includes m=16 BCH(126,110) codewords. In consideration of DP-16QAM modulation, every L=8 bits are mapped to one DP-16QAM symbol. 252 DP-16QAM symbols may be obtained through bit interleaving and mapping of the 16 BCH(126,110) codewords in each codeword set.
A total of 2016 bits in the foregoing 16 BCH(126,110) codewords are represented by using a first matrix H1 with 16 rows and 126 columns, where each row in the first matrix H1 includes 126 bits in one inner-code BCH(126,110) codeword. The bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with 16 rows and 126 columns. An interleaving correspondence between the first matrix H1 and the third matrix H3 is: for 0; i<16,
In the foregoing third matrix H3 with the 16 rows and the 126 columns, each column includes 16 bits. Every eight bits in the 16 bits are mapped to one DP-16QAM symbol. Each column is separately mapped to two modulation symbols. In a specific implementation, in each column, the 0th row to the 7th row are mapped to one DP-16QAM symbol, and the 8th row to the 15th row are mapped to the other DP-16QAM symbol. Each third matrix H3 is mapped to 252 DP-16QAM symbols. The two DP-16QAM symbols obtained through the mapping of each column are used as two consecutive DP-16QAM symbols in a first modulation symbol stream, and 252 DP-16QAM symbols obtained through the mapping of 126 columns are used as 252 consecutive DP-16QAM symbols in the first modulation symbol stream.
Every 16 codewords in the 32 codewords undergo the bit interleaving, and then are mapped to 252 DP-16QAM symbols. The 32 codewords undergo the bit interleaving, and then are mapped to a total of 504 DP-16QAM symbols, and the 504 DP-16QAM symbols are used as 504 consecutive DP-16QAM symbols in the first modulation symbol stream.
In this embodiment, when there is colored noise in actual transmission, and the colored noise has a width of four DP-16QAM symbols, 32 error bits can be scattered to a plurality of inner codes BCH(126,110), and a quantity of error bits corresponding to each inner code is not greater than 2. Because the inner code BCH(126,110) can correct two bits is considered, colored noise with a width of two or three DP-16QAM symbols can be effectively corrected by the inner code. In addition, according to the designed bit interleaving and mapping method, an overall concatenated-FEC solution can resist a burst error with a length greater than 1200 bits. That is, according to the designed bit interleaving and mapping method, the overall concatenated-FEC solution can effectively resist the colored noise with the width of up to the four DP-16QAM symbols, and can resist the burst error with the length greater than 1200 bits. According to the designed bit interleaving and mapping method, the overall concatenated-FEC solution can effectively resist the colored noise with the width of up to the four DP-16QAM symbols, and can resist the burst error with the length greater than 1200 bits.
Based on the solution in Embodiment 12, a total of 2016 bits in 16 BCH(126,110) codewords are represented by using a first matrix H1 with 16 rows and 126 columns, and data obtained through bit interleaving of the first matrix H1 is not represented by using the third matrix H3 with the 16 rows and the 126 columns shown in Embodiment 1, but is represented by using an array A with a length of 2016 bits. The bit interleaving is performed on the first matrix H1 to obtain the array A with the length of 2016 bits. An interleaving correspondence between the first matrix H1 and array A is: for 0≤i<16,
Every eight consecutive bits in the first array A that includes the 2016 bits are mapped to one DP-16QAM symbol, to obtain 252 DP-16QAM symbols, and the 252 DP-16QAM symbols are used as 252 consecutive DP-16QAM symbols in a first modulation symbol stream.
Every 16 codewords in the 32 codewords undergo the bit interleaving, and then are mapped to 252 DP-16QAM symbols. The 32 codewords undergo the bit interleaving, and then are mapped to a total of 504 DP-16QAM symbols, and the 504 DP-16QAM symbols are used as 504 consecutive DP-16QAM symbols in the first modulation symbol stream.
It should be noted that, when values of the row offset constraint factor Δ and the column offset constraint factor θ in Embodiment 11 are respectively equal to values of Δ and θ in Embodiment 12, the 504 DP-16QAM symbols that are the same as those in Embodiment 12 are obtained through the bit interleaving and the mapping of the 32 codewords in Embodiment 11.
In this embodiment, according to the designed bit interleaving and mapping method, an overall concatenated-FEC solution can effectively resist colored noise with a width of up to four DP-16QAM symbols, and can resist a burst error with a length greater than 1200 bits.
A physical medium attachment (PMA) sublayer of a transmitter processing module processes data from a plurality of synchronous client lanes to obtain n=32 first data streams. The 32 first data streams are separately sent to inner-code encoders for inner-code encoding to obtain 32 second data streams. BCH(126,110) is used for the inner-code encoding. That is, a codeword bit length N=126, an information bit length K=110, and a parity bit length P=16. 110 information bits in each inner-code codeword are from 11 symbols in 11 different outer-code RS codewords.
32 codewords obtained through the inner-code encoding are grouped into four codeword sets, and each codeword set includes m=8 BCH(126,110) codewords. In consideration of DP-16QAM modulation, every L=8 bits are mapped to one DP-16QAM symbol. 126 DP-16QAM symbols may be obtained through bit interleaving and mapping of the eight BCH(126,110) codewords in each codeword set.
A total of 1008 bits in the foregoing eight BCH(126,110) codewords are represented by using a first matrix H1 with eight rows and 126 columns, where each row in the first matrix H1 includes 126 bits in one inner-code BCH(126,110) codeword. The bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with eight rows and 126 columns. An interleaving correspondence between the first matrix H1 and the third matrix H3 is: for 0≤i<8,
In the foregoing third matrix H3 with the eight rows and the 126 columns, each column includes eight bits. In consideration of Lr=4 and Lc=2, a total of eight bits in two columns in every four rows are mapped to one DP-16QAM symbol. In the third matrix H3, 2 modulation symbols obtained through the mapping of every 2 columns are used as 2 consecutive modulation symbols in a first modulation symbol stream, and 126 modulation symbols obtained through the mapping of the 126 columns are used as 126 consecutive modulation symbols in the first modulation symbol stream, and are used as 126 consecutive DP-16QAM symbols in the first modulation symbol stream.
Every eight codewords in the 32 codewords undergo the bit interleaving, and then are mapped to 126 DP-16QAM symbols. The 32 codewords undergo the bit interleaving, and then are mapped to a total of 504 DP-16QAM symbols, and the 504 DP-16QAM symbols are used as 504 consecutive DP-16QAM symbols in the first modulation symbol stream.
A physical medium attachment (PMA) sublayer of a transmitter processing module processes data from a plurality of synchronous client lanes to obtain n=16 first data streams. The 16 first data streams are separately sent to inner-code encoders for inner-code encoding to obtain 16 second data streams. BCH(136,120) is used for the inner-code encoding. That is, a codeword bit length N=136, an information bit length K=120, and a parity bit length P=16. 120 information bits in each inner-code codeword are from 12 symbols in 12 different outer-code RS codewords.
16 codewords obtained through the inner-code encoding are used as h=1 codeword set, and the codeword set includes m=16 BCH(136,120) codewords. In consideration of DP-16QAM modulation, every L=8 bits are mapped to one DP-16QAM symbol. 272 DP-16QAM symbols may be obtained through bit interleaving and mapping of the 16 BCH(136,120) codewords in each codeword set.
A total of 2176 bits in the foregoing 16 BCH(136,120) codewords are represented by using a first matrix H1 with 16 rows and 136 columns, where each row in the first matrix H1 includes 136 bits in one inner-code BCH(136,120) codeword. The bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with 16 rows and 136 columns. An interleaving correspondence between the first matrix H1 and the third matrix H3 is: for 0; i<16,
In the foregoing third matrix H3 with the 16 rows and the 136 columns, each column includes 16 bits. Every eight bits in the 16 bits are mapped to one DP-16QAM symbol. Each column is separately mapped to two modulation symbols. In a specific implementation, in each column, the 0th row to the 7th row are mapped to one DP-16QAM symbol, and the 8th row to the 15th row are mapped to the other DP-16QAM symbol. Each third matrix H3 is mapped to 272 DP-16QAM symbols. The two DP-16QAM symbols obtained through the mapping of each column are used as two consecutive DP-16QAM symbols in a first modulation symbol stream, and 272 DP-16QAM symbols obtained through the mapping of the 136 columns are used as 272 consecutive DP-16QAM symbols in the first modulation symbol stream.
In this embodiment, when there is colored noise in actual transmission, and the colored noise has a width of four DP-16QAM symbols, 32 error bits can be scattered to a plurality of inner codes BCH(136,120), and a quantity of error bits corresponding to each inner code is not greater than 2. Because the inner code BCH(136,120) can correct two bits is considered, colored noise with a width of two or three DP-16QAM symbols can be effectively corrected by the inner code. In addition, according to the designed bit interleaving and mapping method, an overall concatenated-FEC solution can resist a burst error with a length greater than 1200 bits. That is, according to the designed bit interleaving and mapping method, the overall concatenated-FEC solution can effectively resist the colored noise with the width of up to the four DP-16QAM symbols, and can resist the burst error with the length greater than 1200 bits. According to the designed bit interleaving and mapping method, the overall concatenated-FEC solution can effectively resist the colored noise with the width of up to the four DP-16QAM symbols, and can resist the burst error with the length greater than 1200 bits.
Based on the solution in Embodiment 15, a total of 2176 bits in 16 BCH(136,120) codewords are represented by using a first matrix H1 with 16 rows and 136 columns, and data obtained through bit interleaving of the first matrix H1 is not represented by using the third matrix H3 with the 16 rows and the 136 columns shown in Embodiment 1, but is represented by using an array A with a length of 2176 bits. The bit interleaving is performed on the first matrix H1 to obtain the array A with the length of 2176 bits. An interleaving correspondence between the first matrix H1 and array A is: for 0 i<16,
Every eight consecutive bits in the first array A that includes the 2176 bits are mapped to one DP-16QAM symbol, to obtain 272 DP-16QAM symbols, and the 272 DP-16QAM symbols are used as 272 consecutive DP-16QAM symbols in a first modulation symbol stream.
In this embodiment, according to the designed bit interleaving and mapping method, an overall concatenated-FEC solution can effectively resist colored noise with a width of up to four DP-16QAM symbols, and can resist a burst error with a length greater than 1200 bits.
A physical medium attachment (PMA) sublayer of a transmitter processing module processes data from a plurality of synchronous client lanes to obtain n=16 first data streams. The 16 first data streams are separately sent to inner-code encoders for inner-code encoding to obtain 16 second data streams. BCH(136,120) is used for the inner-code encoding. That is, a codeword bit length N=136, an information bit length K=120, and a parity bit length P=16. 120 information bits in each inner-code codeword are from 12 symbols in 12 different outer-code RS codewords.
16 codewords obtained through the inner-code encoding are grouped into two codeword sets, and each codeword set includes m=8 BCH(136,110) codewords. In consideration of DP-16QAM modulation, every L=8 bits are mapped to one DP-16QAM symbol. 136 DP-16QAM symbols may be obtained through bit interleaving and mapping of the eight BCH(136,120) codewords in each codeword set.
A total of 1088 bits in the foregoing eight BCH(136,120) codewords are represented by using a first matrix H1 with eight rows and 136 columns, where each row in the first matrix H1 includes 136 bits in one inner-code BCH(136,120) codeword. The bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with eight rows and 136 columns. An interleaving correspondence between the first matrix H1 and the third matrix H3 is: for 0≤i<8,
In the foregoing third matrix H3 with the eight rows and the 136 columns, each column includes eight bits. In consideration of Lr=4 and Lc=2, a total of eight bits in two columns in every four rows are mapped to one DP-16QAM symbol. In the third matrix H3, 2 modulation symbols obtained through the mapping of every 2 columns are used as 2 consecutive modulation symbols in a first modulation symbol stream, and 136 modulation symbols obtained through the mapping of the 136 columns are used as 136 consecutive modulation symbols in the first modulation symbol stream, and are used as 136 consecutive DP-16QAM symbols in the first modulation symbol stream.
Every eight codewords in the 16 codewords undergo the bit interleaving, and then are mapped to 136 DP-16QAM symbols. The 16 codewords undergo the bit interleaving, and then are mapped to a total of 272 DP-16QAM symbols, and the 272 DP-16QAM symbols are used as 272 consecutive DP-16QAM symbols in the first modulation symbol stream.
A physical medium attachment (PMA) sublayer of a transmitter processing module processes data from a plurality of synchronous client lanes to obtain n=12 first data streams. The 12 first data streams are separately sent to inner-code encoders for inner-code encoding to obtain 12 second data streams. BCH(176,160) is used for the inner-code encoding. That is, a codeword bit length N=176, an information bit length K=160, and a parity bit length P=16. 160 information bits in each inner-code codeword are from 16 symbols in 16 different outer-code RS codewords.
12 codewords obtained through the inner-code encoding are used as one codeword set, and the codeword set includes m=12 BCH(176,160) codewords. In consideration of DP-16QAM modulation, every L=8 bits are mapped to one DP-16QAM symbol. 264 DP-16QAM symbols may be obtained through bit interleaving and mapping of the 12 BCH(176,160) codewords in each codeword set.
A total of 2112 bits in the foregoing 12 BCH(176,160) codewords are represented by using a first matrix H1 with 12 rows and 176 columns, where each row in the first matrix H1 includes 176 bits in one inner-code BCH(176,160) codeword. The bit interleaving is performed on the first matrix H1 to obtain a third matrix H3 with 12 rows and 176 columns. An interleaving correspondence between the first matrix H1 and the third matrix H3 is: for 0≤i<12,
In the foregoing third matrix H3 with the 12 rows and the 176 columns, each column includes eight bits. In consideration of Lr=4 and Lc=2, a total of eight bits in two columns in every four rows are mapped to one DP-16QAM symbol. In the third matrix H3, 3 modulation symbols obtained through the mapping of every 2 columns are used as 3 consecutive modulation symbols in a first modulation symbol stream, and 264 modulation symbols obtained through the mapping of the 176 columns are used as 264 consecutive DP-16QAM modulation symbols in the first modulation symbol stream.
It should be noted that the foregoing embodiments all describe the operation steps in the data processing method shown in
Implementation 1: an operation procedure in which a transmitter processing module is used in a 1×800G interface scenario.
A physical medium attachment (PMA) sublayer of the transmitter processing module performs first data processing on data from a plurality of synchronous client lanes to obtain the n first data streams, where n is an integer greater than 1. The first data processing may include alignment marker lock (or alignment lock), lane de-skew processing, lane reorder processing, concatenated interleaving (concatenated interleaving) processing, or the like. This embodiment provides specific details of the first data processing.
It should be noted that, both the lane de-skew processing and the lane reorder in
Based on the foregoing diagram of data processing of the transmitter processing module shown in
It should be noted that, an operation procedure of the transmitter processing module may alternatively be as shown in
Implementation 2: an operation procedure in which a transmitter processing module is used in a 2×400G interface scenario.
Based on the foregoing diagram of data processing of the transmitter processing module shown in
It should be noted that, an operation procedure of the transmitter processing module may alternatively be as shown in
Implementation 3: an operation procedure in which a transmitter processing module is used in another 1×800G interface scenario.
Based on the foregoing diagram of data processing of the transmitter processing module shown in
It should be noted that, an operation procedure of the transmitter processing module may alternatively be as shown in
Implementation 4: an operation procedure in which a transmitter processing module is used in concatenated interleaving in a 1×800G or 2×400G interface scenario.
Based on the foregoing implementation 1 or implementation 2, this embodiment provides a concatenated interleaver. The concatenated interleaver performs data disorder processing on 32 PCS lane data streams that undergo lane reorder, to obtain n=32 first data streams. The following describes a specific structure of the concatenated interleaving.
As shown in
row and a c0th column in the 128 RS symbols that are in the 32 rows and the four columns and on which the permutation has not been performed. 32 data streams obtained through the lane permutation are sent to convolution interleavers for interleaving and data disorder.
Implementation 5: another operation procedure in which a transmitter processing module is used in concatenated interleaving in a 1×800G or 2×400G interface scenario.
Based on the foregoing implementation 1 or implementation 2, this embodiment provides another specific implementation of a concatenated interleaver. The concatenated interleaver performs data disorder processing on 32 PCS lane data streams that undergo lane reorder, to obtain n=16 first data streams. The following describes a specific structure of the concatenated interleaving.
Multiplexing processing is performed on every two of the 32 third data streams obtained through the foregoing convolutional interleaving processing, to obtain one first data stream, so that the 16 first data streams are obtained in total. As shown in
Implementation 6: still another operation procedure in which a transmitter processing module is used in concatenated interleaving in a 1×800G interface scenario.
Based on the foregoing implementation 3, this embodiment provides still another specific implementation of a concatenated interleaver. The concatenated interleaver performs data disorder processing on eight lane data streams that undergo lane reorder, to obtain n=8 first data streams. The following describes a specific structure of the concatenated interleaving.
Implementation 7: still another operation procedure in which a transmitter processing module is used in concatenated interleaving in a 1×800G or 2×400G interface scenario.
Based on the foregoing implementation 4, this embodiment provides a diagram of another structure of a convolution interleaver.
Implementation 8: yet another operation procedure in which a transmitter processing module is used in concatenated interleaving in a 1×800G or 2×400G interface scenario.
Based on the foregoing implementation 5, this embodiment provides a diagram of another structure of a convolution interleaver.
Multiplexing processing is performed on every two of 32 third data streams obtained through the foregoing convolutional interleaving processing, to obtain one first data stream, so that 16 first data streams are obtained in total. As shown in
It should be noted that, in some actual application, different bit interleaving and mapping methods may be selected based on different transmission scenarios.
The foregoing describes the data processing method provided in embodiments of this application. The following describes the data processing apparatus provided in embodiments of this application.
It should be understood that the apparatus provided in this application may alternatively be implemented in another manner. For example, division into the units in the foregoing apparatus is merely logical function division and may be other division during actual implementation. For example, a plurality of units or components may be combined or integrated into another system. In addition, functional units in embodiments of this application may be integrated into one processing unit, each may be an independent physical unit, or two or more functional units may be integrated into one processing unit. The integrated unit may be implemented in a form of hardware, or may be implemented in a form of a software functional unit.
It should be noted that, in the data processing method in
401: Separately perform interleaving and encoding processing on every n1 first data streams in n0 first data streams to obtain one second data stream, to obtain a total of n2 second data streams, where n2=n0/n1, and n1 is an integer greater than 0.
In this embodiment, a physical medium attachment (PMA) sublayer of the transmitter processing module performs first data processing on data from a plurality of synchronous client lanes to obtain the n0 first data streams, where n0 is an integer greater than 1. The first data processing may include alignment marker lock (or alignment lock), lane de-skew processing or lane alignment processing, lane reorder processing, symbol multiplexing (symbol mux) processing, or the like. The foregoing n0 first data streams are all outer-code encoded data streams. For example, an RS code may be used for the outer-code encoding, and n outer-code encoded data streams may include a plurality of RS codewords. For example, the outer code is a used KP4 RS(544,514) code, a code length is 544 symbols, and one outer-code symbol includes 10 bits.
The following describes a specific operation of performing the interleaving and encoding processing on the n1 first data streams to obtain one second data stream. The interleaving and encoding processing includes inner-code encoding, circular shift, round-robin reading, and the like.
As shown in (b) in
It should be noted that convolutional interleaving processing is usually further performed before the inner-code encoding, to enable the K information bits to correspond to a large quantity of KP4 outer-code symbols, for example, correspond to K/10 outer-code symbols, and enable the corresponding outer-code symbols to be from a large quantity of outer-code codewords, to implement good overall concatenated-FEC performance. For example, K=120, and the 120 information bits correspond to the 12 KP4 outer-code symbols, and the 12 KP4 outer-code symbols are from 12 outer-code codewords.
It should be noted that, in some scenarios in which a low delay is required, the convolutional interleaving processing is usually not performed before inner-code encoding. The K information bits correspond to the K/10 outer-code symbols, and the corresponding outer-code symbols are from less than K/10 outer-code codewords. For example, K=120, the 120 information bits correspond to the 12 KP4 outer-code symbols, and the 12 KP4 symbols are from four outer-code codewords.
As shown in (b) in
The left circular shift is used as an example. For a first bit set (u0, u1, u2, u3, . . . , uK-2, uK-1) including K bits, the left circular shift is performed by Y bits, to obtain a second bit set (u(φ)% K, u(1+φ)% K, u(2+φ)% K, . . . , u(K−2+φ)% K, u(K-1+φ)% K) that includes the K bits and that is obtained through the shift, where Y % Z represents a remainder obtained by dividing the integer Y by the integer Z. Generally, an offset constraint factor φ of the left circular shift is an integer multiple of 10, and 0≤φ<K.
The right circular shift is used as an example. For a first bit set (u0, u1, u2, u3, . . . , uK-2, UK-1) including K bits, the right circular shift is performed by δ bits, to obtain a second bit set (u(−δ)% K, u(1−δ)% K, u(2−δ)% K, . . . , u(K-2−δ)% K, u(K-1-δ)% K) that includes the K bits and that is obtained through the shift, where Y % Z represents a remainder obtained by dividing the integer Y by the integer Z. Generally, an offset constraint factor δ of the right circular shift is an integer multiple of 10, and 0<δ<K.
It should be noted that, that the second bit set is obtained by performing the left circular shift on the first bit set by the φ bits is equivalent to that the second bit set is obtained by performing the right circular shift on the first bit set by the δ=K−φ bits.
It should be noted that, the offset constraint factor φ of the left circular shift and the offset constraint factor δ of the right circular shift are not fixed, and may be time-varying. Generally, a periodicity of the circular shift is pc In the circular shift, the left circular shift is performed by φi bits on an ith group of first bit set that includes K bits, or the right circular shift is performed by δi bits on an ith group of first bit set that includes K bits, where m is an integer multiple of the integer pc, and 0≤i<pc. Usually, m=pc. Typically, values of any two φ in m offset constraint factors φi (namely, φ0, φ1, . . . , φm-1) are not equal to each other, and values of any two δ in m offset constraint factors δi (namely, δ0, δ1, . . . , δm-1) are not equal to each other.
As shown in (b) in
The second data stream includes a plurality of fourth bit sets, where the fourth bit set that includes the m×N bits is obtained by performing 2-bit round-robin reading on the m third bit sets, the m third bit sets that each include the N bits is obtained by performing the information bit circular shift on the m inner-code codewords, and the m inner-code codewords are obtained by performing the inner-code encoding on the m first bit sets, and the m first bit sets are obtained by obtaining a0 first bit sets from each of the n1 first data streams, where m=n1×a0.
It should be noted that the “round-robin reading”, to be specific, obtaining two bits from each third bit set through round robin to obtain the fourth bit set including the m×N bits is equivalent to the following operation: First, for m second bit sets, two bits are obtained from each second bit set through round robin to obtain m×K bits in total; then, for the parity bit sets in the m inner-code codewords, two bits are obtained from each parity bit set through round robin to obtain m×P bits in total; and the m×K bits obtained from the m second bit sets and the m×P bits obtained from the m parity bit sets are combined to obtain the fourth bit set including the m×N bits.
It should be noted that, in some specific application, the circular shift and the round-robin reading operation may be combined, and bit interleaving is performed, through one step of operation, on the m inner-code codewords including the m×N bits, to obtain the fourth bit set.
As shown in
For the circular shift operation, left circular shift is used as an example. The left circular shift is performed on K information bits (namely, K bits in the ith row in the first bit matrix M1) in the ith (0≤i<m) row in the inner-code codeword matrix Mc by φi bits, to obtain K bits in the ith (0≤i<m) row in the third bit matrix M3, where the non-zero integer φi is an offset constraint factor of circular shift in the ith row. In this case, the third bit matrix M3 and the inner-code codeword matrix Mc satisfy a formula (X-1):
It should be noted that the left circular shift is performed on K information bits in an ith row in a first matrix H1 by φi bits to obtain K bits in the 0th column to a (K−1)th column in an ith row in a second matrix H2. Equivalently, right circular shift is performed on K information bits in the 0th column to a (K−1)th column in the ith row in the first matrix H1 by K−φi bits to obtain the K bits in the 0th column to the (K−1)th column in the ith row in the second matrix H2.
In another example, right circular shift is used. The third bit matrix M3 and the inner-code codeword matrix Mc satisfy a formula (X-2):
Y % Z represents a remainder obtained by dividing the integer Y by the integer Z, and 0≤i<m. Generally, an offset constraint factor δi of the right circular shift is an integer multiple of 10, and 0<δi<K.
It should be noted that, the right circular shift is performed on K information bits in the ith row in the inner-code codeword matrix Mc by δi bits to obtain K bits in the 0th column to a (K−1)th column in the ith row in the third bit matrix M3. Equivalently, left circular shift is performed on the K information bits in the 0th column to the (K−1)th column in the ith row in the third bit matrix M3 by δi bits to obtain K bits in the 0th column to a (K−1)th column in the ith row in the inner-code codeword matrix Mc. In other words, the formula (X-2) may alternatively be written as a formula (X-3):
Circular shift of each row of information bits is performed on the inner-code codeword matrix Mc to obtain the third bit matrix M3.
As shown in
It should be noted that the operation of the reading 2 bits from each row in the third bit matrix M3 through round robin is referred to as m-way codeword interleaving.
The circular shift of each row of information bits is performed on the inner-code codeword matrix Mc to obtain the third bit matrix M3, and then two bits are read from each row through round robin. This is implemented through two steps of operations, or may be performed through one step of operation. The following directly provides a direct mapping relationship between Mc and A.
If the left circular shift is used, with reference to the formula (X-1) and the formula (X-4), there is the following formula (X-5):
If the right circular shift is used, with reference to the formula (X-2) and the formula (X-4), there is the following formula (X-6):
It should be noted that, the circular shift and the round-robin reading are performed in one step, which has advantages such as simple implementation and low complexity.
It should be noted that in the interleaving and encoding processing, the circular shift and the inner-code encoding are performed in parallel, and then the round-robin reading is performed. The following describes this implementation.
As shown in (b) in
The inner-code encoding is performed on each first bit set that includes K bits and that is in the m first bit sets, to obtain a parity bit set that includes P bits, so that m parity bit sets are obtained in total. In the “round-robin reading”, first, for the m second bit sets, two bits are obtained from each second bit set through round robin to obtain m×K bits in total; then, for the m parity bit sets, two bits are obtained from each parity bit set through round robin to obtain m×P bits in total; and the m×K bits obtained from the m second bit sets and the m×P bits obtained from the m parity bit sets are combined to obtain a fourth bit set including m×N bits.
Left circular shift is used as an example. The first bit matrix M1 and the second bit matrix M2 satisfy a formula (X-7):
Y % Z represents a remainder obtained by dividing the integer Y by the integer Z, 0≤i<m, and 0≤j<K. Generally, an offset constraint factor φi of the left circular shift is an integer multiple of 10, and 0<φi<K.
It should be noted that, the left circular shift is performed on K bits in an ith row in the first bit matrix M1 by φi bits to obtain K bits in an ith row in the second bit matrix M2. Equivalently, right circular shift is performed on the K bits in the ith row in the first bit matrix M1 by K− φi bits, to obtain the K bits in the ith row in the second bit matrix M2.
In another example, location transformation is performed through right circular shift. The right circular shift is performed on an ith first bit set in the m first bit sets by δi bits, where the non-zero integer δi is an offset constraint factor of the circular shift corresponding to the ith bit set. The right circular shift satisfies a formula (X-8):
Y % Z represents a remainder obtained by dividing the integer Y by the integer Z, 0<i<m, and 0≤j<K. Generally, an offset constraint factor δi of the right circular shift is an integer multiple of 10, and 0<δi<K.
It should be noted that, the right circular shift is performed on K bits in an ith row in the first bit matrix M1 by δi bits to obtain K bits in an ith row in the second bit matrix M2. Equivalently, left circular shift is performed on the K bits in the ith row in the second bit matrix M2 by δi bits, to obtain the K bits in the ith row in the first bit matrix M1. In other words, the formula (X-8) may alternatively be written as a formula (X-9):
As shown in
It should be noted that, the circular shift and the inner-code encoding are performed in parallel, which has a low-delay advantage.
It should be noted that, in the interleaving and encoding processing, the circular shift is first performed, then the inner-code encoding is performed, and then the round-robin reading is performed. The following describes this implementation.
As shown in (b) in
As shown in (b) in
As shown in (b) in
Left circular shift is used as an example. The first bit matrix M1 and the second bit matrix M2 satisfy a formula (X-10):
It should be noted that, the left circular shift is performed on K bits in an ith row in the first bit matrix M1 by φi bits to obtain K bits in an ith row in the second bit matrix M2. Equivalently, right circular shift is performed on the K bits in the ith row in the first bit matrix M1 by K−φi bits, to obtain the K bits in the ith row in the second bit matrix M2.
In another example, location transformation is performed through right circular shift. The right circular shift is performed on an ith first bit set in the m first bit sets by δi bits, where the non-zero integer δi is an offset constraint factor of the circular shift corresponding to the ith bit set. The right circular shift satisfies a formula (X-11):
It should be noted that, the right circular shift is performed on K bits in an ith row in the first bit matrix M1 by δi bits to obtain K bits in an ith row in the second bit matrix M2. Equivalently, left circular shift is performed on the K bits in the ith row in the second bit matrix M2 by δi bits, to obtain the K bits in the ith row in the first bit matrix M1. In other words, the formula (X-11) may alternatively be written as a formula (X-12):
As shown in
402: Separately map every two bits in the n2 second data streams to one PAM4 symbol, to obtain n2 PAM4 symbol data streams.
For PAM4 modulation, every two bits are mapped to one PAM4 modulation symbol.
The fourth bit set or the array A including the m×N bits is mapped to m×N/2 PAM4 modulation symbols. The two bits mapped to the one PAM4 modulation symbol are from one inner-code codeword, and m×2 bits mapped to m consecutive PAM4 modulation symbols are from m inner-code codewords.
Further, two outer-code symbols from a same RS outer-code codeword in one first data stream are mapped to a plurality of PAM4 symbols in a same PAM4 symbol data stream through the foregoing data processing. An appropriate offset constraint factor φi of the left circular shift or constraint factor δi of the right circular shift offset is selected, so that any two of the plurality of PAM4 symbols are separated by at least two PAM4 symbols in the PAM4 symbol data stream. It should be noted that two adjacent PAM4 symbols in one PAM4 symbol data stream are considered as being separated by one PAM4 symbol.
In some specific application, before the bit mapping is performed on the n2 second data streams, padding bits are periodically inserted into the n2 second data streams, where the padding bit include an alignment marker for alignment and synchronization of a receiver.
In this embodiment of this application, a concatenated-FEC transmission solution is used. That is, the outer-code encoding and the inner-code encoding are sequentially performed on the data streams. On this basis, this application designs an interleaving and encoding processing method, so that both bits in an outer-code codeword and bits in an inner-code codeword are discretely and evenly mapped to modulation symbols. In this way, the concatenated-FEC transmission solution has a strong burst resistance capability. Particularly, a burst error with a small length may be directly corrected through inner-code decoding. The concatenated-FEC transmission solution is widely applicable to transmission scenarios, particularly an actual coherent transmission scenario in which there is colored noise on a channel.
It should be noted that, in the materials of this application, in the round-robin reading, two bits are obtained from each third bit set through round robin, to obtain the fourth bit set including the m×N bits. That is, two bits are obtained from the 0th third bit set, two bits are obtained from the 1st third bit set, . . . , two bits are obtained from an (m−1)th third bit set, and then two bits are obtained from the 0th third bit set until all m×N bits are obtained. In some specific implementations, an order of the round-robin reading may be changed. Correspondingly, corresponding order change only needs to be performed on the offset constraint factor φ0, φ1, . . . , φm-1 of the left circular shift or the offset constraint factor δ0, δ1, . . . , δm-1 of the right circular shift in the circular shift operation.
With reference to some specific embodiments, the following further describes a procedure of the data processing method described in
Embodiment X-1: n0=4, n1=1, and a0=8. A data processing procedure includes convolutional interleaving. For example, a bit set is for representation, and left circular shift is used.
A physical medium attachment (PMA) sublayer of a transmitter processing module performs first data processing on data from a plurality of synchronous client lanes to obtain n0=4 first data streams. The foregoing n0=4 first data streams are all outer-code encoded data streams. Interleaving and encoding processing is performed on every n1=1 first data stream in the n0=4 first data streams to obtain one second data stream, to obtain a total of n2=4 second data streams.
Refer to
The inner-code encoding is performed on every K=120 bit by using the inner-code encoding, and P=8 parity bits are added, to obtain an inner-code codeword including N=128 bits, to obtain m=8 inner-code codewords in total. The K=120 bits are also referred to as an information bit sequence.
In this application, in a circular shift operation, the left circular shift is performed on K=120 information bits in an ith (0≤i<8) inner-code codeword, namely, an ith first bit set, by φi bits, to obtain an ith second bit set, where specific values of eight offset constraint factors {φ0, φ1, φ2, φ3, φ4, φ5, φ6, φ7} of the left circular shift are one of the following value items 1:
It should be understood that, for any item, a fixed offset is added to a value of each of the eight offset constraint factors {φ0, φ1, φ2, φ3, φ4, φ5, φ6, φ7} of the left circular shift. That is, {(φ0+Δ)% K, (φ1+Δ)% K, (φ2+Δ)% K, (φ3+Δ)% K, (φ4+Δ)% K, (φ5+Δ)% K, (φ6+Δ)% K, (φ7+Δ)% K} is still considered as a valid parameter item, where Δ is an integer.
The ith second bit set is combined with P=8 parity bits in the ith inner-code codeword to obtain an ith third bit set that includes N=128 bits.
Refer to
Every two bits in the fourth bit set including the 1024 bits are mapped to one PAM4 modulation symbol, to obtain 512 PAM4 symbols in total. The two bits mapped to the one PAM4 modulation symbol are from one inner-code codeword, and 16 bits mapped to 8 consecutive PAM4 modulation symbols are from 8 inner-code codewords.
For two KP4 outer-code symbols from a same RS outer-code codeword in the n1=1 first data stream, there are a total of 20 bits. The 20 bits undergo the foregoing interleaving and encoding processing, and are mapped to 10 PAM4 symbols in one PAM4 symbol data stream. The offset constraint factor φi of the left circular shift in the value item 1 is used, so that any two of the 10 PAM4 symbols can be separated by at least two PAM4 symbols in the PAM4 symbol data stream. More specifically, when the two of the 10 PAM4 symbols are from different KP4 outer-code codewords, the two of the 10 PAM4 symbols are separated by at least 12 PAM4 symbols in the PAM4 symbol data stream.
According to the interleaving and encoding processing method designed in this embodiment, both bits in an outer-code codeword and bits in an inner-code codeword are discretely and evenly mapped to modulation symbols. In this way, a concatenated-FEC transmission solution has a strong burst resistance capability.
It should be noted that, in this embodiment, n0=4, n1=1, a0=8, and n2=n0/n1=4, which may be applied to an 800GE scenario, where the n2=4 second data streams have a rate about 200G, and are correspondingly carried on four lanes of optical signals for sending. The interleaving and encoding processing used in this embodiment may be applied to a 1.6TE scenario, where n0=8, n1=1, a0=8, and n2=n0/n1=8. In this case, the physical medium attachment (PMA) sublayer of the transmitter processing module performs the first data processing on the data from the plurality of synchronous client lanes to obtain n0=8 first data streams. The foregoing n0=8 first data streams are all outer-code encoded data streams. The interleaving and encoding processing is performed on every n1=1 first data stream in the n0=8 first data streams to obtain one second data stream, to obtain a total of n2=8 second data streams. The n2=8 second data streams (a rate is approximately 200G per second data stream) are correspondingly carried on eight lanes of optical signals for sending.
Embodiment X-2: n0=4, n1=1, and a0=8. A data processing procedure includes convolutional interleaving. For example, a matrix is for representation, and left circular shift is used.
Based on the solution in Embodiment X-1, m=8 first bit set may be represented by using a first bit matrix M1 with 8 rows and 120 columns. Inner-code encoding is performed on K=120 bits in each row in the first bit matrix M1 to obtain one inner code with N=128 bits. 8 inner-code codewords may be represented by using an inner-code codeword matrix Mc with 8 rows and 128 columns, where each row in the inner-code codeword matrix Mc includes N=128 bits in one inner-code codeword. In the inner-code codeword matrix Mc, a total of m×K=960 bits in the 0th column to a (K−1=119)th column correspond to m×K=960 information bits in m=8 inner-code codewords; and in the inner-code codeword matrix, a total of m×P=64 bits in a (K=120)th column to an (N−1=127)th column in the inner-code codeword matrix Mc correspond to m×P=64 parity bits in the m=8 inner-code codewords.
The left circular shift is performed on 120 information bits (namely, 120 bits in an ith row in the first bit matrix M1) in an ith (0≤i<8) row in the inner-code codeword matrix Mc by φi bits, to obtain 120 bits in an ith row in a third bit matrix M3. The following formula is satisfied:
2 bits are read from each row in the third bit matrix M3 through round robin, and all 1024 bits are read through 512 operations in total, to obtain an array A that includes m×N=1024 interleaved bits. A bit in the ith row and a jth column in the third bit matrix M3 is output to a ([j/2]×16+(i×2)+(j %2))th bit in the array A, and the following formula is satisfied:
It should be noted that, circular shift and the round-robin reading that are performed on the inner-code codeword matrix Mc to obtain the array A of the 1024 bits are performed by using two operations, or may be performed by using one operation. The following directly provides a direct correspondence between Mc and A:
Every two bits in the array A including the 1024 bits are mapped to one PAM4 modulation symbol, to obtain 512 PAM4 symbols in total. The two bits mapped to the one PAM4 modulation symbol are from one inner-code codeword, and 16 bits mapped to 8 consecutive PAM4 modulation symbols are from 8 inner-code codewords.
For two KP4 outer-code symbols from a same RS outer-code codeword in the n1=1 first data stream, there are a total of 20 bits. The 20 bits undergo the foregoing interleaving and encoding processing, and are mapped to 10 PAM4 symbols in one PAM4 symbol data stream. The offset constraint factor φi of the left circular shift in the value item 1 is used, so that any two of the 10 PAM4 symbols can be separated by at least two PAM4 symbols in the PAM4 symbol data stream. More specifically, when the two of the 10 PAM4 symbols are from different KP4 outer-code codewords, the two of the 10 PAM4 symbols are separated by at least 12 PAM4 symbols in the PAM4 symbol data stream.
According to the interleaving and encoding processing method designed in this embodiment, both bits in an outer-code codeword and bits in an inner-code codeword are discretely and evenly mapped to modulation symbols. In this way, a concatenated-FEC transmission solution has a strong burst resistance capability.
It should be noted that, in this embodiment, n0=4, n1=1, a0=8, and n2=n0/n1=4, which may be applied to an 800GE scenario, where the n2=4 second data streams have a rate about 200G, and are correspondingly carried on four lanes of optical signals for sending. The interleaving and encoding processing used in this embodiment may be applied to a 1.6TE scenario, where n0=8, n1=1, a0=8, and n2=n0/n1=8. In this case, the physical medium attachment (PMA) sublayer of the transmitter processing module performs the first data processing on the data from the plurality of synchronous client lanes to obtain n0=8 first data streams. The foregoing n0=8 first data streams are all outer-code encoded data streams. The interleaving and encoding processing is performed on every n1=1 first data stream in the n0=8 first data streams to obtain one second data stream, to obtain a total of n2=8 second data streams. The n2=8 second data streams (a rate is approximately 200G per second data stream) are correspondingly carried on eight lanes of optical signals for sending.
Embodiment X-3: n0=4, n1=1, and a0=8. A data processing procedure includes convolutional interleaving. For example, a matrix is for representation, and right circular shift is used.
Based on the solution in Embodiment X-2, the right circular shift is used. The right circular shift is performed on 120 information bits (namely, 120 bits in an ith row in the first bit matrix M1) in an ith (0≤i<8) row in the inner-code codeword matrix Mc by δi bits, to obtain 120 bits in an ith row in a third bit matrix M3. The following formula is satisfied:
It should be noted that a correspondence between M3 and M2 may alternatively be written as the following formula:
It should be noted that, for any one of the value items 2, a fixed offset is added to a value of each of the eight offset constraint factors {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} of the right circular shift. That is, {(δ0+Δ)% K, (δ1+Δ)% K, (δ2+Δ)% K, (δ3+Δ)% K, (δ4+Δ)% K, (δ5+Δ)% K, (δ6+) % K, (δ7+Δ)% K} is still considered as a valid parameter item, where Δ is an integer.
2 bits are read from each row in the third bit matrix M3 through round robin, and all 1024 bits are read through 512 operations in total, to obtain an array A that includes m×N=1024 interleaved bits. A bit in the ith row and a jth column in the third bit matrix M3 is output to a ([j/2]×16+(i×2)+(j %2))th bit in the array A, and the following formula is satisfied:
It should be noted that, circular shift and the round-robin reading that are performed on the inner-code codeword matrix Mc to obtain the array A of the 1024 bits are performed by using two operations, or may be performed by using one operation. The following directly provides a direct correspondence between Mc and A:
Every two bits in the array A including the 1024 bits are mapped to one PAM4 modulation symbol, to obtain 512 PAM4 symbols in total. The two bits mapped to the one PAM4 modulation symbol are from one inner-code codeword, and 16 bits mapped to 8 consecutive PAM4 modulation symbols are from 8 inner-code codewords.
For two KP4 outer-code symbols from a same RS outer-code codeword in the n1=1 first data stream, there are a total of 20 bits. The 20 bits undergo the foregoing interleaving and encoding processing, and are mapped to 10 PAM4 symbols in one PAM4 symbol data stream. The offset constraint factor δi of the right circular shift in the value item 2 is used, so that any two of the 10 PAM4 symbols can be separated by at least two PAM4 symbols in the PAM4 symbol data stream. More specifically, when the two of the 10 PAM4 symbols are from different KP4 outer-code codewords, the two of the 10 PAM4 symbols are separated by at least 12 PAM4 symbols in the PAM4 symbol data stream.
According to the interleaving and encoding processing method designed in this embodiment, both bits in an outer-code codeword and bits in an inner-code codeword are discretely and evenly mapped to modulation symbols. In this way, a concatenated-FEC transmission solution has a strong burst resistance capability.
It should be noted that, in this embodiment, n0=4, n1=1, a0=8, and n2=n0/n1=4, which may be applied to an 800GE scenario, where the n2=4 second data streams have a rate about 200G, and are correspondingly carried on four lanes of optical signals for sending. The interleaving and encoding processing used in this embodiment may be applied to a 1.6TE scenario, where n0=8, n1=1, a0=8, and n2=n0/n1=8. In this case, the physical medium attachment (PMA) sublayer of the transmitter processing module performs the first data processing on the data from the plurality of synchronous client lanes to obtain n0=8 first data streams. The foregoing n0=8 first data streams are all outer-code encoded data streams. The interleaving and encoding processing is performed on every n1=1 first data stream in the n0=8 first data streams to obtain one second data stream, to obtain a total of n2=8 second data streams. The n2=8 second data streams (a rate is approximately 200G per second data stream) are correspondingly carried on eight lanes of optical signals for sending.
Embodiment X-4: n0=4, n1=1, and a0=8. A data processing procedure does not include convolutional interleaving. For example, a bit set is for representation, and left circular shift is used.
Based on Embodiment X-1, a convolutional interleaving operation is not performed (is bypassed), which has a low-delay advantage and satisfy an application scenario with a high delay requirement. A physical medium attachment (PMA) sublayer of a transmitter processing module performs first data processing on data from a plurality of synchronous client lanes to obtain n0=4 first data streams. The foregoing n0=4 first data streams are all outer-code encoded data streams. The interleaving and encoding processing is performed on every n1=1 first data stream in the n0=4 first data streams to obtain one second data stream, to obtain a total of n2=4 second data streams.
Refer to
The inner-code encoding is performed on every K=120 bit by using the inner-code encoding, and P=8 parity bits are added, to obtain an inner-code codeword including N=128 bits, to obtain m=8 inner-code codewords in total. The K=120 bits are also referred to as an information bit sequence.
In this application, in a circular shift operation, the left circular shift is performed on K=120 information bits in an ith (0≤i<8) inner-code codeword, namely, an ith first bit set, by φi bits, to obtain an ith second bit set, where specific values of eight offset constraint factors {φ0, φ1, φ2, φ3, φ4, φ5, φ6, φ7} of the left circular shift are one of the following value items 3:
It should be understood that, for any item, a fixed offset is added to a value of each of the eight offset constraint factors {φ0, φ1, φ2, φ3, φ4, φ5, φ6, φ7} of the left circular shift. That is, {(φ0+Δ)% K, (φ1+Δ)% K, (φ2+Δ)% K, (φ3+Δ)% K, (φ4+Δ)% K, (φ5+Δ)% K, (φ6+Δ)% K, (φ7+Δ)% K} is still considered as a valid parameter item, where Δ is an integer.
The ith second bit set is combined with P=8 parity bits in the ith inner-code codeword to obtain an ith third bit set that includes N=128 bits.
Refer to
Every two bits in the fourth bit set including the 1024 bits are mapped to one PAM4 modulation symbol, to obtain 512 PAM4 symbols in total. The two bits mapped to the one PAM4 modulation symbol are from one inner-code codeword, and 16 bits mapped to 8 consecutive PAM4 modulation symbols are from 8 inner-code codewords.
For two KP4 outer-code symbols from a same RS outer-code codeword in the n1=1 first data stream, there are a total of 20 bits. The 20 bits undergo the foregoing interleaving and encoding processing, and are mapped to 10 PAM4 symbols in one PAM4 symbol data stream. The offset constraint factor φi of the left circular shift in the value item 3 is used, so that any two of the 10 PAM4 symbols can be separated by at least two PAM4 symbols in the PAM4 symbol data stream.
According to the bit interleaving and mapping method designed in this embodiment, when a low delay is ensured, bits in an outer-code codeword and bits in an inner-code codeword are discretely and evenly mapped to modulation symbols. In this way, a concatenated-FEC transmission solution has a good burst resistance capability.
It should be noted that, in this embodiment, n0=4, n1=1, a0=8, and n2=n0/n1=4, which may be applied to an 800GE scenario, where the n2=4 second data streams have a rate about 200G, and are correspondingly carried on four lanes of optical signals for sending. The interleaving and encoding processing used in this embodiment may be applied to a 1.6TE scenario, where n0=8, n1=1, a0=8, and n2=n0/n1=8. In this case, the physical medium attachment (PMA) sublayer of the transmitter processing module performs the first data processing on the data from the plurality of synchronous client lanes to obtain n0=8 first data streams. The foregoing n0=8 first data streams are all outer-code encoded data streams. The interleaving and encoding processing is performed on every n1=1 first data stream in the n0=8 first data streams to obtain one second data stream, to obtain a total of n2=8 second data streams. The n2=8 second data streams (a rate is approximately 200G per second data stream) are correspondingly carried on eight lanes of optical signals for sending.
Embodiment X-5: n0=4, n1=1, and a0=8. In a data processing procedure, convolutional interleaving is not performed. For example, a matrix is for representation, and left circular shift is used.
Based on Embodiment X-4, m=8 bit sets may be represented by using a matrix. Inner-code encoding is performed on K=120 bits in each row in a first bit matrix M1 to obtain an inner-code codeword matrix Mc. Left circular shift is performed on 120 information bits (namely, 120 bits in an ith row in the first bit matrix M1) in an ith (0≤i<8) row in the inner-code codeword matrix Mc by φi bits, to obtain 120 bits in an ith row in a third bit matrix M3. The following formula is satisfied:
2 bits are read from each row in the third bit matrix M3 through round robin, and all 1024 bits are read through 512 operations in total, to obtain an array A that includes m×N=1024 interleaved bits.
Every two bits in the array A including the 1024 bits are mapped to one PAM4 modulation symbol, to obtain 512 PAM4 symbols in total. The two bits mapped to the one PAM4 modulation symbol are from one inner-code codeword, and 16 bits mapped to 8 consecutive PAM4 modulation symbols are from 8 inner-code codewords.
For two KP4 outer-code symbols from a same RS outer-code codeword in the n1=1 first data stream, there are a total of 20 bits. The 20 bits undergo the foregoing interleaving and encoding processing, and are mapped to 10 PAM4 symbols in one PAM4 symbol data stream. The offset constraint factor φi of the left circular shift in the value item 3 is used, so that any two of the 10 PAM4 symbols can be separated by at least two PAM4 symbols in the PAM4 symbol data stream.
According to the bit interleaving and mapping method designed in this embodiment, when a low delay is ensured, bits in an outer-code codeword and bits in an inner-code codeword are discretely and evenly mapped to modulation symbols. In this way, a concatenated-FEC transmission solution has a good burst resistance capability.
It should be noted that, in this embodiment, n0=4, n1=1, a0=8, and n2=n0/n1=4, which may be applied to an 800GE scenario, where the n2=4 second data streams have a rate about 200G, and are correspondingly carried on four lanes of optical signals for sending. The interleaving and encoding processing used in this embodiment may be applied to a 1.6TE scenario, where n0=8, n1=1, a0=8, and n2=n0/n1=8. In this case, the physical medium attachment (PMA) sublayer of the transmitter processing module performs the first data processing on the data from the plurality of synchronous client lanes to obtain n0=8 first data streams. The foregoing n0=8 first data streams are all outer-code encoded data streams. The interleaving and encoding processing is performed on every n1=1 first data stream in the n0=8 first data streams to obtain one second data stream, to obtain a total of n2=8 second data streams. The n2=8 second data streams (a rate is approximately 200G per second data stream) are correspondingly carried on eight lanes of optical signals for sending.
Embodiment X-6: n0=4, n1=1, and a0=8. In a data processing procedure, convolutional interleaving is not performed. For example, a matrix is for representation, and right circular shift is used.
Based on Embodiment X-5, the right circular shift is used. The right circular shift is performed on 120 information bits (namely, 120 bits in an ith row in the first bit matrix M1) in an ith (0≤i<8) row in the inner-code codeword matrix Mc by δi bits, to obtain 120 bits in an ith row in a third bit matrix M3. The following formula is satisfied:
It should be understood that, for any item, a fixed offset is added to a value of each of the eight offset constraint factors {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} of the right circular shift. That is, {(δ0+Δ)% K, (δ1+Δ)% K, (δ2+Δ)% K, (δ3+Δ)% K, (δ4+Δ)% K, (δ5+Δ)% K, (δ6+Δ)% K, (δ7+Δ)% K} is still considered as a valid parameter item, where Δ is an integer.
It should be noted that a correspondence between M3 and Mc may alternatively be written as the following:
2 bits are read from each row in the third bit matrix M3 through round robin, and all 1024 bits are read through 512 operations in total, to obtain an array A that includes m×N=1024 interleaved bits.
Every two bits in the array A including the 1024 bits are mapped to one PAM4 modulation symbol, to obtain 512 PAM4 symbols in total. The two bits mapped to the one PAM4 modulation symbol are from one inner-code codeword, and 16 bits mapped to 8 consecutive PAM4 modulation symbols are from 8 inner-code codewords.
For two KP4 outer-code symbols from a same RS outer-code codeword in the n1=1 first data stream, there are a total of 20 bits. The 20 bits undergo the foregoing interleaving and encoding processing, and are mapped to 10 PAM4 symbols in one PAM4 symbol data stream. The offset constraint factor δi of the right circular shift in the value item 4 is used, so that any two of the 10 PAM4 symbols can be separated by at least two PAM4 symbols in the PAM4 symbol data stream.
According to the bit interleaving and mapping method designed in this embodiment, when a low delay is ensured, bits in an outer-code codeword and bits in an inner-code codeword are discretely and evenly mapped to modulation symbols. In this way, a concatenated-FEC transmission solution has a good burst resistance capability.
It should be noted that, in this embodiment, n0=4, n1=1, a0=8, and n2=n0/n1=4, which may be applied to an 800GE scenario, where the n2=4 second data streams have a rate about 200G, and are correspondingly carried on four lanes of optical signals for sending. The interleaving and encoding processing used in this embodiment may be applied to a 1.6TE scenario, where n0=8, n1=1, a0=8, and n2=n0/n1=8. In this case, the physical medium attachment (PMA) sublayer of the transmitter processing module performs the first data processing on the data from the plurality of synchronous client lanes to obtain n0=8 first data streams. The foregoing n0=8 first data streams are all outer-code encoded data streams. The interleaving and encoding processing is performed on every n1=1 first data stream in the n0=8 first data streams to obtain one second data stream, to obtain a total of n2=8 second data streams. The n2=8 second data streams (a rate is approximately 200G per second data stream) are correspondingly carried on eight lanes of optical signals for sending.
It should be noted that, in Embodiment X-1 to Embodiment X-6, the inner-code encoding is first performed, and then the circular shift is performed. The inner-code encoding and the circular shift may alternatively be performed in parallel, as shown in
Embodiment X-7: n0=4, n1=1, and a0=8. A data processing procedure includes convolutional interleaving. For example, a matrix is for representation, and left circular shift is used. Inner-code encoding and the circular shift are performed in parallel.
Based on the solution in Embodiment X-3, the inner-code encoding and the circular shift in this embodiment are performed in parallel.
The inner-code encoding is performed on K=120 bits in each row in the first bit matrix M1 to obtain one P=8 parity bit, to obtain a parity bit matrix Mp.
2 bits are read from each row in the third bit matrix M3 through round robin, and all 1024 bits are read through 512 operations in total, to obtain an array A that includes m×N=1024 interleaved bits. A bit in the ith row and a jth column in the third bit matrix M3 is output to an (i×[j/2]×16+(i×2)+(j %2))th bit in the array A, and the following formula is satisfied:
It should be noted that, circular shift and the round-robin reading that are performed on the inner-code codeword matrix Mc to obtain the array A of the 1024 bits are performed by using two operations, or may be performed by using one operation. The following directly provides a direct correspondence between Mc and A:
Every two bits in the array A including the 1024 bits are mapped to one PAM4 modulation symbol, to obtain 512 PAM4 symbols in total. The two bits mapped to the one PAM4 modulation symbol are from one inner-code codeword, and 16 bits mapped to 8 consecutive PAM4 modulation symbols are from 8 inner-code codewords.
For two KP4 outer-code symbols from a same RS outer-code codeword in the n1=1 first data stream, there are a total of 20 bits. The 20 bits undergo the foregoing interleaving and encoding processing, and are mapped to 10 PAM4 symbols in one PAM4 symbol data stream. The offset constraint factor φi of the left circular shift is used, so that any two of the 10 PAM4 symbols can be separated by at least two PAM4 symbols in the PAM4 symbol data stream.
According to the interleaving and encoding processing method designed in this embodiment, both bits in an outer-code codeword and bits in an inner-code codeword are discretely and evenly mapped to modulation symbols. In this way, a concatenated-FEC transmission solution has a strong burst resistance capability.
It should be noted that, in this embodiment, n0=4, n1=1, a0=8, and n2=n0/n1=4, which may be applied to an 800GE scenario, where the n2=4 second data streams have a rate about 200G, and are correspondingly carried on four lanes of optical signals for sending. The interleaving and encoding processing used in this embodiment may be applied to a 1.6TE scenario, where n0=8, n1=1, a0=8, and n2=n0/n1=8. In this case, the physical medium attachment (PMA) sublayer of the transmitter processing module performs the first data processing on the data from the plurality of synchronous client lanes to obtain n0=8 first data streams. The foregoing n0=8 first data streams are all outer-code encoded data streams. The interleaving and encoding processing is performed on every n1=1 first data stream in the n0=8 first data streams to obtain one second data stream, to obtain a total of n2=8 second data streams. The n2=8 second data streams (a rate is approximately 200G per second data stream) are correspondingly carried on eight lanes of optical signals for sending.
The following Embodiment X-8 to Embodiment X-11 describe the data processing procedures shown in
Embodiment X-8: n0=4, n1=1, and a0=8. A data processing procedure includes convolutional interleaving. For example, a bit set is for representation, and left circular shift is used.
A physical medium attachment (PMA) sublayer of a transmitter processing module performs first data processing on data from a plurality of synchronous client lanes to obtain n0=4 first data streams. The foregoing n0=4 first data streams are all outer-code encoded data streams. The interleaving and encoding processing is performed on every n1=1 first data stream in the n0=4 first data streams to obtain one second data stream, to obtain a total of n2=4 second data streams.
Refer to
In this application, in a circular shift operation, the left circular shift is performed on an ith (0≤i<8) first bit set by φi bits, to obtain an ith second bit set, where specific values of eight offset constraint factors {φ0, φ1, φ2, φ3, φ4, φ5, φ6, φ7} of the left circular shift are one of value items 1:
The inner-code encoding is performed on K=120 bits in the ith second bit set, and P=8 parity bits are added to obtain an ith inner-code codeword including N=128 bits, to obtain m=8 inner-code codewords in total. The K=120 bits are also referred to as an information bit sequence.
Refer to
Every two bits in the fourth bit set including the 1024 bits are mapped to one PAM4 modulation symbol, to obtain 512 PAM4 symbols in total. The two bits mapped to the one PAM4 modulation symbol are from one inner-code codeword, and 16 bits mapped to 8 consecutive PAM4 modulation symbols are from 8 inner-code codewords.
For two KP4 outer-code symbols from a same RS outer-code codeword in the n1=1 first data stream, there are a total of 20 bits. The 20 bits undergo the foregoing interleaving and encoding processing, and are mapped to 10 PAM4 symbols in one PAM4 symbol data stream. The offset constraint factor φi of the left circular shift is used, so that any two of the 10 PAM4 symbols can be separated by at least two PAM4 symbols in the PAM4 symbol data stream.
According to the interleaving and encoding processing method designed in this embodiment, both bits in an outer-code codeword and bits in an inner-code codeword are discretely and evenly mapped to modulation symbols. In this way, a concatenated-FEC transmission solution has a strong burst resistance capability.
It should be noted that, in this embodiment, n0=4, n1=1, a0=8, and n2=n0/n1=4, which may be applied to an 800GE scenario, where the n2=4 second data streams have a rate about 200G, and are correspondingly carried on four lanes of optical signals for sending. The interleaving and encoding processing used in this embodiment may be applied to a 1.6TE scenario, where n0=8, n1=1, a0=8, and n2=n0/n1=8. In this case, the physical medium attachment (PMA) sublayer of the transmitter processing module performs the first data processing on the data from the plurality of synchronous client lanes to obtain n0=8 first data streams. The foregoing n0=8 first data streams are all outer-code encoded data streams. The interleaving and encoding processing is performed on every n1=1 first data stream in the n0=8 first data streams to obtain one second data stream, to obtain a total of n2=8 second data streams. The n2=8 second data streams (a rate is approximately 200G per second data stream) are correspondingly carried on eight lanes of optical signals for sending.
Embodiment X-9: n0=4, n1=1, and a0=8. A data processing procedure includes convolutional interleaving. For example, a matrix is for representation, and left circular shift is used.
Based on the solution in Embodiment X-8, m=8 first bit set may be represented by using a first bit matrix M1 with 8 rows and 120 columns. The left circular shift is performed on 120 information bits in an ith (0≤i<8) row in the first bit matrix M1 by φi bits, to obtain 120 bits in an ith row in a second bit matrix M2. The following formula is satisfied:
Y % Z represents a remainder obtained by dividing the integer Y by the integer Z, 0≤i<8, and 0≤j<120. Specific values of eight offset constraint factors {φ0, φ1, φ2, φ3, φ4, φ5, φ6, φ7} of the left circular shift are one of value items 1.
2 bits are read from each row in the inner-code codeword matrix Mc through round robin, and all 1024 bits are read through 512 operations in total, to obtain an array A that includes m×N=1024 interleaved bits. A bit in an ith row and a jth column in the inner-code codeword matrix Mc is output to an (i×[j/2]×16+(i×2)+(j %2))th bit in the array A, and the following formula is satisfied:
Every two bits in the array A including the 1024 bits are mapped to one PAM4 modulation symbol, to obtain 512 PAM4 symbols in total. The two bits mapped to the one PAM4 modulation symbol are from one inner-code codeword, and 16 bits mapped to 8 consecutive PAM4 modulation symbols are from 8 inner-code codewords.
For two KP4 outer-code symbols from a same RS outer-code codeword in the n1=1 first data stream, there are a total of 20 bits. The 20 bits undergo the foregoing interleaving and encoding processing, and are mapped to 10 PAM4 symbols in one PAM4 symbol data stream. The offset constraint factor φi of the left circular shift is used, so that any two of the 10 PAM4 symbols can be separated by at least two PAM4 symbols in the PAM4 symbol data stream.
According to the interleaving and encoding processing method designed in this embodiment, both bits in an outer-code codeword and bits in an inner-code codeword are discretely and evenly mapped to modulation symbols. In this way, a concatenated-FEC transmission solution has a strong burst resistance capability.
It should be noted that, in this embodiment, n0=4, n1=1, a0=8, and n2=n0/n1=4, which may be applied to an 800GE scenario, where the n2=4 second data streams have a rate about 200G, and are correspondingly carried on four lanes of optical signals for sending. The interleaving and encoding processing used in this embodiment may be applied to a 1.6TE scenario, where n0=8, n1=1, a0=8, and n2=n0/n1=8. In this case, the physical medium attachment (PMA) sublayer of the transmitter processing module performs the first data processing on the data from the plurality of synchronous client lanes to obtain n0=8 first data streams. The foregoing n0=8 first data streams are all outer-code encoded data streams. The interleaving and encoding processing is performed on every n1=1 first data stream in the n0=8 first data streams to obtain one second data stream, to obtain a total of n2=8 second data streams. The n2=8 second data streams (a rate is approximately 200G per second data stream) are correspondingly carried on eight lanes of optical signals for sending.
Embodiment X-10: n0=8, n1=2, and a0=4. A data processing procedure includes convolutional interleaving. For example, a bit set is for representation, and right circular shift is used.
A physical medium attachment (PMA) sublayer of a transmitter processing module performs first data processing on data from a plurality of synchronous client lanes to obtain n0=8 first data streams. The foregoing n0=8 first data streams are all outer-code encoded data streams. The interleaving and encoding processing is performed on every n1=2 first data stream in the n0=8 first data streams to obtain one second data stream, to obtain a total of n2=4 second data streams.
Refer to
In this application, in a circular shift operation, the right circular shift is performed on an ith (0≤i<8) first bit set by δi bits, to obtain an ith second bit set, where specific values of eight offset constraint factors {δ0, δ1, δ2, δ3, δ4, δ5, δ6, δ7} of the right circular shift are one of value items 2:
The inner-code encoding is performed on K=120 bits in the ith second bit set, and P=8 parity bits are added to obtain an ith inner-code codeword including N=128 bits, to obtain m=8 inner-code codewords in total. The K=120 bits are also referred to as an information bit sequence.
Refer to
It should be noted that, in the eight third bit sets, the 0th third bit set, the 1st third bit set, the 2nd third bit set, and the 3rd third bit set are from a same data stream, and the 4th third bit set, the 5th third bit set, the 6th third bit set, and the 7th third bit set are from the other data stream. That is, in the round-robin read operation, eight bits are first obtained from one data stream, and then eight bits are obtained from one data stream.
Every two bits in the fourth bit set including the 1024 bits are mapped to one PAM4 modulation symbol, to obtain 512 PAM4 symbols in total. The two bits mapped to the one PAM4 modulation symbol are from one inner-code codeword, and 16 bits mapped to 8 consecutive PAM4 modulation symbols are from 8 inner-code codewords.
For two KP4 outer-code symbols from a same RS outer-code codeword in the n1=1 first data stream, there are a total of 20 bits. The 20 bits undergo the foregoing interleaving and encoding processing, and are mapped to 10 PAM4 symbols in one PAM4 symbol data stream. The offset constraint factor S; of the right circular shift is used, so that any two of the 10 PAM4 symbols can be separated by at least two PAM4 symbols in the PAM4 symbol data stream.
According to the interleaving and encoding processing method designed in this embodiment, both bits in an outer-code codeword and bits in an inner-code codeword are discretely and evenly mapped to modulation symbols. In this way, a concatenated-FEC transmission solution has a strong burst resistance capability.
It should be noted that, in this embodiment, n0=8, n1=2, a0=4, and n2=n0/n1=4, which may be applied to an 800GE scenario, where the n2=4 second data streams have a rate about 200G, and are correspondingly carried on four lanes of optical signals for sending. The interleaving and encoding processing used in this embodiment may be applied to a 1.6TE scenario, where n0=16, n1=2, a0=4, and n2=n0/n1=8. In this case, the physical medium attachment (PMA) sublayer of the transmitter processing module performs the first data processing on the data from the plurality of synchronous client lanes to obtain n0=16 first data streams. The foregoing n0=16 first data streams are all outer-code encoded data streams. The interleaving and encoding processing is performed on every n1=2 first data stream in the n0=16 first data streams to obtain one second data stream, to obtain a total of n2=8 second data streams. The n2=8 second data streams (a rate is approximately 200G per second data stream) are correspondingly carried on eight lanes of optical signals for sending.
It should be noted that, in some other embodiments, four consecutive first bit sets in one first data stream are referred to as the 0th first bit set, the 2nd first bit set, the 4th first bit set, and the 6th first bit set. Four consecutive first bit sets in another first data stream are referred to as the 1st first bit set, the 3rd first bit set, the 5th first bit set, and the 7th first bit set. For m=8 third bit sets output after the circular shift, in the round-robin reading, two bits are obtained from the 0th third bit set, two bits are obtained from the 1st third bit set, . . . , two bits are obtained from the 7th third bit set, and then two bits are obtained from the 0th third bit set until all 1024 bits are obtained. Correspondingly, in the eight third bit sets, the 0th first bit set, the 2nd first bit set, the 4th first bit set, and the 6th third bit set are from a same data stream, and the 1st third bit set, the 3rd third bit set, the 5th third bit set, and the 7th third bit set are from the other data stream. That is, in the round-robin read operation, two bits are first obtained from one data stream, and then two bits are obtained from one data stream.
It should be noted that, in some other embodiments, four consecutive first bit sets in one first data stream are referred to as the 0th first bit set, the 1st first bit set, the 4th first bit set, and the 5th first bit set. Four consecutive first bit sets in another first data stream are referred to as the 2nd first bit set, the 3rd first bit set, the 6th first bit set, and the 7th first bit set. For m=8 third bit sets output after the circular shift, in the round-robin reading, two bits are obtained from the 0th third bit set, two bits are obtained from the 1st third bit set, . . . , two bits are obtained from the 7th third bit set, and then two bits are obtained from the 0th third bit set until all 1024 bits are obtained. Correspondingly, in the eight third bit sets, the 0th third bit set, the 1st third bit set, the 4th third bit set, and the 5th third bit set are from a same data stream, and the 2nd third bit set, the 3rd third bit set, the 6th third bit set, and the 7th third bit set are from the other data stream. That is, in the round-robin read operation, four bits are first obtained from one data stream, and then four bits are obtained from one data stream.
It should be understood that the apparatus provided in this application may alternatively be implemented in another manner. For example, division into the units in the foregoing apparatus is merely logical function division and may be other division during actual implementation. For example, a plurality of units or components may be combined or integrated into another system. In addition, functional units in embodiments of this application may be integrated into one processing unit, each may be an independent physical unit, or two or more functional units may be integrated into one processing unit. The integrated unit may be implemented in a form of hardware, or may be implemented in a form of a software functional unit.
It should be noted that the processor shown in
It may be clearly understood by a person skilled in the art that, for the purpose of convenient and brief description, for a detailed working process of the foregoing system, apparatus, and unit, refer to a corresponding process in the foregoing method embodiments. Details are not described herein again.
A person of ordinary skill in the art may understand that all or some of the steps in the foregoing embodiments may be implemented through hardware or a program instructing related hardware. The program may be stored in a computer-readable storage medium. The storage medium mentioned above may be a read-only memory, a random access memory, or the like. Whether the functions are performed by hardware or software depends on particular applications and design constraint conditions of the technical solutions. A person skilled in the art may use different methods to implement the functions for each particular application, but it should not be considered that this implementation goes beyond the scope of this application.
When software is used to implement the functions, all or some of the method steps described in the foregoing embodiments may be implemented in a form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the procedure or functions according to embodiments of this application are all or partially generated. The computer may be a general-purpose computer, a dedicated computer, a computer network, or another programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or may be transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired (for example, a coaxial cable, an optical fiber, or a digital subscriber line (DSL)) or wireless (for example, infrared, radio, or microwave) manner. The computer-readable storage medium may be any usable medium accessible by the computer, or a data storage device, for example, a server or a data center, integrating one or more usable media. The usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, or a magnetic tape), an optical medium (for example, a DVD), a semiconductor medium (for example, a solid-state drive Solid State Disk (SSD)), or the like.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202210727137.1 | Jun 2022 | CN | national |
| 202210867882.6 | Jul 2022 | CN | national |
| 202310382561.1 | Apr 2023 | CN | national |
This application is a continuation of International Application No. PCT/CN2023/098219, filed on Jun. 5, 2023, which claims priorities to Chinese Patent Application No. 202210727137.1, filed on Jun. 24, 2022 and Chinese Patent Application No. 202210867882.6, filed on Jul. 22, 2022 and Chinese Patent Application No. 202310382561.1, filed on Apr. 4, 2023. All of the aforementioned patent applications are hereby incorporated by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2023/098219 | Jun 2023 | WO |
| Child | 18999679 | US |
