Data processing system and method

Abstract

Disclosed is a data processing system and method. The data processing method determines the number of static registers and the number of rotating registers for assigning a register to a variable contained in a certain program, assigns the register to the variable based on the number of the static registers and the number of the rotating registers, and compiles the program. Further, the method stores in the special register a value corresponding to the number of the rotating registers in the compiling operation, and obtains a physical address from a logical address of the register based on the value. Accordingly, the present invention provides an aspect of efficiently using register files by dynamically controlling the number of rotating registers and the number of static registers for a software pipelined loop, and has an effect capable of reducing the generations of spill/fill codes unnecessary during program execution to a minimum.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above aspects and features of the present invention will be more apparent by describing certain exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

FIGS. 1A and 1B are views for explaining a rotating register file supporting a software pipelining method;

FIG. 2 is a view for showing a conventional loop accelerator;

FIG. 3 is a block diagram for showing a data processing system according to an exemplary embodiment of the present invention;

FIG. 4 is a view for showing in detail an address translating unit and a register file of FIG. 3 according to an exemplary embodiment of the present invention; and

FIG. 5 is a flowchart for showing a data processing method according to an exemplary embodiment of the present invention.

Claims

1. A data processing method, comprising: determining a number of static registers and a number of rotating registers for assigning a register to a variable contained in a certain program, assigning the register to the variable based on the number of the static registers and the number of the rotating registers, and compiling the program; andexecuting the compiled program.

2. The method as claimed in claim 1, wherein the number of the static registers and the number of the rotating registers are determined such that a number of spill/fill codes to be generated is minimized during the executing of the compiled program.

3. The method as claimed in claim 1, wherein the number of the static registers and the number of the rotating registers are determined for every loop contained in the program.

4. The method as claimed in claim 1, wherein the executing of the compiled program comprises obtaining a physical address for the register from a logical address of the register based on at least one of the number of the static registers and the number of the rotating registers.

5. The method as claimed in claim 1, further comprising adding to the program, prior to the compiling, an instruction which instructs storing in a special register a value corresponding to the number of the rotating registers.

6. The method as claimed in claim 5, wherein the executing of the compiled program comprises obtaining a physical address for the register from a logical address of the register based on the value stored in the special register.

7. The method as claimed in claim 6, further comprising accessing the register corresponding to the obtained physical address.

8. The method as claimed in claim 6, wherein the obtaining of the physical address for the register comprises: comparing the logical address with the value stored in the special register; anddetermining the logical address as the physical address if the logical address is not smaller than the value stored in the special register as a result of the comparing.

9. The method as claimed in claim 8, wherein, if the logical address is smaller than the value stored in the special register as a result of the comparing, the physical address is determined in an equation as below: PR={(LR+RRB)%R}, where PR denotes the physical address of the register, LR the logical address of the register, RRB a value corresponding to the number of current iteration times stored in a base register, R the value stored in the special register, and % a modulus operator.

10. The method as claimed in claim 1, further comprising adding to the program, prior to the compiling, an instruction which instructs storing in a special register a value corresponding to the number of the static registers.

11. The method as claimed in claim 10, wherein the executing of the compiled program comprises obtaining a physical address for the register from a logical address of the register based on the value stored in the special register.

12. The method as claimed in claim 11, further comprising accessing the register corresponding to the obtained physical address.

13. The method as claimed in claim 11, wherein the obtaining of the physical address for the register comprises: comparing the logical address with the value stored in the special register; anddetermining the logical address as the physical address if the logical address is smaller than the value stored in the special register as a result of the comparing.

14. The method as claimed in claim 13, wherein, if the logical address is not smaller than the value stored in the special register as a result of the comparing, the physical address is determined in an equation as below: PR={(LR+RRB−S)%(N−S)}+S, where PR denotes the physical address of the register, LR the logical address of the register, RRB a value corresponding to the number of current iteration times stored in a base register, R the value stored in the special register, S the number of the static registers, N a sum of the R and the S, and % a modulus operator.

15. A data processing system comprising: a compiler which determines a number of static registers and a number of rotating registers for assigning a register to a variable contained in a certain program, assigns the register to the variable based on the number of the static registers and the number of the rotating registers, and compiles the program; anda processor which comprises a register file comprising at least one of the static registers and the rotating registers, and executes the compiled program.

16. The system as claimed in claim 15, wherein the number of the static registers and the number of the rotating registers are determined such that a number of spill/fill codes to be generated is minimized during the executing of the compiled program.

17. The system as claimed in claim 15, wherein the number of the static registers and the number of the rotating registers are determined for every loop contained in the program.

18. The systems as claimed in claim 15, wherein the processor comprises an address translating unit which obtains a physical address for the register from a logical address of the register based on at least one of the number of the static registers and the number of the rotating registers.

19. The system as claimed in claim 15, wherein the compiler further adds to the program an instruction for storing in the processor a value corresponding to the number of the rotating registers, and compiles the program.

20. The system as claimed in claim 19, wherein the processor comprises: a special register which stores the value corresponding to the number of the rotating registers;an execution unit which executes the instruction for the storing in the special register the value corresponding to the number of the rotating registers; andan address translating unit which obtains a physical address for the register from a logical address of the register based on the value stored in the special register.

21. The system as claimed in claim 20, wherein the address translating unit comprises: an arithmetic unit which receives a value RRB corresponding to the number of current iteration times stored in a base register, LR the logical address of the register, and R the value stored in the special register, and outputs PR, a value calculated in an equation: PR={(LR+RRB) % R}, where % denotes a modulus operator;a comparing unit which compares the logical address with the value stored in the special register; anda selecting unit which selectively outputs as the physical address for the register one of PR, the value outputted from the arithmetic unit, and the logical address of the register according to a result of the comparing of the comparing unit.

22. The system as claimed in claim 21, wherein the selecting unit outputs the logical address as the physical address for the register if the logical address is not smaller than the value stored in the special register, andwherein the selecting unit outputs PR, the value outputted from the arithmetic unit, as the physical address for the register if the logical address is smaller than the value stored in the special register.

23. The system as claimed in claim 15, wherein the compiler further adds to the program an instruction for storing in a processor a value corresponding to the number of the static registers, and compiles the program.

24. The system as claimed in claim 23, wherein the processor comprises: a special register which stores the value corresponding to the number of the static registers;an execution unit which executes the instruction for the storing in the special register the value corresponding to the number of the static registers; andan address translating unit which obtains a physical address for the register from a logical address of the register based on the value stored in the special register.

25. The system as claimed in claim 24, wherein the address translating unit comprises: an arithmetic unit which receives a value RRB corresponding to the number of current iteration times stored in a base register, LR the logical address of the register, R the value stored in the special register, S the number of the static registers, and N a sum of the R and the S, and outputs PR, a value calculated in an equation: PR={(LR+RRB−S)%(N−S)}+S, where % denotes a modulus operator;a comparing unit which compares the logical address with the value stored in the special register; anda selecting unit which selectively outputs as the physical address for the register one of PR, the value outputted from the arithmetic unit, and the logical address of the register according to a result of the comparing of the comparing unit.

26. The system as claimed in claim 25, wherein the selecting unit outputs the logical address as the physical address for the register if the logical address is smaller than the value stored in the special register, andwherein the selecting unit outputs PR, the value outputted from the arithmetic unit, as the physical address for the register if the logical address is not smaller than the value stored in the special register.